1 /* CTRC functionality */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-10/2005 4 */ 5 6 #define MODULE_BIT 0x00040000 7 8 #include "nv_std.h" 9 10 /* doing general fail-safe default setup here */ 11 //fixme: this is a _very_ basic setup, and it's preliminary... 12 status_t nv_crtc_update_fifo() 13 { 14 uint8 bytes_per_pixel = 1; 15 uint32 drain; 16 17 /* we are only using this on coldstarted cards which really need this */ 18 if ((si->settings.usebios) || (si->ps.card_type != NV05M64)) return B_OK; 19 20 /* enable access to primary head */ 21 set_crtc_owner(0); 22 23 /* set CRTC FIFO low watermark according to memory drain */ 24 switch(si->dm.space) 25 { 26 case B_CMAP8: 27 bytes_per_pixel = 1; 28 break; 29 case B_RGB15_LITTLE: 30 case B_RGB16_LITTLE: 31 bytes_per_pixel = 2; 32 break; 33 case B_RGB24_LITTLE: 34 bytes_per_pixel = 3; 35 break; 36 case B_RGB32_LITTLE: 37 bytes_per_pixel = 4; 38 break; 39 } 40 /* fixme: 41 * - I should probably include the refreshrate as well; 42 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ 43 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 44 45 /* Doesn't work for other than 32bit space (yet?) */ 46 if (si->dm.space != B_RGB32_LITTLE) 47 { 48 /* BIOS defaults */ 49 CRTCW(FIFO, 0x03); 50 CRTCW(FIFO_LWM, 0x20); 51 LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 52 return B_OK; 53 } 54 55 if (drain > (((uint32)1280) * 1024 * 4)) 56 { 57 /* set CRTC FIFO burst size for 'smaller' bursts */ 58 CRTCW(FIFO, 0x01); 59 /* Instruct CRTC to fetch new data 'earlier' */ 60 CRTCW(FIFO_LWM, 0x40); 61 LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 64\n")); 62 } 63 else 64 { 65 if (drain > (((uint32)1024) * 768 * 4)) 66 { 67 /* BIOS default */ 68 CRTCW(FIFO, 0x02); 69 /* Instruct CRTC to fetch new data 'earlier' */ 70 CRTCW(FIFO_LWM, 0x40); 71 LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 128\n")); 72 } 73 else 74 { 75 /* BIOS defaults */ 76 CRTCW(FIFO, 0x03); 77 CRTCW(FIFO_LWM, 0x20); 78 LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 79 } 80 } 81 82 return B_OK; 83 } 84 85 /* Adjust passed parameters to a valid mode line */ 86 status_t nv_crtc_validate_timing( 87 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 88 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 89 ) 90 { 91 /* horizontal */ 92 /* make all parameters multiples of 8 */ 93 *hd_e &= 0xfff8; 94 *hs_s &= 0xfff8; 95 *hs_e &= 0xfff8; 96 *ht &= 0xfff8; 97 98 /* confine to required number of bits, taking logic into account */ 99 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 100 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 101 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 102 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 103 104 /* NOTE: keep horizontal timing at multiples of 8! */ 105 /* confine to a reasonable width */ 106 if (*hd_e < 640) *hd_e = 640; 107 if (si->ps.card_type > NV04) 108 { 109 if (*hd_e > 2048) *hd_e = 2048; 110 } 111 else 112 { 113 if (*hd_e > 1920) *hd_e = 1920; 114 } 115 116 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 117 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 118 119 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 120 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 121 122 /* make sure sync pulse is not during display */ 123 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 124 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 125 126 /* correct sync pulse if it is too long: 127 * there are only 5 bits available to save this in the card registers! */ 128 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 129 130 /*vertical*/ 131 /* confine to required number of bits, taking logic into account */ 132 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 133 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 134 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 135 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 136 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 137 138 /* confine to a reasonable height */ 139 if (*vd_e < 480) *vd_e = 480; 140 if (si->ps.card_type > NV04) 141 { 142 if (*vd_e > 1536) *vd_e = 1536; 143 } 144 else 145 { 146 if (*vd_e > 1440) *vd_e = 1440; 147 } 148 149 /*if vertical total does not leave room for a sync pulse, increase it!*/ 150 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 151 152 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 153 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 154 155 /* make sure sync pulse is not during display */ 156 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 157 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 158 159 /* correct sync pulse if it is too long: 160 * there are only 4 bits available to save this in the card registers! */ 161 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 162 163 return B_OK; 164 } 165 166 /*set a mode line - inputs are in pixels*/ 167 status_t nv_crtc_set_timing(display_mode target) 168 { 169 uint8 temp; 170 171 uint32 htotal; /*total horizontal total VCLKs*/ 172 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 173 uint32 hsync_s; /*begin of horizontal sync pulse*/ 174 uint32 hsync_e; /*end of horizontal sync pulse*/ 175 uint32 hblnk_s; /*begin horizontal blanking*/ 176 uint32 hblnk_e; /*end horizontal blanking*/ 177 178 uint32 vtotal; /*total vertical total scanlines*/ 179 uint32 vdisp_e; /*end of vertical display*/ 180 uint32 vsync_s; /*begin of vertical sync pulse*/ 181 uint32 vsync_e; /*end of vertical sync pulse*/ 182 uint32 vblnk_s; /*begin vertical blanking*/ 183 uint32 vblnk_e; /*end vertical blanking*/ 184 185 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 186 187 LOG(4,("CRTC: setting timing\n")); 188 189 /* setup tuned internal modeline for flatpanel if connected and active */ 190 /* notes: 191 * - the CRTC modeline must end earlier than the panel modeline to keep correct 192 * sync going; 193 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 194 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 195 * and if it gets worse, also normal desktop output will suffer. The stripes 196 * are mainly visible at the left of the screen, over the entire screen height. */ 197 if (si->ps.tmds1_active) 198 { 199 LOG(2,("CRTC: DFP active: tuning modeline\n")); 200 201 /* horizontal timing */ 202 target.timing.h_sync_start = 203 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * 204 target.timing.h_display)) & 0xfff8; 205 206 target.timing.h_sync_end = 207 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * 208 target.timing.h_display)) & 0xfff8; 209 210 target.timing.h_total = 211 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * 212 target.timing.h_display)) & 0xfff8) - 8; 213 214 /* in native mode the CRTC needs some extra time to keep synced correctly; 215 * OTOH the overlay unit distorts if we reserve too much time! */ 216 if (target.timing.h_display == si->ps.p1_timing.h_display) 217 { 218 /* NV11 timing has different constraints than later cards */ 219 if (si->ps.card_type == NV11) 220 target.timing.h_total -= 56; 221 else 222 /* confirmed NV34 with 1680x1050 panel */ 223 target.timing.h_total -= 32; 224 } 225 226 if (target.timing.h_sync_start == target.timing.h_display) 227 target.timing.h_sync_start += 8; 228 if (target.timing.h_sync_end == target.timing.h_total) 229 target.timing.h_sync_end -= 8; 230 231 /* vertical timing */ 232 target.timing.v_sync_start = 233 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * 234 target.timing.v_display)); 235 236 target.timing.v_sync_end = 237 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * 238 target.timing.v_display)); 239 240 target.timing.v_total = 241 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * 242 target.timing.v_display)) - 1; 243 244 if (target.timing.v_sync_start == target.timing.v_display) 245 target.timing.v_sync_start += 1; 246 if (target.timing.v_sync_end == target.timing.v_total) 247 target.timing.v_sync_end -= 1; 248 249 /* disable GPU scaling testmode so automatic scaling will be done */ 250 DACW(FP_DEBUG1, 0); 251 } 252 253 /* Modify parameters as required by standard VGA */ 254 htotal = ((target.timing.h_total >> 3) - 5); 255 hdisp_e = ((target.timing.h_display >> 3) - 1); 256 hblnk_s = hdisp_e; 257 hblnk_e = (htotal + 4); 258 hsync_s = (target.timing.h_sync_start >> 3); 259 hsync_e = (target.timing.h_sync_end >> 3); 260 261 vtotal = target.timing.v_total - 2; 262 vdisp_e = target.timing.v_display - 1; 263 vblnk_s = vdisp_e; 264 vblnk_e = (vtotal + 1); 265 vsync_s = target.timing.v_sync_start; 266 vsync_e = target.timing.v_sync_end; 267 268 /* prevent memory adress counter from being reset (linecomp may not occur) */ 269 linecomp = target.timing.v_display; 270 271 /* enable access to primary head */ 272 set_crtc_owner(0); 273 274 /* Note for laptop and DVI flatpanels: 275 * CRTC timing has a seperate set of registers from flatpanel timing. 276 * The flatpanel timing registers have scaling registers that are used to match 277 * these two modelines. */ 278 { 279 LOG(4,("CRTC: Setting full timing...\n")); 280 281 /* log the mode that will be set */ 282 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 283 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 284 285 /* actually program the card! */ 286 /* unlock CRTC registers at index 0-7 */ 287 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); 288 /* horizontal standard VGA regs */ 289 CRTCW(HTOTAL, (htotal & 0xff)); 290 CRTCW(HDISPE, (hdisp_e & 0xff)); 291 CRTCW(HBLANKS, (hblnk_s & 0xff)); 292 /* also unlock vertical retrace registers in advance */ 293 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 294 CRTCW(HSYNCS, (hsync_s & 0xff)); 295 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 296 297 /* vertical standard VGA regs */ 298 CRTCW(VTOTAL, (vtotal & 0xff)); 299 CRTCW(OVERFLOW, 300 ( 301 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 302 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 303 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 304 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 305 )); 306 CRTCW(PRROWSCN, 0x00); /* not used */ 307 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 308 CRTCW(VSYNCS, (vsync_s & 0xff)); 309 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 310 CRTCW(VDISPE, (vdisp_e & 0xff)); 311 CRTCW(VBLANKS, (vblnk_s & 0xff)); 312 CRTCW(VBLANKE, (vblnk_e & 0xff)); 313 CRTCW(LINECOMP, (linecomp & 0xff)); 314 315 /* horizontal extended regs */ 316 //fixme: we reset bit4. is this correct?? 317 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | 318 ( 319 ((htotal & 0x100) >> (8 - 0)) | 320 ((hdisp_e & 0x100) >> (8 - 1)) | 321 ((hblnk_s & 0x100) >> (8 - 2)) | 322 ((hsync_s & 0x100) >> (8 - 3)) 323 )); 324 325 /* (mostly) vertical extended regs */ 326 CRTCW(LSR, 327 ( 328 ((vtotal & 0x400) >> (10 - 0)) | 329 ((vdisp_e & 0x400) >> (10 - 1)) | 330 ((vsync_s & 0x400) >> (10 - 2)) | 331 ((vblnk_s & 0x400) >> (10 - 3)) | 332 ((hblnk_e & 0x040) >> (6 - 4)) 333 //fixme: we still miss one linecomp bit!?! is this it?? 334 //| ((linecomp & 0x400) >> 3) 335 )); 336 337 /* more vertical extended regs (on GeForce cards only) */ 338 if (si->ps.card_arch >= NV10A) 339 { 340 CRTCW(EXTRA, 341 ( 342 ((vtotal & 0x800) >> (11 - 0)) | 343 ((vdisp_e & 0x800) >> (11 - 2)) | 344 ((vsync_s & 0x800) >> (11 - 4)) | 345 ((vblnk_s & 0x800) >> (11 - 6)) 346 //fixme: do we miss another linecomp bit!?! 347 )); 348 } 349 350 /* setup 'large screen' mode */ 351 if (target.timing.h_display >= 1280) 352 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); 353 else 354 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); 355 356 /* setup HSYNC & VSYNC polarity */ 357 LOG(2,("CRTC: sync polarity: ")); 358 temp = NV_REG8(NV8_MISCR); 359 if (target.timing.flags & B_POSITIVE_HSYNC) 360 { 361 LOG(2,("H:pos ")); 362 temp &= ~0x40; 363 } 364 else 365 { 366 LOG(2,("H:neg ")); 367 temp |= 0x40; 368 } 369 if (target.timing.flags & B_POSITIVE_VSYNC) 370 { 371 LOG(2,("V:pos ")); 372 temp &= ~0x80; 373 } 374 else 375 { 376 LOG(2,("V:neg ")); 377 temp |= 0x80; 378 } 379 NV_REG8(NV8_MISCW) = temp; 380 381 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 382 } 383 384 /* always disable interlaced operation */ 385 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 386 CRTCW(INTERLACE, 0xff); 387 388 /* disable CRTC slaved mode unless a panel is in use */ 389 // fixme: this kills TVout when it was in use... 390 if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); 391 392 /* setup flatpanel if connected and active */ 393 if (si->ps.tmds1_active) 394 { 395 uint32 iscale_x, iscale_y; 396 397 /* calculate inverse scaling factors used by hardware in 20.12 format */ 398 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); 399 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); 400 401 /* unblock flatpanel timing programming (or something like that..) */ 402 CRTCW(FP_HTIMING, 0); 403 CRTCW(FP_VTIMING, 0); 404 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); 405 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); 406 407 /* enable full width visibility on flatpanel */ 408 DACW(FP_HVALID_S, 0); 409 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); 410 /* enable full height visibility on flatpanel */ 411 DACW(FP_VVALID_S, 0); 412 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); 413 414 /* nVidia cards support upscaling except on ??? */ 415 /* NV11 cards can upscale after all! */ 416 if (0)//si->ps.card_type == NV11) 417 { 418 /* disable last fetched line limiting */ 419 DACW(FP_DEBUG2, 0x00000000); 420 /* inform panel to scale if needed */ 421 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 422 { 423 LOG(2,("CRTC: DFP needs to do scaling\n")); 424 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 425 } 426 else 427 { 428 LOG(2,("CRTC: no scaling for DFP needed\n")); 429 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 430 } 431 } 432 else 433 { 434 float dm_aspect; 435 436 LOG(2,("CRTC: GPU scales for DFP if needed\n")); 437 438 /* calculate display mode aspect */ 439 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 440 441 /* limit last fetched line if vertical scaling is done */ 442 if (iscale_y != (1 << 12)) 443 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 444 else 445 DACW(FP_DEBUG2, 0x00000000); 446 447 /* inform panel not to scale */ 448 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 449 450 /* GPU scaling is automatically setup by hardware, so only modify this 451 * scalingfactor for non 4:3 (1.33) aspect panels; 452 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 453 454 /* correct for widescreen panels relative to mode... 455 * (so if panel is more widescreen than mode being set) */ 456 /* BTW: known widescreen panels: 457 * 1280 x 800 (1.60), 458 * 1440 x 900 (1.60), 459 * 1680 x 1050 (1.60), 460 * 1920 x 1200 (1.60). */ 461 /* known 4:3 aspect non-standard resolution panels: 462 * 1400 x 1050 (1.33). */ 463 /* NOTE: 464 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 465 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) 466 { 467 uint16 diff; 468 469 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); 470 471 /* X-scaling should be the same as Y-scaling */ 472 iscale_x = iscale_y; 473 /* enable testmode (b12) and program modified X-scaling factor */ 474 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 475 /* center/cut-off left and right side of screen */ 476 diff = ((si->ps.p1_timing.h_display - 477 ((target.timing.h_display * (1 << 12)) / iscale_x)) 478 / 2); 479 DACW(FP_HVALID_S, diff); 480 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); 481 } 482 /* correct for portrait panels... */ 483 /* NOTE: 484 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 485 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) 486 { 487 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); 488 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 489 } 490 } 491 492 /* do some logging.. */ 493 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 494 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 495 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 496 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 497 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 498 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 499 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); 500 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); 501 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); 502 } 503 504 return B_OK; 505 } 506 507 status_t nv_crtc_depth(int mode) 508 { 509 uint8 viddelay = 0; 510 uint32 genctrl = 0; 511 512 /* set VCLK scaling */ 513 switch(mode) 514 { 515 case BPP8: 516 viddelay = 0x01; 517 /* genctrl b4 & b5 reset: 'direct mode' */ 518 genctrl = 0x00101100; 519 break; 520 case BPP15: 521 viddelay = 0x02; 522 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 523 genctrl = 0x00100130; 524 break; 525 case BPP16: 526 viddelay = 0x02; 527 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 528 genctrl = 0x00101130; 529 break; 530 case BPP24: 531 viddelay = 0x03; 532 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 533 genctrl = 0x00100130; 534 break; 535 case BPP32: 536 viddelay = 0x03; 537 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 538 genctrl = 0x00101130; 539 break; 540 } 541 /* enable access to primary head */ 542 set_crtc_owner(0); 543 544 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); 545 DACW(GENCTRL, genctrl); 546 547 return B_OK; 548 } 549 550 status_t nv_crtc_dpms(bool display, bool h, bool v) 551 { 552 uint8 temp; 553 554 LOG(4,("CRTC: setting DPMS: ")); 555 556 /* enable access to primary head */ 557 set_crtc_owner(0); 558 559 /* start synchronous reset: required before turning screen off! */ 560 SEQW(RESET, 0x01); 561 562 temp = SEQR(CLKMODE); 563 if (display) 564 { 565 /* turn screen on */ 566 SEQW(CLKMODE, (temp & ~0x20)); 567 568 /* end synchronous reset because display should be enabled */ 569 SEQW(RESET, 0x03); 570 571 if (si->ps.tmds1_active && !si->ps.laptop) 572 { 573 /* restore original panelsync and panel-enable */ 574 uint32 panelsync = 0x00000000; 575 if(si->ps.p1_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 576 if(si->ps.p1_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 577 /* display enable polarity (not an official flag) */ 578 if(si->ps.p1_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 579 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 580 581 //fixme?: looks like we don't need this after all: 582 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 583 * internal transmitters... */ 584 /* note: 585 * the powerbits in this register are hardwired to the DVI connectors, 586 * instead of to the DACs! (confirmed NV34) */ 587 //fixme... 588 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); 589 /* ... and powerup external TMDS transmitter if it exists */ 590 /* (confirmed OK on NV28 and NV34) */ 591 //CRTCW(0x59, (CRTCR(0x59) | 0x01)); 592 } 593 594 LOG(4,("display on, ")); 595 } 596 else 597 { 598 /* turn screen off */ 599 SEQW(CLKMODE, (temp | 0x20)); 600 601 if (si->ps.tmds1_active && !si->ps.laptop) 602 { 603 /* shutoff panelsync and disable panel */ 604 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 605 606 //fixme?: looks like we don't need this after all: 607 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 608 * internal transmitters... */ 609 /* note: 610 * the powerbits in this register are hardwired to the DVI connectors, 611 * instead of to the DACs! (confirmed NV34) */ 612 //fixme... 613 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); 614 /* ... and powerdown external TMDS transmitter if it exists */ 615 /* (confirmed OK on NV28 and NV34) */ 616 //CRTCW(0x59, (CRTCR(0x59) & 0xfe)); 617 } 618 619 LOG(4,("display off, ")); 620 } 621 622 if (h) 623 { 624 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); 625 LOG(4,("hsync enabled, ")); 626 } 627 else 628 { 629 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); 630 LOG(4,("hsync disabled, ")); 631 } 632 if (v) 633 { 634 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 635 LOG(4,("vsync enabled\n")); 636 } 637 else 638 { 639 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); 640 LOG(4,("vsync disabled\n")); 641 } 642 643 return B_OK; 644 } 645 646 status_t nv_crtc_set_display_pitch() 647 { 648 uint32 offset; 649 650 LOG(4,("CRTC: setting card pitch (offset between lines)\n")); 651 652 /* figure out offset value hardware needs */ 653 offset = si->fbc.bytes_per_row / 8; 654 655 LOG(2,("CRTC: offset register set to: $%04x\n", offset)); 656 657 /* enable access to primary head */ 658 set_crtc_owner(0); 659 660 /* program the card */ 661 CRTCW(PITCHL, (offset & 0x00ff)); 662 CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 663 664 return B_OK; 665 } 666 667 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) 668 { 669 uint8 temp; 670 uint32 timeout = 0; 671 672 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); 673 674 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 675 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); 676 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); 677 678 /* we might have no retraces during setmode! */ 679 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 680 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 681 (timeout < (25000/10))) 682 { 683 /* don't snooze much longer or retrace might get missed! */ 684 snooze(10); 685 timeout++; 686 } 687 688 /* enable access to primary head */ 689 set_crtc_owner(0); 690 691 if (si->ps.card_arch == NV04A) 692 { 693 /* upto 32Mb RAM adressing: must be used this way on pre-NV10! */ 694 695 /* set standard registers */ 696 /* (NVidia: startadress in 32bit words (b2 - b17) */ 697 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2)); 698 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10)); 699 700 /* set extended registers */ 701 /* NV4 extended bits: (b18-22) */ 702 temp = (CRTCR(REPAINT0) & 0xe0); 703 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18))); 704 /* NV4 extended bits: (b23-24) */ 705 temp = (CRTCR(HEB) & 0x9f); 706 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18))); 707 } 708 else 709 { 710 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 711 /* NOTE: 712 * While this register also exists on pre-NV10 cards, it will 713 * wrap-around at 16Mb boundaries!! */ 714 715 /* 30bit adress in 32bit words */ 716 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 717 } 718 719 /* set NV4/NV10 byte adress: (b0 - 1) */ 720 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1)); 721 722 return B_OK; 723 } 724 725 status_t nv_crtc_cursor_init() 726 { 727 int i; 728 uint32 * fb; 729 /* cursor bitmap will be stored at the start of the framebuffer */ 730 const uint32 curadd = 0; 731 732 /* enable access to primary head */ 733 set_crtc_owner(0); 734 735 /* set cursor bitmap adress ... */ 736 if ((si->ps.card_arch == NV04A) || (si->ps.laptop)) 737 { 738 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 739 740 /* cursorbitmap must start on 2Kbyte boundary: */ 741 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 742 CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9)); 743 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 744 CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 745 /* set adress bit24-31 */ 746 CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24)); 747 } 748 else 749 { 750 /* upto 4Gb RAM adressing: 751 * can be used on NV10 and later (except for 'Go' cards)! */ 752 /* NOTE: 753 * This register does not exist on pre-NV10 and 'Go' cards. */ 754 755 /* cursorbitmap must still start on 2Kbyte boundary: */ 756 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); 757 } 758 759 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 760 761 /*clear cursor*/ 762 fb = (uint32 *) si->framebuffer + curadd; 763 for (i=0;i<(2048/4);i++) 764 { 765 fb[i]=0; 766 } 767 768 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 769 NV_REG32(NV32_CURCONF) = 0x02000100; 770 771 /* activate hardware-sync between cursor updates and vertical retrace where 772 * available */ 773 if (si->ps.card_arch >= NV10A) 774 DACW(NV10_CURSYNC, (DACR(NV10_CURSYNC) | 0x02000000)); 775 776 /* activate hardware cursor */ 777 nv_crtc_cursor_show(); 778 779 return B_OK; 780 } 781 782 status_t nv_crtc_cursor_show() 783 { 784 LOG(4,("CRTC: enabling cursor\n")); 785 786 /* enable access to CRTC1 on dualhead cards */ 787 set_crtc_owner(0); 788 789 /* b0 = 1 enables cursor */ 790 CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); 791 792 /* workaround for hardware bug confirmed existing on NV43: 793 * Cursor visibility is not updated without a position update if its hardware 794 * retrace sync is enabled. */ 795 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 796 797 return B_OK; 798 } 799 800 status_t nv_crtc_cursor_hide() 801 { 802 LOG(4,("CRTC: disabling cursor\n")); 803 804 /* enable access to primary head */ 805 set_crtc_owner(0); 806 807 /* b0 = 0 disables cursor */ 808 CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); 809 810 /* workaround for hardware bug confirmed existing on NV43: 811 * Cursor visibility is not updated without a position update if its hardware 812 * retrace sync is enabled. */ 813 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 814 815 return B_OK; 816 } 817 818 /*set up cursor shape*/ 819 status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask) 820 { 821 int x, y; 822 uint8 b; 823 uint16 *cursor; 824 uint16 pixel; 825 826 /* get a pointer to the cursor */ 827 cursor = (uint16*) si->framebuffer; 828 829 /* draw the cursor */ 830 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 831 for (y = 0; y < 16; y++) 832 { 833 b = 0x80; 834 for (x = 0; x < 8; x++) 835 { 836 /* preset transparant */ 837 pixel = 0x0000; 838 /* set white if requested */ 839 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 840 /* set black if requested */ 841 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 842 /* set invert if requested */ 843 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 844 /* place the pixel in the bitmap */ 845 cursor[x + (y * 32)] = pixel; 846 b >>= 1; 847 } 848 xorMask++; 849 andMask++; 850 b = 0x80; 851 for (; x < 16; x++) 852 { 853 /* preset transparant */ 854 pixel = 0x0000; 855 /* set white if requested */ 856 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 857 /* set black if requested */ 858 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 859 /* set invert if requested */ 860 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 861 /* place the pixel in the bitmap */ 862 cursor[x + (y * 32)] = pixel; 863 b >>= 1; 864 } 865 xorMask++; 866 andMask++; 867 } 868 869 return B_OK; 870 } 871 872 /* position the cursor */ 873 status_t nv_crtc_cursor_position(uint16 x, uint16 y) 874 { 875 /* the cursor position is updated during retrace by card hardware except for 876 * pre-GeForce cards */ 877 if (si->ps.card_arch < NV10A) 878 { 879 uint16 yhigh; 880 881 /* make sure we are beyond the first line of the cursorbitmap being drawn during 882 * updating the position to prevent distortions: no double buffering feature */ 883 /* Note: 884 * we need to return as quick as possible or some apps will exhibit lagging.. */ 885 886 /* read the old cursor Y position */ 887 yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16); 888 /* make sure we will wait until we are below both the old and new Y position: 889 * visible cursorbitmap drawing needs to be done at least... */ 890 if (y > yhigh) yhigh = y; 891 892 if (yhigh < (si->dm.timing.v_display - 16)) 893 { 894 /* we have vertical lines below old and new cursorposition to spare. So we 895 * update the cursor postion 'mid-screen', but below that area. */ 896 while (((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) 897 { 898 snooze(10); 899 } 900 } 901 else 902 { 903 /* no room to spare, just wait for retrace (is relatively slow) */ 904 while ((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) 905 { 906 /* don't snooze much longer or retrace might get missed! */ 907 snooze(10); 908 } 909 } 910 } 911 912 /* update cursorposition */ 913 DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 914 915 return B_OK; 916 } 917 918 status_t nv_crtc_stop_tvout(void) 919 { 920 /* enable access to primary head */ 921 set_crtc_owner(0); 922 923 /* just to be sure Vsync is _really_ enabled */ 924 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 925 926 /* wait for one image to be generated to make sure VGA has kicked in and is 927 * running OK before continuing... 928 * (Kicking in will fail often if we do not wait here) */ 929 /* Note: 930 * The used CRTC's Vsync is required to be enabled here. The DPMS state 931 * programming in the driver makes sure this is the case. 932 * (except for driver startup: see nv_general.c.) */ 933 934 /* make sure we are 'in' active VGA picture */ 935 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 936 /* wait for next vertical retrace start on VGA */ 937 while (!(NV_REG8(NV8_INSTAT1) & 0x08)) snooze(1); 938 /* now wait until we are 'in' active VGA picture again */ 939 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 940 941 942 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ 943 if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03)); 944 945 /* CAUTION: 946 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 947 * write actions do succeed ... 948 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 949 950 /* setup TVencoder connection */ 951 /* b1-0 = %00: encoder type is SLAVE; 952 * b24 = 1: VIP datapos is b0-7 */ 953 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 954 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 955 DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000003) | 0x01000000)); 956 957 /* tell GPU to use pixelclock from internal source instead of using TVencoder */ 958 if (si->ps.secondary_head) 959 DACW(PLLSEL, 0x30000f00); 960 else 961 DACW(PLLSEL, 0x10000700); 962 963 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 964 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 965 CRTCW(TREG, 0x00); 966 967 /* select panel encoder, not TV encoder if needed (b0 = 1). 968 * Note: 969 * Both are devices (often) using the CRTC in slaved mode. */ 970 if (si->ps.slaved_tmds1) CRTCW(LCD, (CRTCR(LCD) | 0x01)); 971 972 return B_OK; 973 } 974 975 status_t nv_crtc_start_tvout(void) 976 { 977 /* enable access to primary head */ 978 set_crtc_owner(0); 979 980 /* CAUTION: 981 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 982 * write actions do succeed ... 983 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 984 985 /* setup TVencoder connection */ 986 /* b1-0 = %01: encoder type is MASTER; 987 * b24 = 1: VIP datapos is b0-7 */ 988 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 989 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 990 DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001)); 991 992 /* tell GPU to use pixelclock from TVencoder instead of using internal source */ 993 /* (nessecary or display will 'shiver' on both TV and VGA.) */ 994 if (si->ps.secondary_head) 995 DACW(PLLSEL, 0x20030f00); 996 else 997 DACW(PLLSEL, 0x00030700); 998 999 /* Set overscan color to 'black' */ 1000 /* note: 1001 * Change this instruction for a visible overscan color if you're trying to 1002 * center the output on TV. Use it as a guide-'line' then ;-) */ 1003 ATBW(OSCANCOLOR, 0x00); 1004 1005 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ 1006 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xc7) | 0x80)); 1007 /* select TV encoder, not panel encoder (b0 = 0). 1008 * Note: 1009 * Both are devices (often) using the CRTC in slaved mode. */ 1010 CRTCW(LCD, (CRTCR(LCD) & 0xfe)); 1011 1012 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 1013 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 1014 CRTCW(TREG, 0x80); 1015 1016 return B_OK; 1017 } 1018