1 /* NV Acceleration functions */ 2 /* Author: 3 Rudolf Cornelissen 8/2003-12/2003. 4 5 This code was possible thanks to the Linux NV driver. 6 */ 7 8 #define MODULE_BIT 0x00080000 9 10 #include "nv_std.h" 11 12 /*acceleration notes*/ 13 14 /*functions Be's app_server uses: 15 fill span (horizontal only) 16 fill rectangle (these 2 are very similar) 17 invert rectangle 18 blit 19 */ 20 21 status_t nv_acc_wait_idle() 22 { 23 /* wait until engine completely idle */ 24 while (ACCR(STATUS)) 25 { 26 /* snooze a bit so I do not hammer the bus */ 27 snooze (100); 28 } 29 30 return B_OK; 31 } 32 33 /* AFAIK this must be done for every new screenmode. 34 * Engine required init. */ 35 status_t nv_acc_init() 36 { 37 uint16 cnt; 38 39 /* setup PTIMER: */ 40 /* set timer numerator to 8 (in b0-15) */ 41 ACCW(PT_NUMERATOR, 0x00000008); 42 /* set timer denominator to 3 (in b0-15) */ 43 ACCW(PT_DENOMINATR, 0x00000003); 44 /* disable timer-alarm INT requests (b0) */ 45 ACCW(PT_INTEN, 0x00000000); 46 /* reset timer-alarm INT status bit (b0) */ 47 ACCW(PT_INTSTAT, 0xffffffff); 48 49 /* enable PRAMIN write access on pre NV10 before programming it! */ 50 if (si->ps.card_arch == NV04A) 51 { 52 /* set framebuffer config: type = notiling, PRAMIN write access enabled */ 53 NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; 54 } 55 56 /*** PFIFO ***/ 57 /* (setup caches) */ 58 /* disable caches reassign */ 59 ACCW(PF_CACHES, 0x00000000); 60 /* cache1 push0 access disabled */ 61 ACCW(PF_CACH1_PSH0, 0x00000000); 62 /* cache1 pull0 access disabled */ 63 ACCW(PF_CACH1_PUL0, 0x00000000); 64 /* cache1 push1 mode = pio */ 65 ACCW(PF_CACH1_PSH1, 0x00000000); 66 /* cache1 DMA instance adress = 0 (b0-15) */ 67 ACCW(PF_CACH1_DMAI, 0x00000000); 68 /* cache0 push0 access disabled */ 69 ACCW(PF_CACH0_PSH0, 0x00000000); 70 /* cache0 pull0 access disabled */ 71 ACCW(PF_CACH0_PUL0, 0x00000000); 72 /* RAM HT (hash table(?)) baseadress = $10000 (b4-8), size = 4k, 73 * search = 128 (byte offset between hash 'sets'(?)) */ 74 /* (note: so(?) HT base is $00710000, last is $00710fff) */ 75 ACCW(PF_RAMHT, 0x03000100); 76 /* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */ 77 /* (note: so(?) FC base is $00711000, last is $007111ff) */ 78 ACCW(PF_RAMFC, 0x00000110); 79 /* RAM RO baseadress = $11200 (b1-8), size = 0.5k */ 80 /* (note: so(?) RO base is $00711200, last is $007113ff) */ 81 /* (note also: 82 * This means(?) the PRAMIN CTX registers are accessible from base $00711400) */ 83 ACCW(PF_RAMRO, 0x00000112); 84 /* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */ 85 ACCW(PF_SIZE, 0x0000ffff); 86 /* cache1 hash instance = $ffff (b0-15) */ 87 ACCW(PF_CACH1_HASH, 0x0000ffff); 88 /* disable all PFIFO INTs */ 89 ACCW(PF_INTEN, 0x00000000); 90 /* reset all PFIFO INT status bits */ 91 ACCW(PF_INTSTAT, 0xffffffff); 92 /* cache0 pull0 engine = acceleration engine (graphics) */ 93 ACCW(PF_CACH0_PUL1, 0x00000001); 94 /* cache1 push0 access enabled */ 95 ACCW(PF_CACH1_PSH0, 0x00000001); 96 /* cache1 pull0 access enabled */ 97 ACCW(PF_CACH1_PUL0, 0x00000001); 98 /* cache1 pull1 engine = acceleration engine (graphics) */ 99 ACCW(PF_CACH1_PUL1, 0x00000001); 100 /* enable PFIFO caches reassign */ 101 ACCW(PF_CACHES, 0x00000001); 102 103 /*** PRAMIN ***/ 104 /* RAMHT space (hash-table(?)) */ 105 /* (first set) */ 106 ACCW(HT_HANDL_00, 0x80000010); /* 32bit handle */ 107 ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */ 108 ACCW(HT_HANDL_01, 0x80000011); /* 32bit handle */ 109 ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */ 110 ACCW(HT_HANDL_02, 0x80000012); /* 32bit handle */ 111 ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */ 112 ACCW(HT_HANDL_03, 0x80000013); /* 32bit handle */ 113 ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */ 114 ACCW(HT_HANDL_04, 0x80000014); /* 32bit handle */ 115 ACCW(HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */ 116 ACCW(HT_HANDL_05, 0x80000015); /* 32bit handle */ 117 ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */ 118 ACCW(HT_HANDL_06, 0x80000016); /* 32bit handle */ 119 if (si->ps.card_arch != NV04A) 120 ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */ 121 else 122 ACCW(HT_VALUE_06, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */ 123 /* (second set) */ 124 ACCW(HT_HANDL_10, 0x80000000); /* 32bit handle */ 125 ACCW(HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */ 126 ACCW(HT_HANDL_11, 0x80000001); /* 32bit handle */ 127 ACCW(HT_VALUE_11, 0x80011143); /* instance $1143, engine = acc engine, CHID = $00 */ 128 ACCW(HT_HANDL_12, 0x80000002); /* 32bit handle */ 129 ACCW(HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */ 130 ACCW(HT_HANDL_13, 0x80000003); /* 32bit handle */ 131 ACCW(HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */ 132 ACCW(HT_HANDL_14, 0x80000004); /* 32bit handle */ 133 ACCW(HT_VALUE_14, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */ 134 ACCW(HT_HANDL_15, 0x80000005); /* 32bit handle */ 135 ACCW(HT_VALUE_15, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */ 136 ACCW(HT_HANDL_16, 0x80000006); /* 32bit handle */ 137 ACCW(HT_VALUE_16, 0x8001114e); /* instance $114e, engine = acc engine, CHID = $00 */ 138 if (si->ps.card_arch != NV04A) 139 { 140 ACCW(HT_HANDL_17, 0x80000007); /* 32bit handle */ 141 ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */ 142 } 143 /* program CTX registers: CTX1 is mostly done later (colorspace dependant) */ 144 /* (setup 'root' set first) */ 145 ACCW(PR_CTX0_R, 0x00003000); /* NVclass = NVroot, chromakey and userclip enabled */ 146 /* fixme: CTX1_R should reflect RAM amount? (no influence on current used functions) */ 147 ACCW(PR_CTX1_R, 0x01ffffff); /* cardmemory mask(?) */ 148 ACCW(PR_CTX2_R, 0x00000002); /* ??? */ 149 ACCW(PR_CTX3_R, 0x00000002); /* ??? */ 150 /* (setup set '0') */ 151 ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */ 152 ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */ 153 ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */ 154 /* (setup set '1') */ 155 ACCW(PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */ 156 ACCW(PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */ 157 ACCW(PR_CTX3_1, 0x00000000); /* method traps disabled */ 158 /* (setup set '2') */ 159 ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */ 160 ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */ 161 ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */ 162 /* (setup set '3') */ 163 ACCW(PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian */ 164 ACCW(PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid */ 165 ACCW(PR_CTX3_3, 0x00000000); /* method traps disabled */ 166 /* (setup set '4') */ 167 ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */ 168 ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */ 169 ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */ 170 /* (setup set '5') */ 171 ACCW(PR_CTX0_5, 0x0100804b); /* NVclass $04b, patchcfg ROP_AND, nv10+: little endian */ 172 ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */ 173 ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */ 174 /* (setup set '6') */ 175 ACCW(PR_CTX0_6, 0x0100a048); /* NVclass $048, patchcfg ROP_AND, userclip enable, 176 * nv10+: little endian */ 177 ACCW(PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */ 178 ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 179 ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */ 180 /* (setup set '7') */ 181 if (si->ps.card_arch != NV04A) 182 ACCW(PR_CTX0_7, 0x0300a094); /* NVclass $094, patchcfg ROP_AND, userclip enable, 183 * context surface0 valid, nv10+: little endian */ 184 else 185 ACCW(PR_CTX0_7, 0x0300a054); /* NVclass $054, patchcfg ROP_AND, userclip enable, 186 * context surface0 valid */ 187 ACCW(PR_CTX1_7, 0x00000d01); /* format is A8RGB24, MSB mono */ 188 ACCW(PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 189 ACCW(PR_CTX3_7, 0x00000000); /* method traps disabled */ 190 /* (setup set '8') */ 191 if (si->ps.card_arch != NV04A) 192 ACCW(PR_CTX0_8, 0x0300a095); /* NVclass $095, patchcfg ROP_AND, userclip enable, 193 * context surface0 valid, nv10+: little endian */ 194 else 195 ACCW(PR_CTX0_8, 0x0300a055); /* NVclass $055, patchcfg ROP_AND, userclip enable, 196 * context surface0 valid */ 197 ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */ 198 ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 199 ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */ 200 /* (setup set '9') */ 201 ACCW(PR_CTX0_9, 0x00000058); /* NVclass $058, nv10+: little endian */ 202 ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 203 ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */ 204 /* (setup set 'A') */ 205 ACCW(PR_CTX0_A, 0x00000059); /* NVclass $059, nv10+: little endian */ 206 ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 207 ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */ 208 /* (setup set 'B') */ 209 ACCW(PR_CTX0_B, 0x0000005a); /* NVclass $05a, nv10+: little endian */ 210 ACCW(PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 211 ACCW(PR_CTX3_B, 0x00000000); /* method traps disabled */ 212 /* (setup set 'C') */ 213 ACCW(PR_CTX0_C, 0x0000005b); /* NVclass $05b, nv10+: little endian */ 214 ACCW(PR_CTX2_C, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 215 ACCW(PR_CTX3_C, 0x00000000); /* method traps disabled */ 216 /* (setup set 'D') */ 217 if (si->ps.card_arch != NV04A) 218 ACCW(PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */ 219 else 220 ACCW(PR_CTX0_D, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, 221 * context surface0 valid */ 222 ACCW(PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 223 ACCW(PR_CTX3_D, 0x00000000); /* method traps disabled */ 224 /* (setup set 'E' if needed) */ 225 if (si->ps.card_arch != NV04A) 226 { 227 ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, 228 * context surface0 valid, nv10+: little endian */ 229 ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */ 230 ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */ 231 } 232 233 /*** PGRAPH ***/ 234 if (si->ps.card_arch != NV04A) 235 { 236 /* set resetstate for most function blocks */ 237 ACCW(DEBUG0, 0x0003ffff); 238 /* init some function blocks */ 239 ACCW(DEBUG1, 0x00118701); 240 ACCW(DEBUG2, 0x24f82ad9); 241 ACCW(DEBUG3, 0x55de0030); 242 /* end resetstate for the function blocks */ 243 ACCW(DEBUG0, 0x00000000); 244 /* disable specific functions */ 245 ACCW(NV10_DEBUG4, 0); 246 } 247 else 248 { 249 /* init some function blocks */ 250 ACCW(DEBUG0, 0x1231c001); 251 ACCW(DEBUG1, 0x72111101); 252 ACCW(DEBUG2, 0x11d5f071); 253 ACCW(DEBUG3, 0x10d4ff31); 254 } 255 256 /* reset all cache sets */ 257 ACCW(CACHE1_1, 0); 258 ACCW(CACHE1_2, 0); 259 ACCW(CACHE1_3, 0); 260 ACCW(CACHE1_4, 0); 261 ACCW(CACHE1_5, 0); 262 ACCW(CACHE2_1, 0); 263 ACCW(CACHE2_2, 0); 264 ACCW(CACHE2_3, 0); 265 ACCW(CACHE2_4, 0); 266 ACCW(CACHE2_5, 0); 267 ACCW(CACHE3_1, 0); 268 ACCW(CACHE3_2, 0); 269 ACCW(CACHE3_3, 0); 270 ACCW(CACHE3_4, 0); 271 ACCW(CACHE3_5, 0); 272 ACCW(CACHE4_1, 0); 273 ACCW(CACHE4_2, 0); 274 ACCW(CACHE4_3, 0); 275 ACCW(CACHE4_4, 0); 276 ACCW(CACHE4_5, 0); 277 if (si->ps.card_arch != NV04A) 278 ACCW(NV10_CACHE5_1, 0); 279 ACCW(CACHE5_2, 0); 280 ACCW(CACHE5_3, 0); 281 ACCW(CACHE5_4, 0); 282 ACCW(CACHE5_5, 0); 283 if (si->ps.card_arch != NV04A) 284 ACCW(NV10_CACHE6_1, 0); 285 ACCW(CACHE6_2, 0); 286 ACCW(CACHE6_3, 0); 287 ACCW(CACHE6_4, 0); 288 ACCW(CACHE6_5, 0); 289 if (si->ps.card_arch != NV04A) 290 ACCW(NV10_CACHE7_1, 0); 291 ACCW(CACHE7_2, 0); 292 ACCW(CACHE7_3, 0); 293 ACCW(CACHE7_4, 0); 294 ACCW(CACHE7_5, 0); 295 if (si->ps.card_arch != NV04A) 296 ACCW(NV10_CACHE8_1, 0); 297 ACCW(CACHE8_2, 0); 298 ACCW(CACHE8_3, 0); 299 ACCW(CACHE8_4, 0); 300 ACCW(CACHE8_5, 0); 301 302 if (si->ps.card_arch != NV04A) 303 { 304 /* reset (disable) context switch stuff */ 305 ACCW(NV10_CTX_SW1, 0); 306 ACCW(NV10_CTX_SW2, 0); 307 ACCW(NV10_CTX_SW3, 0); 308 ACCW(NV10_CTX_SW4, 0); 309 ACCW(NV10_CTX_SW5, 0); 310 } 311 312 /* setup accesible card memory range for acc engine */ 313 ACCW(BBASE0, 0x00000000); 314 ACCW(BBASE1, 0x00000000); 315 ACCW(BBASE2, 0x00000000); 316 ACCW(BBASE3, 0x00000000); 317 ACCW(BLIMIT0, ((si->ps.memory_size << 20) - 1)); 318 ACCW(BLIMIT1, ((si->ps.memory_size << 20) - 1)); 319 ACCW(BLIMIT2, ((si->ps.memory_size << 20) - 1)); 320 ACCW(BLIMIT3, ((si->ps.memory_size << 20) - 1)); 321 if (si->ps.card_arch >= NV10A) 322 { 323 ACCW(NV10_BBASE4, 0x00000000); 324 ACCW(NV10_BBASE5, 0x00000000); 325 ACCW(NV10_BLIMIT4, ((si->ps.memory_size << 20) - 1)); 326 ACCW(NV10_BLIMIT5, ((si->ps.memory_size << 20) - 1)); 327 } 328 if (si->ps.card_arch >= NV20A) 329 { 330 /* fixme(?): assuming more BLIMIT registers here: Then how about BBASE6-9? 331 * (linux fixed value 'BLIMIT6-9' 0x01ffffff) */ 332 ACCW(NV20_BLIMIT6, ((si->ps.memory_size << 20) - 1)); 333 ACCW(NV20_BLIMIT7, ((si->ps.memory_size << 20) - 1)); 334 ACCW(NV20_BLIMIT8, ((si->ps.memory_size << 20) - 1)); 335 ACCW(NV20_BLIMIT9, ((si->ps.memory_size << 20) - 1)); 336 } 337 338 /* disable all acceleration engine INT reguests */ 339 ACCW(ACC_INTE, 0x00000000); 340 341 /* reset all acceration engine INT status bits */ 342 ACCW(ACC_INTS, 0xffffffff); 343 if (si->ps.card_arch != NV04A) 344 { 345 /* context control enabled */ 346 ACCW(NV10_CTX_CTRL, 0x10010100); 347 /* all acceleration buffers, pitches and colors are valid */ 348 ACCW(NV10_ACC_STAT, 0xffffffff); 349 } 350 else 351 { 352 /* context control enabled */ 353 ACCW(NV04_CTX_CTRL, 0x10010100); 354 /* all acceleration buffers, pitches and colors are valid */ 355 ACCW(NV04_ACC_STAT, 0xffffffff); 356 } 357 /* enable acceleration engine command FIFO */ 358 ACCW(FIFO_EN, 0x00000001); 359 /* pattern shape value = 8x8, 2 color */ 360 ACCW(PAT_SHP, 0x00000000); 361 if (si->ps.card_arch != NV04A) 362 { 363 /* surface type is non-swizzle */ 364 ACCW(NV10_SURF_TYP, 0x00000001); 365 } 366 else 367 { 368 /* surface type is non-swizzle */ 369 ACCW(NV04_SURF_TYP, 0x00000001); 370 } 371 372 /*** Set pixel width and format ***/ 373 switch(si->dm.space) 374 { 375 case B_CMAP8: 376 /* acc engine */ 377 ACCW(FORMATS, 0x00001010); 378 if (si->ps.card_arch < NV30A) 379 ACCW(BPIXEL, 0x00111111); /* set depth 0-5: 4 bits per color */ 380 else 381 ACCW(BPIXEL, 0x00000021); /* set depth 0-1: 5 bits per color */ 382 ACCW(STRD_FMT, 0x03020202); 383 /* PRAMIN */ 384 ACCW(PR_CTX1_0, 0x00000302); /* format is X24Y8, LSB mono */ 385 ACCW(PR_CTX1_1, 0x00000302); /* format is X24Y8, LSB mono */ 386 ACCW(PR_CTX1_2, 0x00000202); /* format is X16A8Y8, LSB mono */ 387 ACCW(PR_CTX1_3, 0x00000302); /* format is X24Y8, LSB mono */ 388 ACCW(PR_CTX1_4, 0x00000302); /* format is X24Y8, LSB mono */ 389 ACCW(PR_CTX1_5, 0x00000302); /* format is X24Y8, LSB mono */ 390 ACCW(PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */ 391 ACCW(PR_CTX2_9, 0x00000302); /* dma_instance 0 valid, instance 1 invalid */ 392 ACCW(PR_CTX1_B, 0x00000000); /* format is invalid */ 393 ACCW(PR_CTX1_C, 0x00000000); /* format is invalid */ 394 if (si->ps.card_arch == NV04A) 395 { 396 ACCW(PR_CTX1_D, 0x00000302); /* format is X24Y8, LSB mono */ 397 } 398 else 399 { 400 ACCW(PR_CTX1_D, 0x00000000); /* format is invalid */ 401 ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */ 402 } 403 break; 404 case B_RGB15_LITTLE: 405 /* acc engine */ 406 ACCW(FORMATS, 0x00002071); 407 if (si->ps.card_arch < NV30A) 408 ACCW(BPIXEL, 0x00226222); /* set depth 0-5: 4 bits per color */ 409 else 410 ACCW(BPIXEL, 0x00000042); /* set depth 0-1: 5 bits per color */ 411 ACCW(STRD_FMT, 0x09080808); 412 /* PRAMIN */ 413 ACCW(PR_CTX1_0, 0x00000902); /* format is X17RGB15, LSB mono */ 414 ACCW(PR_CTX1_1, 0x00000902); /* format is X17RGB15, LSB mono */ 415 ACCW(PR_CTX1_2, 0x00000802); /* format is X16A1RGB15, LSB mono */ 416 ACCW(PR_CTX1_3, 0x00000902); /* format is X17RGB15, LSB mono */ 417 ACCW(PR_CTX1_4, 0x00000902); /* format is X17RGB15, LSB mono */ 418 ACCW(PR_CTX1_5, 0x00000902); /* format is X17RGB15, LSB mono */ 419 ACCW(PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */ 420 ACCW(PR_CTX2_9, 0x00000902); /* dma_instance 0 valid, instance 1 invalid */ 421 if (si->ps.card_arch == NV04A) 422 { 423 ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */ 424 ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */ 425 } 426 else 427 { 428 ACCW(PR_CTX1_B, 0x00000902); /* format is X17RGB15, LSB mono */ 429 ACCW(PR_CTX1_C, 0x00000902); /* format is X17RGB15, LSB mono */ 430 ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */ 431 } 432 ACCW(PR_CTX1_D, 0x00000902); /* format is X17RGB15, LSB mono */ 433 break; 434 case B_RGB16_LITTLE: 435 /* acc engine */ 436 ACCW(FORMATS, 0x000050C2); 437 if (si->ps.card_arch < NV30A) 438 ACCW(BPIXEL, 0x00556555); /* set depth 0-5: 4 bits per color */ 439 else 440 ACCW(BPIXEL, 0x000000a5); /* set depth 0-1: 5 bits per color */ 441 if (si->ps.card_arch == NV04A) 442 ACCW(STRD_FMT, 0x0c0b0b0b); 443 else 444 ACCW(STRD_FMT, 0x000b0b0c); 445 /* PRAMIN */ 446 ACCW(PR_CTX1_0, 0x00000c02); /* format is X16RGB16, LSB mono */ 447 ACCW(PR_CTX1_1, 0x00000c02); /* format is X16RGB16, LSB mono */ 448 ACCW(PR_CTX1_2, 0x00000b02); /* format is A16RGB16, LSB mono */ 449 ACCW(PR_CTX1_3, 0x00000c02); /* format is X16RGB16, LSB mono */ 450 ACCW(PR_CTX1_4, 0x00000c02); /* format is X16RGB16, LSB mono */ 451 ACCW(PR_CTX1_5, 0x00000c02); /* format is X16RGB16, LSB mono */ 452 ACCW(PR_CTX1_9, 0x00000c02); /* format is X16RGB16, LSB mono */ 453 ACCW(PR_CTX2_9, 0x00000c02); /* dma_instance 0 valid, instance 1 invalid */ 454 if (si->ps.card_arch == NV04A) 455 { 456 ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */ 457 ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */ 458 } 459 else 460 { 461 ACCW(PR_CTX1_B, 0x00000c02); /* format is X16RGB16, LSB mono */ 462 ACCW(PR_CTX1_C, 0x00000c02); /* format is X16RGB16, LSB mono */ 463 ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */ 464 } 465 ACCW(PR_CTX1_D, 0x00000c02); /* format is X16RGB16, LSB mono */ 466 break; 467 case B_RGB32_LITTLE:case B_RGBA32_LITTLE: 468 /* acc engine */ 469 ACCW(FORMATS, 0x000070e5); 470 if (si->ps.card_arch < NV30A) 471 ACCW(BPIXEL, 0x0077d777); /* set depth 0-5: 4 bits per color */ 472 else 473 ACCW(BPIXEL, 0x000000e7); /* set depth 0-1: 5 bits per color */ 474 ACCW(STRD_FMT, 0x0e0d0d0d); 475 /* PRAMIN */ 476 ACCW(PR_CTX1_0, 0x00000e02); /* format is X8RGB24, LSB mono */ 477 ACCW(PR_CTX1_1, 0x00000e02); /* format is X8RGB24, LSB mono */ 478 ACCW(PR_CTX1_2, 0x00000d02); /* format is A8RGB24, LSB mono */ 479 ACCW(PR_CTX1_3, 0x00000e02); /* format is X8RGB24, LSB mono */ 480 ACCW(PR_CTX1_4, 0x00000e02); /* format is X8RGB24, LSB mono */ 481 ACCW(PR_CTX1_5, 0x00000e02); /* format is X8RGB24, LSB mono */ 482 ACCW(PR_CTX1_9, 0x00000e02); /* format is X8RGB24, LSB mono */ 483 ACCW(PR_CTX2_9, 0x00000e02); /* dma_instance 0 valid, instance 1 invalid */ 484 ACCW(PR_CTX1_B, 0x00000e02); /* format is X8RGB24, LSB mono */ 485 ACCW(PR_CTX1_C, 0x00000e02); /* format is X8RGB24, LSB mono */ 486 ACCW(PR_CTX1_D, 0x00000e02); /* format is X8RGB24, LSB mono */ 487 if (si->ps.card_arch >= NV10A) 488 ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */ 489 break; 490 default: 491 LOG(8,("ACC: init, invalid bit depth\n")); 492 return B_ERROR; 493 } 494 495 /* setup some extra stuff for NV30A */ 496 if (si->ps.card_arch == NV30A) 497 { 498 /* 499 fixme: Does not belong here (and not needed?) 500 if(!chip->flatPanel) 501 { 502 chip->PRAMDAC0[0x0578/4] = state->vpllB; //0x00680578 = ??? never modified! 503 chip->PRAMDAC0[0x057C/4] = state->vpll2B; //0x0068057c = ??? never modified! 504 } 505 */ 506 507 /* activate Zcullflush(?) */ 508 ACCW(DEBUG3, (ACCR(DEBUG3) | 0x00000001)); 509 /* unknown */ 510 ACCW(NV30_WHAT, (ACCR(NV30_WHAT) | 0x00040000)); 511 } 512 513 /*** setup screen location and pitch ***/ 514 switch (si->ps.card_arch) 515 { 516 case NV04A: 517 case NV10A: 518 /* location of active screen in framebuffer */ 519 ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 520 ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 521 ACCW(OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 522 ACCW(OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 523 ACCW(OFFSET4, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 524 ACCW(OFFSET5, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 525 526 /* setup buffer pitch */ 527 ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); 528 ACCW(PITCH1, (si->fbc.bytes_per_row & 0x0000ffff)); 529 ACCW(PITCH2, (si->fbc.bytes_per_row & 0x0000ffff)); 530 ACCW(PITCH3, (si->fbc.bytes_per_row & 0x0000ffff)); 531 ACCW(PITCH4, (si->fbc.bytes_per_row & 0x0000ffff)); 532 break; 533 case NV20A: 534 case NV30A: 535 /* location of active screen in framebuffer */ 536 ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 537 ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 538 ACCW(NV20_OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 539 ACCW(NV20_OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); 540 541 /* setup buffer pitch */ 542 ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); 543 ACCW(NV20_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff)); 544 ACCW(NV20_PITCH2, (si->fbc.bytes_per_row & 0x0000ffff)); 545 ACCW(NV20_PITCH3, (si->fbc.bytes_per_row & 0x0000ffff)); 546 break; 547 } 548 549 /*** setup tile and pipe stuff ***/ 550 if (si->ps.card_arch >= NV10A) 551 { 552 /* 553 fixme: setup elsewhere (does not belong here): 554 chip->PRAMDAC[0x00000404/4] |= (1 << 25);//0x00680404 = ??? 555 */ 556 557 /* setup acc engine tile stuff: */ 558 /* reset tile adresses */ 559 ACCW(NV10_FBTIL0AD, 0); 560 ACCW(NV10_FBTIL1AD, 0); 561 ACCW(NV10_FBTIL2AD, 0); 562 ACCW(NV10_FBTIL3AD, 0); 563 ACCW(NV10_FBTIL4AD, 0); 564 ACCW(NV10_FBTIL5AD, 0); 565 ACCW(NV10_FBTIL6AD, 0); 566 ACCW(NV10_FBTIL7AD, 0); 567 /* copy tile setup stuff from 'source' to acc engine */ 568 if (si->ps.card_arch >= NV20A) 569 { 570 /* unknown: */ 571 ACCW(NV20_WHAT0, ACCR(NV20_FBWHAT0)); 572 ACCW(NV20_WHAT1, ACCR(NV20_FBWHAT1)); 573 } 574 /* tile 0: */ 575 /* tile invalid, tile adress = $00000 (18bit) */ 576 ACCW(NV10_TIL0AD, ACCR(NV10_FBTIL0AD)); 577 /* set tile end adress (18bit) */ 578 ACCW(NV10_TIL0ED, ACCR(NV10_FBTIL0ED)); 579 /* set tile size pitch (8bit: b8-15) */ 580 ACCW(NV10_TIL0PT, ACCR(NV10_FBTIL0PT)); 581 /* set tile status */ 582 ACCW(NV10_TIL0ST, ACCR(NV10_FBTIL0ST)); 583 /* tile 1: */ 584 ACCW(NV10_TIL1AD, ACCR(NV10_FBTIL1AD)); 585 ACCW(NV10_TIL1ED, ACCR(NV10_FBTIL1ED)); 586 ACCW(NV10_TIL1PT, ACCR(NV10_FBTIL1PT)); 587 ACCW(NV10_TIL1ST, ACCR(NV10_FBTIL1ST)); 588 /* tile 2: */ 589 ACCW(NV10_TIL2AD, ACCR(NV10_FBTIL2AD)); 590 ACCW(NV10_TIL2ED, ACCR(NV10_FBTIL2ED)); 591 ACCW(NV10_TIL2PT, ACCR(NV10_FBTIL2PT)); 592 ACCW(NV10_TIL2ST, ACCR(NV10_FBTIL2ST)); 593 /* tile 3: */ 594 ACCW(NV10_TIL3AD, ACCR(NV10_FBTIL3AD)); 595 ACCW(NV10_TIL3ED, ACCR(NV10_FBTIL3ED)); 596 ACCW(NV10_TIL3PT, ACCR(NV10_FBTIL3PT)); 597 ACCW(NV10_TIL3ST, ACCR(NV10_FBTIL3ST)); 598 /* tile 4: */ 599 ACCW(NV10_TIL4AD, ACCR(NV10_FBTIL4AD)); 600 ACCW(NV10_TIL4ED, ACCR(NV10_FBTIL4ED)); 601 ACCW(NV10_TIL4PT, ACCR(NV10_FBTIL4PT)); 602 ACCW(NV10_TIL4ST, ACCR(NV10_FBTIL4ST)); 603 /* tile 5: */ 604 ACCW(NV10_TIL5AD, ACCR(NV10_FBTIL5AD)); 605 ACCW(NV10_TIL5ED, ACCR(NV10_FBTIL5ED)); 606 ACCW(NV10_TIL5PT, ACCR(NV10_FBTIL5PT)); 607 ACCW(NV10_TIL5ST, ACCR(NV10_FBTIL5ST)); 608 /* tile 6: */ 609 ACCW(NV10_TIL6AD, ACCR(NV10_FBTIL6AD)); 610 ACCW(NV10_TIL6ED, ACCR(NV10_FBTIL6ED)); 611 ACCW(NV10_TIL6PT, ACCR(NV10_FBTIL6PT)); 612 ACCW(NV10_TIL6ST, ACCR(NV10_FBTIL6ST)); 613 /* tile 7: */ 614 ACCW(NV10_TIL7AD, ACCR(NV10_FBTIL7AD)); 615 ACCW(NV10_TIL7ED, ACCR(NV10_FBTIL7ED)); 616 ACCW(NV10_TIL7PT, ACCR(NV10_FBTIL7PT)); 617 ACCW(NV10_TIL7ST, ACCR(NV10_FBTIL7ST)); 618 619 /* setup pipe */ 620 /* set eyetype to local, lightning is off */ 621 ACCW(NV10_XFMOD0, 0x10000000); 622 /* disable all lights */ 623 ACCW(NV10_XFMOD1, 0x00000000); 624 625 ACCW(NV10_PIPEADR, 0x00000040); 626 ACCW(NV10_PIPEDAT, 0x00000008); 627 628 ACCW(NV10_PIPEADR, 0x00000200); 629 for (cnt = 0; cnt < (3 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 630 631 ACCW(NV10_PIPEADR, 0x00000040); 632 ACCW(NV10_PIPEDAT, 0x00000000); 633 634 ACCW(NV10_PIPEADR, 0x00000800); 635 for (cnt = 0; cnt < (16 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 636 637 /* turn lightning on */ 638 ACCW(NV10_XFMOD0, 0x30000000); 639 /* set light 1 to infinite type, other lights remain off */ 640 ACCW(NV10_XFMOD1, 0x00000004); 641 642 ACCW(NV10_PIPEADR, 0x00006400); 643 for (cnt = 0; cnt < (59 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 644 645 ACCW(NV10_PIPEADR, 0x00006800); 646 for (cnt = 0; cnt < (47 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 647 648 ACCW(NV10_PIPEADR, 0x00006c00); 649 for (cnt = 0; cnt < (3 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 650 651 ACCW(NV10_PIPEADR, 0x00007000); 652 for (cnt = 0; cnt < (19 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 653 654 ACCW(NV10_PIPEADR, 0x00007400); 655 for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 656 657 ACCW(NV10_PIPEADR, 0x00007800); 658 for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 659 660 ACCW(NV10_PIPEADR, 0x00004400); 661 for (cnt = 0; cnt < (8 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 662 663 ACCW(NV10_PIPEADR, 0x00000000); 664 for (cnt = 0; cnt < 16; cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 665 666 ACCW(NV10_PIPEADR, 0x00000040); 667 for (cnt = 0; cnt < 4; cnt++) ACCW(NV10_PIPEDAT, 0x00000000); 668 } 669 670 /*** setup acceleration engine command shortcuts (so via fifo) ***/ 671 /* (b31 = 1 selects 'config' function?) */ 672 ACCW(FIFO_00800000, 0x80000000); /* Raster OPeration */ 673 ACCW(FIFO_00802000, 0x80000001); /* Clip */ 674 ACCW(FIFO_00804000, 0x80000002); /* Pattern */ 675 ACCW(FIFO_00806000, 0x80000010); /* Pixmap (not used) */ 676 ACCW(FIFO_00808000, 0x80000011); /* Blit */ 677 ACCW(FIFO_0080a000, 0x80000012); /* Bitmap */ 678 ACCW(FIFO_0080c000, 0x80000016); /* Line (not used) */ 679 ACCW(FIFO_0080e000, 0x80000014); /* ??? (not used) */ 680 681 /* do first actual acceleration engine command: 682 * setup clipping region (workspace size) to 32768 x 32768 pixels: 683 * wait for room in fifo for clipping cmd if needed. 684 * (fifo holds 256 32bit words: count those, not bytes) */ 685 while (((NV_REG16(NV16_CLP_FIFOFREE)) >> 2) < 2) 686 { 687 /* snooze a bit so I do not hammer the bus */ 688 snooze (10); 689 } 690 /* now setup clipping (writing 2 32bit words) */ 691 ACCW(CLP_TOPLEFT, 0x00000000); 692 ACCW(CLP_WIDHEIGHT, 0x80008000); 693 694 return B_OK; 695 } 696 697 /* screen to screen blit - i.e. move windows around and scroll within them. */ 698 status_t nv_acc_setup_blit() 699 { 700 /* setup solid pattern: 701 * wait for room in fifo for pattern cmd if needed. 702 * (fifo holds 256 32bit words: count those, not bytes) */ 703 while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) 704 { 705 /* snooze a bit so I do not hammer the bus */ 706 snooze (10); 707 } 708 /* now setup pattern (writing 5 32bit words) */ 709 ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ 710 ACCW(PAT_COLOR0, 0xffffffff); 711 ACCW(PAT_COLOR1, 0xffffffff); 712 ACCW(PAT_MONO1, 0xffffffff); 713 ACCW(PAT_MONO2, 0xffffffff); 714 715 /* ROP3 registers (Raster OPeration): 716 * wait for room in fifo for ROP cmd if needed. 717 * (fifo holds 256 32bit words: count those, not bytes) */ 718 while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) 719 { 720 /* snooze a bit so I do not hammer the bus */ 721 snooze (10); 722 } 723 /* now setup ROP (writing 1 32bit word) */ 724 ACCW(ROP_ROP3, 0xcc); 725 726 return B_OK; 727 } 728 729 status_t nv_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h) 730 { 731 /* Note: blit-copy direction is determined inside riva hardware: no setup needed */ 732 733 /* instruct engine what to blit: 734 * wait for room in fifo for blit cmd if needed. 735 * (fifo holds 256 32bit words: count those, not bytes) */ 736 while (((NV_REG16(NV16_BLT_FIFOFREE)) >> 2) < 3) 737 { 738 /* snooze a bit so I do not hammer the bus */ 739 snooze (10); 740 } 741 /* now setup blit (writing 3 32bit words) */ 742 ACCW(BLT_TOPLFTSRC, ((ys << 16) | xs)); 743 ACCW(BLT_TOPLFTDST, ((yd << 16) | xd)); 744 ACCW(BLT_SIZE, (((h + 1) << 16) | (w + 1))); 745 746 return B_OK; 747 } 748 749 /* rectangle fill - i.e. workspace and window background color */ 750 /* span fill - i.e. (selected) menuitem background color (Dano) */ 751 status_t nv_acc_setup_rectangle(uint32 color) 752 { 753 /* setup solid pattern: 754 * wait for room in fifo for pattern cmd if needed. 755 * (fifo holds 256 32bit words: count those, not bytes) */ 756 while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) 757 { 758 /* snooze a bit so I do not hammer the bus */ 759 snooze (10); 760 } 761 /* now setup pattern (writing 5 32bit words) */ 762 ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ 763 ACCW(PAT_COLOR0, 0xffffffff); 764 ACCW(PAT_COLOR1, 0xffffffff); 765 ACCW(PAT_MONO1, 0xffffffff); 766 ACCW(PAT_MONO2, 0xffffffff); 767 768 /* ROP3 registers (Raster OPeration): 769 * wait for room in fifo for ROP cmd if needed. 770 * (fifo holds 256 32bit words: count those, not bytes) */ 771 while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) 772 { 773 /* snooze a bit so I do not hammer the bus */ 774 snooze (10); 775 } 776 /* now setup ROP (writing 1 32bit word) for GXcopy */ 777 ACCW(ROP_ROP3, 0xcc); 778 779 /* setup fill color: 780 * wait for room in fifo for bitmap cmd if needed. 781 * (fifo holds 256 32bit words: count those, not bytes) */ 782 while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) 783 { 784 /* snooze a bit so I do not hammer the bus */ 785 snooze (10); 786 } 787 /* now setup color (writing 1 32bit word) */ 788 ACCW(BMP_COLOR1A, color); 789 790 return B_OK; 791 } 792 793 status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl) 794 { 795 /* instruct engine what to fill: 796 * wait for room in fifo for bitmap cmd if needed. 797 * (fifo holds 256 32bit words: count those, not bytes) */ 798 while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) 799 { 800 /* snooze a bit so I do not hammer the bus */ 801 snooze (10); 802 } 803 /* now setup fill (writing 2 32bit words) */ 804 ACCW(BMP_UCRECTL_0, ((xs << 16) | (ys & 0x0000ffff))); 805 ACCW(BMP_UCRECSZ_0, (((xe - xs) << 16) | (yl & 0x0000ffff))); 806 807 return B_OK; 808 } 809 810 /* rectangle invert - i.e. text cursor and text selection */ 811 status_t nv_acc_setup_rect_invert() 812 { 813 /* setup solid pattern: 814 * wait for room in fifo for pattern cmd if needed. 815 * (fifo holds 256 32bit words: count those, not bytes) */ 816 while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) 817 { 818 /* snooze a bit so I do not hammer the bus */ 819 snooze (10); 820 } 821 /* now setup pattern (writing 5 32bit words) */ 822 ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ 823 ACCW(PAT_COLOR0, 0xffffffff); 824 ACCW(PAT_COLOR1, 0xffffffff); 825 ACCW(PAT_MONO1, 0xffffffff); 826 ACCW(PAT_MONO2, 0xffffffff); 827 828 /* ROP3 registers (Raster OPeration): 829 * wait for room in fifo for ROP cmd if needed. 830 * (fifo holds 256 32bit words: count those, not bytes) */ 831 while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) 832 { 833 /* snooze a bit so I do not hammer the bus */ 834 snooze (10); 835 } 836 /* now setup ROP (writing 1 32bit word) for GXinvert */ 837 ACCW(ROP_ROP3, 0x55); 838 839 /* reset fill color: 840 * wait for room in fifo for bitmap cmd if needed. 841 * (fifo holds 256 32bit words: count those, not bytes) */ 842 while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) 843 { 844 /* snooze a bit so I do not hammer the bus */ 845 snooze (10); 846 } 847 /* now reset color (writing 1 32bit word) */ 848 ACCW(BMP_COLOR1A, 0); 849 850 return B_OK; 851 } 852 853 status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl) 854 { 855 /* instruct engine what to invert: 856 * wait for room in fifo for bitmap cmd if needed. 857 * (fifo holds 256 32bit words: count those, not bytes) */ 858 while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) 859 { 860 /* snooze a bit so I do not hammer the bus */ 861 snooze (10); 862 } 863 /* now setup invert (writing 2 32bit words) */ 864 ACCW(BMP_UCRECTL_0, ((xs << 16) | (ys & 0x0000ffff))); 865 ACCW(BMP_UCRECSZ_0, (((xe - xs) << 16) | (yl & 0x0000ffff))); 866 867 return B_OK; 868 } 869 870 /* screen to screen tranparent blit */ 871 status_t nv_acc_transparent_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h,uint32 colour) 872 { 873 //fixme: implement. 874 875 return B_ERROR; 876 } 877 878 /* screen to screen scaled filtered blit - i.e. scale video in memory */ 879 status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs, 880 uint16 xd,uint16 yd,uint16 wd,uint16 hd) 881 { 882 //fixme: implement. 883 884 return B_ERROR; 885 } 886