1 /* 2 * Copyright 2006-2007, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Support for i915 chipset and up based on the X driver, 6 * Copyright 2006-2007 Intel Corporation. 7 * 8 * Authors: 9 * Axel Dörfler, axeld@pinc-software.de 10 */ 11 12 13 #include "accelerant_protos.h" 14 #include "accelerant.h" 15 #include "utility.h" 16 17 #include <stdio.h> 18 #include <string.h> 19 #include <math.h> 20 21 #include <create_display_modes.h> 22 #include <ddc.h> 23 #include <edid.h> 24 25 26 #define TRACE_MODE 27 #ifdef TRACE_MODE 28 extern "C" void _sPrintf(const char *format, ...); 29 # define TRACE(x) _sPrintf x 30 #else 31 # define TRACE(x) ; 32 #endif 33 34 35 struct display_registers { 36 uint32 pll; 37 uint32 divisors; 38 uint32 control; 39 uint32 pipe_config; 40 uint32 horiz_total; 41 uint32 horiz_blank; 42 uint32 horiz_sync; 43 uint32 vert_total; 44 uint32 vert_blank; 45 uint32 vert_sync; 46 uint32 size; 47 uint32 stride; 48 uint32 position; 49 uint32 pipe_source; 50 }; 51 52 struct pll_divisors { 53 uint32 post; 54 uint32 post1; 55 uint32 post2; 56 bool post2_high; 57 uint32 n; 58 uint32 m; 59 uint32 m1; 60 uint32 m2; 61 }; 62 63 struct pll_limits { 64 pll_divisors min; 65 pll_divisors max; 66 uint32 min_post2_frequency; 67 uint32 min_vco; 68 uint32 max_vco; 69 }; 70 71 72 static status_t 73 get_i2c_signals(void* cookie, int* _clock, int* _data) 74 { 75 uint32 ioRegister = (uint32)cookie; 76 uint32 value = read32(ioRegister); 77 78 *_clock = (value & I2C_CLOCK_VALUE_IN) != 0; 79 *_data = (value & I2C_DATA_VALUE_IN) != 0; 80 81 return B_OK; 82 } 83 84 85 static status_t 86 set_i2c_signals(void* cookie, int clock, int data) 87 { 88 uint32 ioRegister = (uint32)cookie; 89 uint32 value; 90 91 if (gInfo->shared_info->device_type == INTEL_TYPE_83x) { 92 // on these chips, the reserved values are fixed 93 value = 0; 94 } else { 95 // on all others, we have to preserve them manually 96 value = read32(ioRegister) & I2C_RESERVED; 97 } 98 99 if (data != 0) 100 value |= I2C_DATA_DIRECTION_MASK; 101 else 102 value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT | I2C_DATA_VALUE_MASK; 103 104 if (clock != 0) 105 value |= I2C_CLOCK_DIRECTION_MASK; 106 else 107 value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT | I2C_CLOCK_VALUE_MASK; 108 109 write32(ioRegister, value); 110 read32(ioRegister); 111 // make sure the PCI bus has flushed the write 112 113 return B_OK; 114 } 115 116 117 void 118 set_frame_buffer_base() 119 { 120 intel_shared_info &sharedInfo = *gInfo->shared_info; 121 display_mode &mode = sharedInfo.current_mode; 122 uint32 baseRegister; 123 uint32 surfaceRegister; 124 125 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { 126 baseRegister = INTEL_DISPLAY_A_BASE; 127 surfaceRegister = INTEL_DISPLAY_A_SURFACE; 128 } else { 129 baseRegister = INTEL_DISPLAY_B_BASE; 130 surfaceRegister = INTEL_DISPLAY_B_SURFACE; 131 } 132 133 if (sharedInfo.device_type == INTEL_TYPE_965) { 134 write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row 135 + mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8); 136 read32(baseRegister); 137 write32(surfaceRegister, sharedInfo.frame_buffer_offset); 138 read32(surfaceRegister); 139 } else { 140 write32(baseRegister, sharedInfo.frame_buffer_offset 141 + mode.v_display_start * sharedInfo.bytes_per_row 142 + mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8); 143 read32(baseRegister); 144 } 145 } 146 147 148 /*! Creates the initial mode list of the primary accelerant. 149 It's called from intel_init_accelerant(). 150 */ 151 status_t 152 create_mode_list(void) 153 { 154 i2c_bus bus; 155 bus.cookie = (void*)INTEL_I2C_IO_A; 156 bus.set_signals = &set_i2c_signals; 157 bus.get_signals = &get_i2c_signals; 158 ddc2_init_timing(&bus); 159 160 if (ddc2_read_edid1(&bus, &gInfo->edid_info, NULL, NULL) == B_OK) { 161 edid_dump(&gInfo->edid_info); 162 gInfo->has_edid = true; 163 } else { 164 TRACE(("intel_extreme: getting EDID failed!\n")); 165 } 166 167 display_mode *list; 168 uint32 count = 0; 169 gInfo->mode_list_area = create_display_modes("intel extreme modes", 170 gInfo->has_edid ? &gInfo->edid_info : NULL, NULL, 0, NULL, 0, NULL, 171 &list, &count); 172 if (gInfo->mode_list_area < B_OK) 173 return gInfo->mode_list_area; 174 175 gInfo->mode_list = list; 176 gInfo->shared_info->mode_list_area = gInfo->mode_list_area; 177 gInfo->shared_info->mode_count = count; 178 179 return B_OK; 180 } 181 182 183 void 184 wait_for_vblank(void) 185 { 186 acquire_sem_etc(gInfo->shared_info->vblank_sem, 1, B_RELATIVE_TIMEOUT, 25000); 187 // With the output turned off via DPMS, we might not get any interrupts anymore 188 // that's why we don't wait forever for it. 189 } 190 191 192 static void 193 get_pll_limits(pll_limits &limits) 194 { 195 // Note, the limits are taken from the X driver; they have not yet been tested 196 197 if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { 198 // TODO: support LVDS output limits as well 199 static const pll_limits kLimits = { 200 // p, p1, p2, high, n, m, m1, m2 201 { 5, 1, 10, false, 5, 70, 12, 7}, // min 202 { 80, 8, 5, true, 10, 120, 22, 11}, // max 203 200000, 1400000, 2800000 204 }; 205 limits = kLimits; 206 } else { 207 // TODO: support LVDS output limits as well 208 static const pll_limits kLimits = { 209 // p, p1, p2, high, n, m, m1, m2 210 { 4, 2, 4, false, 5, 96, 20, 8}, 211 {128, 33, 2, true, 18, 140, 28, 18}, 212 165000, 930000, 1400000 213 }; 214 limits = kLimits; 215 } 216 217 TRACE(("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", 218 limits.min.post, limits.min.post1, limits.min.post2, limits.min.n, 219 limits.min.m, limits.min.m1, limits.min.m2)); 220 TRACE(("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", 221 limits.max.post, limits.max.post1, limits.max.post2, limits.max.n, 222 limits.max.m, limits.max.m1, limits.max.m2)); 223 } 224 225 226 static bool 227 valid_pll_divisors(const pll_divisors& divisors, const pll_limits& limits) 228 { 229 pll_info &info = gInfo->shared_info->pll_info; 230 uint32 vco = info.reference_frequency * divisors.m / divisors.n; 231 uint32 frequency = vco / divisors.post; 232 233 if (divisors.post < limits.min.post || divisors.post > limits.max.post 234 || divisors.m < limits.min.m || divisors.m > limits.max.m 235 || vco < limits.min_vco || vco > limits.max_vco 236 || frequency < info.min_frequency || frequency > info.max_frequency) 237 return false; 238 239 return true; 240 } 241 242 243 static void 244 compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors) 245 { 246 float requestedPixelClock = current.timing.pixel_clock / 1000.0f; 247 float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 248 pll_limits limits; 249 get_pll_limits(limits); 250 251 TRACE(("required MHz: %g\n", requestedPixelClock)); 252 253 if (current.timing.pixel_clock < limits.min_post2_frequency) { 254 // slow DAC timing 255 divisors.post2 = limits.min.post2; 256 divisors.post2_high = limits.min.post2_high; 257 } else { 258 // fast DAC timing 259 divisors.post2 = limits.max.post2; 260 divisors.post2_high = limits.max.post2_high; 261 } 262 263 float best = requestedPixelClock; 264 pll_divisors bestDivisors; 265 266 for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1; divisors.m1++) { 267 for (divisors.m2 = limits.min.m2; divisors.m2 < divisors.m1 268 && divisors.m2 <= limits.max.m2; divisors.m2++) { 269 for (divisors.n = limits.min.n; divisors.n <= limits.max.n; 270 divisors.n++) { 271 for (divisors.post1 = limits.min.post1; 272 divisors.post1 <= limits.max.post1; divisors.post1++) { 273 divisors.m = 5 * divisors.m1 + divisors.m2; 274 divisors.post = divisors.post1 * divisors.post2; 275 276 if (!valid_pll_divisors(divisors, limits)) 277 continue; 278 279 float error = fabs(requestedPixelClock 280 - ((referenceClock * divisors.m) / divisors.n) / divisors.post); 281 if (error < best) { 282 best = error; 283 bestDivisors = divisors; 284 285 if (error == 0) 286 break; 287 } 288 } 289 } 290 } 291 } 292 293 divisors = bestDivisors; 294 295 TRACE(("found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu (m1 = %lu, m2 = %lu)\n", 296 ((referenceClock * divisors.m) / divisors.n) / divisors.post, 297 divisors.post, divisors.post1, divisors.post2, divisors.n, 298 divisors.m, divisors.m1, divisors.m2)); 299 } 300 301 302 static void 303 get_color_space_format(const display_mode &mode, uint32 &colorMode, 304 uint32 &bytesPerRow, uint32 &bitsPerPixel) 305 { 306 uint32 bytesPerPixel; 307 308 switch (mode.space) { 309 case B_RGB32_LITTLE: 310 colorMode = DISPLAY_CONTROL_RGB32; 311 bytesPerPixel = 4; 312 bitsPerPixel = 32; 313 break; 314 case B_RGB16_LITTLE: 315 colorMode = DISPLAY_CONTROL_RGB16; 316 bytesPerPixel = 2; 317 bitsPerPixel = 16; 318 break; 319 case B_RGB15_LITTLE: 320 colorMode = DISPLAY_CONTROL_RGB15; 321 bytesPerPixel = 2; 322 bitsPerPixel = 15; 323 break; 324 case B_CMAP8: 325 default: 326 colorMode = DISPLAY_CONTROL_CMAP8; 327 bytesPerPixel = 1; 328 bitsPerPixel = 8; 329 break; 330 } 331 332 bytesPerRow = mode.virtual_width * bytesPerPixel; 333 } 334 335 336 // #pragma mark - 337 338 339 uint32 340 intel_accelerant_mode_count(void) 341 { 342 TRACE(("intel_accelerant_mode_count()\n")); 343 return gInfo->shared_info->mode_count; 344 } 345 346 347 status_t 348 intel_get_mode_list(display_mode *modeList) 349 { 350 TRACE(("intel_get_mode_info()\n")); 351 memcpy(modeList, gInfo->mode_list, 352 gInfo->shared_info->mode_count * sizeof(display_mode)); 353 return B_OK; 354 } 355 356 357 status_t 358 intel_propose_display_mode(display_mode *target, const display_mode *low, 359 const display_mode *high) 360 { 361 TRACE(("intel_propose_display_mode()\n")); 362 363 // just search for the specified mode in the list 364 365 for (uint32 i = 0; i < gInfo->shared_info->mode_count; i++) { 366 display_mode *mode = &gInfo->mode_list[i]; 367 368 // TODO: improve this, ie. adapt pixel clock to allowed values!!! 369 370 if (target->virtual_width != mode->virtual_width 371 || target->virtual_height != mode->virtual_height 372 || target->space != mode->space) 373 continue; 374 375 *target = *mode; 376 return B_OK; 377 } 378 return B_BAD_VALUE; 379 } 380 381 382 status_t 383 intel_set_display_mode(display_mode *mode) 384 { 385 TRACE(("intel_set_display_mode()\n")); 386 387 display_mode target = *mode; 388 389 if (mode == NULL || intel_propose_display_mode(&target, mode, mode)) 390 return B_BAD_VALUE; 391 392 uint32 colorMode, bytesPerRow, bitsPerPixel; 393 get_color_space_format(target, colorMode, bytesPerRow, bitsPerPixel); 394 395 #if 0 396 static bool first = true; 397 if (first) { 398 int fd = open("/boot/home/ie_.regs", O_CREAT | O_WRONLY, 0644); 399 if (fd >= 0) { 400 for (int32 i = 0; i < 0x80000; i += 16) { 401 char line[512]; 402 int length = sprintf(line, "%05lx: %08lx %08lx %08lx %08lx\n", 403 i, read32(i), read32(i + 4), read32(i + 8), read32(i + 12)); 404 write(fd, line, length); 405 } 406 close(fd); 407 sync(); 408 } 409 first = false; 410 } 411 #endif 412 413 intel_shared_info &sharedInfo = *gInfo->shared_info; 414 Autolock locker(sharedInfo.accelerant_lock); 415 416 set_display_power_mode(B_DPMS_OFF); 417 418 // free old and allocate new frame buffer in graphics memory 419 420 intel_free_memory(sharedInfo.frame_buffer); 421 422 uint32 base; 423 if (intel_allocate_memory(bytesPerRow * target.virtual_height, 0, 424 base) < B_OK) { 425 // oh, how did that happen? Unfortunately, there is no really good way back 426 if (intel_allocate_memory(sharedInfo.current_mode.virtual_height 427 * sharedInfo.bytes_per_row, 0, base) == B_OK) { 428 sharedInfo.frame_buffer = base; 429 sharedInfo.frame_buffer_offset = base 430 - (addr_t)sharedInfo.graphics_memory; 431 set_frame_buffer_base(); 432 } 433 434 return B_NO_MEMORY; 435 } 436 437 // clear frame buffer before using it 438 memset((uint8 *)base, 0, bytesPerRow * target.virtual_height); 439 sharedInfo.frame_buffer = base; 440 sharedInfo.frame_buffer_offset = base - (addr_t)sharedInfo.graphics_memory; 441 442 // make sure VGA display is disabled 443 write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED); 444 read32(INTEL_VGA_DISPLAY_CONTROL); 445 446 if (gInfo->shared_info->device_type != INTEL_TYPE_85x) { 447 } 448 449 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { 450 pll_divisors divisors; 451 compute_pll_divisors(target, divisors); 452 453 write32(INTEL_DISPLAY_A_PLL_DIVISOR_0, 454 (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK) 455 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK) 456 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); 457 458 uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL; 459 if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { 460 pll |= ((1 << (divisors.post1 - 1)) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 461 & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 462 // pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 463 // & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 464 if (divisors.post2_high) 465 pll |= DISPLAY_PLL_DIVIDE_HIGH; 466 467 pll |= DISPLAY_PLL_MODE_ANALOG; 468 469 if (gInfo->shared_info->device_type == INTEL_TYPE_965) 470 pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; 471 } else { 472 if (!divisors.post2_high) 473 pll |= DISPLAY_PLL_DIVIDE_4X; 474 475 pll |= DISPLAY_PLL_2X_CLOCK; 476 477 if (divisors.post1 > 2) { 478 pll |= (((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 479 & DISPLAY_PLL_POST1_DIVISOR_MASK); 480 } else 481 pll |= DISPLAY_PLL_POST1_DIVIDE_2; 482 } 483 484 write32(INTEL_DISPLAY_A_PLL, pll); 485 read32(INTEL_DISPLAY_A_PLL); 486 spin(150); 487 write32(INTEL_DISPLAY_A_PLL, pll); 488 read32(INTEL_DISPLAY_A_PLL); 489 spin(150); 490 491 // update timing parameters 492 write32(INTEL_DISPLAY_A_HTOTAL, ((uint32)(target.timing.h_total - 1) << 16) 493 | ((uint32)target.timing.h_display - 1)); 494 write32(INTEL_DISPLAY_A_HBLANK, ((uint32)(target.timing.h_total - 1) << 16) 495 | ((uint32)target.timing.h_display - 1)); 496 write32(INTEL_DISPLAY_A_HSYNC, ((uint32)(target.timing.h_sync_end - 1) << 16) 497 | ((uint32)target.timing.h_sync_start - 1)); 498 499 write32(INTEL_DISPLAY_A_VTOTAL, ((uint32)(target.timing.v_total - 1) << 16) 500 | ((uint32)target.timing.v_display - 1)); 501 write32(INTEL_DISPLAY_A_VBLANK, ((uint32)(target.timing.v_total - 1) << 16) 502 | ((uint32)target.timing.v_display - 1)); 503 write32(INTEL_DISPLAY_A_VSYNC, ((uint32)(target.timing.v_sync_end - 1) << 16) 504 | ((uint32)target.timing.v_sync_start - 1)); 505 506 write32(INTEL_DISPLAY_A_IMAGE_SIZE, ((uint32)(target.timing.h_display - 1) << 16) 507 | ((uint32)target.timing.v_display - 1)); 508 509 write32(INTEL_DISPLAY_A_ANALOG_PORT, (read32(INTEL_DISPLAY_A_ANALOG_PORT) 510 & ~(DISPLAY_MONITOR_POLARITY_MASK | DISPLAY_MONITOR_VGA_POLARITY)) 511 | ((target.timing.flags & B_POSITIVE_HSYNC) != 0 ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0) 512 | ((target.timing.flags & B_POSITIVE_VSYNC) != 0 ? DISPLAY_MONITOR_POSITIVE_VSYNC : 0)); 513 } 514 515 // TODO: verify the two comments below: the X driver doesn't seem to 516 // care about both of them! 517 518 // These two have to be set for display B, too - this obviously means 519 // that the second head always must adopt the color space of the first 520 // head. 521 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 522 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) | colorMode); 523 524 if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { 525 write32(INTEL_DISPLAY_B_IMAGE_SIZE, ((uint32)(target.timing.h_display - 1) << 16) 526 | ((uint32)target.timing.v_display - 1)); 527 528 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 529 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) | colorMode); 530 } 531 532 set_display_power_mode(sharedInfo.dpms_mode); 533 534 // changing bytes per row seems to be ignored if the plane/pipe is turned off 535 536 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) 537 write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow); 538 if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) 539 write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow); 540 541 set_frame_buffer_base(); 542 // triggers writing back double-buffered registers 543 544 // update shared info 545 sharedInfo.bytes_per_row = bytesPerRow; 546 sharedInfo.current_mode = target; 547 sharedInfo.bits_per_pixel = bitsPerPixel; 548 549 return B_OK; 550 } 551 552 553 status_t 554 intel_get_display_mode(display_mode *_currentMode) 555 { 556 TRACE(("intel_get_display_mode()\n")); 557 558 display_mode &mode = *_currentMode; 559 560 uint32 pll = read32(INTEL_DISPLAY_A_PLL); 561 uint32 pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0 562 ? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0); 563 564 pll_divisors divisors; 565 divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK) 566 >> DISPLAY_PLL_M1_DIVISOR_SHIFT; 567 divisors.m2 = (pllDivisor & DISPLAY_PLL_M2_DIVISOR_MASK) 568 >> DISPLAY_PLL_M2_DIVISOR_SHIFT; 569 divisors.n = (pllDivisor & DISPLAY_PLL_N_DIVISOR_MASK) 570 >> DISPLAY_PLL_N_DIVISOR_SHIFT; 571 572 pll_limits limits; 573 get_pll_limits(limits); 574 575 if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { 576 divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) 577 >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; 578 579 if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0) 580 divisors.post2 = limits.max.post2; 581 else 582 divisors.post2 = limits.min.post2; 583 } else { 584 // 8xx 585 divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK) 586 >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; 587 588 if ((pll & DISPLAY_PLL_DIVIDE_4X) != 0) 589 divisors.post2 = limits.max.post2; 590 else 591 divisors.post2 = limits.min.post2; 592 } 593 594 divisors.m = 5 * divisors.m1 + divisors.m2; 595 divisors.post = divisors.post1 * divisors.post2; 596 597 float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 598 float pixelClock = ((referenceClock * divisors.m) / divisors.n) / divisors.post; 599 600 // timing 601 602 mode.timing.pixel_clock = uint32(pixelClock * 1000); 603 mode.timing.flags = 0; 604 605 uint32 value = read32(INTEL_DISPLAY_A_HTOTAL); 606 mode.timing.h_total = (value >> 16) + 1; 607 mode.timing.h_display = (value & 0xffff) + 1; 608 609 value = read32(INTEL_DISPLAY_A_HSYNC); 610 mode.timing.h_sync_end = (value >> 16) + 1; 611 mode.timing.h_sync_start = (value & 0xffff) + 1; 612 613 value = read32(INTEL_DISPLAY_A_VTOTAL); 614 mode.timing.v_total = (value >> 16) + 1; 615 mode.timing.v_display = (value & 0xffff) + 1; 616 617 value = read32(INTEL_DISPLAY_A_VSYNC); 618 mode.timing.v_sync_end = (value >> 16) + 1; 619 mode.timing.v_sync_start = (value & 0xffff) + 1; 620 621 // image size and color space 622 623 value = read32(INTEL_DISPLAY_A_IMAGE_SIZE); 624 mode.virtual_width = (value >> 16) + 1; 625 mode.virtual_height = (value & 0xffff) + 1; 626 627 value = read32(INTEL_DISPLAY_A_CONTROL); 628 switch (value & DISPLAY_CONTROL_COLOR_MASK) { 629 case DISPLAY_CONTROL_RGB32: 630 default: 631 mode.space = B_RGB32; 632 break; 633 case DISPLAY_CONTROL_RGB16: 634 mode.space = B_RGB16; 635 break; 636 case DISPLAY_CONTROL_RGB15: 637 mode.space = B_RGB15; 638 break; 639 case DISPLAY_CONTROL_CMAP8: 640 mode.space = B_CMAP8; 641 break; 642 } 643 644 mode.h_display_start = 0; 645 mode.v_display_start = 0; 646 mode.flags = 0; 647 return B_OK; 648 } 649 650 #ifdef __HAIKU__ 651 652 status_t 653 intel_get_edid_info(void* info, size_t size, uint32* _version) 654 { 655 TRACE(("intel_get_edid_info()\n")); 656 657 if (!gInfo->has_edid) 658 return B_ERROR; 659 if (size < sizeof(struct edid1_info)) 660 return B_BUFFER_OVERFLOW; 661 662 memcpy(info, &gInfo->edid_info, sizeof(struct edid1_info)); 663 *_version = EDID_VERSION_1; 664 return B_OK; 665 } 666 667 #endif // __HAIKU__ 668 669 status_t 670 intel_get_frame_buffer_config(frame_buffer_config *config) 671 { 672 TRACE(("intel_get_frame_buffer_config()\n")); 673 674 uint32 offset = gInfo->shared_info->frame_buffer_offset; 675 676 config->frame_buffer = gInfo->shared_info->graphics_memory + offset; 677 config->frame_buffer_dma 678 = (uint8 *)gInfo->shared_info->physical_graphics_memory + offset; 679 config->bytes_per_row = gInfo->shared_info->bytes_per_row; 680 681 return B_OK; 682 } 683 684 685 status_t 686 intel_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high) 687 { 688 TRACE(("intel_get_pixel_clock_limits()\n")); 689 690 if (_low != NULL) { 691 // lower limit of about 48Hz vertical refresh 692 uint32 totalClocks = (uint32)mode->timing.h_total * (uint32)mode->timing.v_total; 693 uint32 low = (totalClocks * 48L) / 1000L; 694 if (low < gInfo->shared_info->pll_info.min_frequency) 695 low = gInfo->shared_info->pll_info.min_frequency; 696 else if (low > gInfo->shared_info->pll_info.max_frequency) 697 return B_ERROR; 698 699 *_low = low; 700 } 701 702 if (_high != NULL) 703 *_high = gInfo->shared_info->pll_info.max_frequency; 704 705 return B_OK; 706 } 707 708 709 status_t 710 intel_move_display(uint16 horizontalStart, uint16 verticalStart) 711 { 712 TRACE(("intel_move_display()\n")); 713 714 intel_shared_info &sharedInfo = *gInfo->shared_info; 715 Autolock locker(sharedInfo.accelerant_lock); 716 717 display_mode &mode = sharedInfo.current_mode; 718 719 if (horizontalStart + mode.timing.h_display > mode.virtual_width 720 || verticalStart + mode.timing.v_display > mode.virtual_height) 721 return B_BAD_VALUE; 722 723 mode.h_display_start = horizontalStart; 724 mode.v_display_start = verticalStart; 725 726 set_frame_buffer_base(); 727 728 return B_OK; 729 } 730 731 732 status_t 733 intel_get_timing_constraints(display_timing_constraints *constraints) 734 { 735 TRACE(("intel_get_timing_contraints()\n")); 736 return B_ERROR; 737 } 738 739 740 void 741 intel_set_indexed_colors(uint count, uint8 first, uint8 *colors, uint32 flags) 742 { 743 TRACE(("intel_set_indexed_colors(colors = %p, first = %u)\n", colors, first)); 744 745 if (colors == NULL) 746 return; 747 748 Autolock locker(gInfo->shared_info->accelerant_lock); 749 750 for (; count-- > 0; first++) { 751 uint32 color = colors[0] << 16 | colors[1] << 8 | colors[2]; 752 colors += 3; 753 754 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) 755 write32(INTEL_DISPLAY_A_PALETTE + first * sizeof(uint32), color); 756 if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) 757 write32(INTEL_DISPLAY_B_PALETTE + first * sizeof(uint32), color); 758 } 759 } 760 761