1 /* 2 * Copyright 2006-2013, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Support for i915 chipset and up based on the X driver, 6 * Copyright 2006-2007 Intel Corporation. 7 * 8 * Authors: 9 * Axel Dörfler, axeld@pinc-software.de 10 */ 11 12 13 #include "accelerant_protos.h" 14 #include "accelerant.h" 15 #include "utility.h" 16 17 #include <Debug.h> 18 #include <stdio.h> 19 #include <string.h> 20 #include <math.h> 21 22 #include <create_display_modes.h> 23 #include <ddc.h> 24 #include <edid.h> 25 #include <validate_display_mode.h> 26 27 28 #undef TRACE 29 #define TRACE_MODE 30 #ifdef TRACE_MODE 31 # define TRACE(x...) _sPrintf("intel_extreme accelerant:" x) 32 #else 33 # define TRACE(x...) 34 #endif 35 36 #define ERROR(x...) _sPrintf("intel_extreme accelerant: " x) 37 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 38 39 40 struct display_registers { 41 uint32 pll; 42 uint32 divisors; 43 uint32 control; 44 uint32 pipe_config; 45 uint32 horiz_total; 46 uint32 horiz_blank; 47 uint32 horiz_sync; 48 uint32 vert_total; 49 uint32 vert_blank; 50 uint32 vert_sync; 51 uint32 size; 52 uint32 stride; 53 uint32 position; 54 uint32 pipe_source; 55 }; 56 57 struct pll_divisors { 58 uint32 post; 59 uint32 post1; 60 uint32 post2; 61 bool post2_high; 62 uint32 n; 63 uint32 m; 64 uint32 m1; 65 uint32 m2; 66 }; 67 68 struct pll_limits { 69 pll_divisors min; 70 pll_divisors max; 71 uint32 min_post2_frequency; 72 uint32 min_vco; 73 uint32 max_vco; 74 }; 75 76 77 static status_t 78 get_i2c_signals(void* cookie, int* _clock, int* _data) 79 { 80 uint32 ioRegister = (uint32)cookie; 81 uint32 value = read32(ioRegister); 82 83 *_clock = (value & I2C_CLOCK_VALUE_IN) != 0; 84 *_data = (value & I2C_DATA_VALUE_IN) != 0; 85 86 return B_OK; 87 } 88 89 90 static status_t 91 set_i2c_signals(void* cookie, int clock, int data) 92 { 93 uint32 ioRegister = (uint32)cookie; 94 uint32 value; 95 96 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_83x)) { 97 // on these chips, the reserved values are fixed 98 value = 0; 99 } else { 100 // on all others, we have to preserve them manually 101 value = read32(ioRegister) & I2C_RESERVED; 102 } 103 104 if (data != 0) 105 value |= I2C_DATA_DIRECTION_MASK; 106 else { 107 value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT 108 | I2C_DATA_VALUE_MASK; 109 } 110 111 if (clock != 0) 112 value |= I2C_CLOCK_DIRECTION_MASK; 113 else { 114 value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT 115 | I2C_CLOCK_VALUE_MASK; 116 } 117 118 write32(ioRegister, value); 119 read32(ioRegister); 120 // make sure the PCI bus has flushed the write 121 122 return B_OK; 123 } 124 125 126 static void 127 get_pll_limits(pll_limits &limits) 128 { 129 // Note, the limits are taken from the X driver; they have not yet been 130 // tested 131 132 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK) 133 || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB) 134 || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)) { 135 // TODO: support LVDS output limits as well 136 static const pll_limits kLimits = { 137 // p, p1, p2, high, n, m, m1, m2 138 { 5, 1, 10, false, 1, 79, 12, 5}, // min 139 { 80, 8, 5, true, 5, 127, 22, 9}, // max 140 225000, 1760000, 3510000 141 }; 142 limits = kLimits; 143 } else if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_G4x)) { 144 // TODO: support LVDS output limits as well 145 static const pll_limits kLimits = { 146 // p, p1, p2, high, n, m, m1, m2 147 { 10, 1, 10, false, 1, 104, 17, 5}, // min 148 { 30, 3, 10, true, 4, 138, 23, 11}, // max 149 270000, 1750000, 3500000 150 }; 151 limits = kLimits; 152 } else if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 153 // TODO: support LVDS output limits as well 154 // m1 is reserved and must be 0 155 static const pll_limits kLimits = { 156 // p, p1, p2, high, n, m, m1, m2 157 { 5, 1, 10, false, 3, 2, 0, 2}, // min 158 { 80, 8, 5, true, 6, 256, 0, 256}, // max 159 200000, 1700000, 3500000 160 }; 161 limits = kLimits; 162 } else if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) { 163 // TODO: support LVDS output limits as well 164 // (Update: Output limits are adjusted in the computation (post2=7/14)) 165 // Should move them here! 166 static const pll_limits kLimits = { 167 // p, p1, p2, high, n, m, m1, m2 168 { 5, 1, 10, false, 5, 70, 12, 7}, // min 169 { 80, 8, 5, true, 10, 120, 22, 11}, // max 170 200000, 1400000, 2800000 171 }; 172 limits = kLimits; 173 } else { 174 // TODO: support LVDS output limits as well 175 static const pll_limits kLimits = { 176 // p, p1, p2, high, n, m, m1, m2 177 { 4, 2, 4, false, 5, 96, 20, 8}, 178 {128, 33, 2, true, 18, 140, 28, 18}, 179 165000, 930000, 1400000 180 }; 181 limits = kLimits; 182 } 183 184 TRACE("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu " 185 "(m1 %lu, m2 %lu)\n", limits.min.post, limits.min.post1, 186 limits.min.post2, limits.min.n, limits.min.m, limits.min.m1, 187 limits.min.m2); 188 TRACE("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu " 189 "(m1 %lu, m2 %lu)\n", limits.max.post, limits.max.post1, 190 limits.max.post2, limits.max.n, limits.max.m, limits.max.m1, 191 limits.max.m2); 192 } 193 194 195 static bool 196 valid_pll_divisors(const pll_divisors& divisors, const pll_limits& limits) 197 { 198 pll_info &info = gInfo->shared_info->pll_info; 199 uint32 vco = info.reference_frequency * divisors.m / divisors.n; 200 uint32 frequency = vco / divisors.post; 201 202 if (divisors.post < limits.min.post || divisors.post > limits.max.post 203 || divisors.m < limits.min.m || divisors.m > limits.max.m 204 || vco < limits.min_vco || vco > limits.max_vco 205 || frequency < info.min_frequency || frequency > info.max_frequency) 206 return false; 207 208 return true; 209 } 210 211 212 static void 213 compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors, 214 bool isLVDS) 215 { 216 float requestedPixelClock = current.timing.pixel_clock / 1000.0f; 217 float referenceClock 218 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 219 pll_limits limits; 220 get_pll_limits(limits); 221 222 TRACE("%s: required MHz: %g\n", __func__, requestedPixelClock); 223 224 if (isLVDS) { 225 if ((read32(INTEL_DISPLAY_LVDS_PORT) & LVDS_CLKB_POWER_MASK) 226 == LVDS_CLKB_POWER_UP) 227 divisors.post2 = LVDS_POST2_RATE_FAST; 228 else 229 divisors.post2 = LVDS_POST2_RATE_SLOW; 230 } else { 231 if (current.timing.pixel_clock < limits.min_post2_frequency) { 232 // slow DAC timing 233 divisors.post2 = limits.min.post2; 234 divisors.post2_high = limits.min.post2_high; 235 } else { 236 // fast DAC timing 237 divisors.post2 = limits.max.post2; 238 divisors.post2_high = limits.max.post2_high; 239 } 240 } 241 242 float best = requestedPixelClock; 243 pll_divisors bestDivisors; 244 245 bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD); 246 for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1; 247 divisors.m1++) { 248 for (divisors.m2 = limits.min.m2; divisors.m2 <= limits.max.m2 249 && ((divisors.m2 < divisors.m1) || is_igd); divisors.m2++) { 250 for (divisors.n = limits.min.n; divisors.n <= limits.max.n; 251 divisors.n++) { 252 for (divisors.post1 = limits.min.post1; 253 divisors.post1 <= limits.max.post1; divisors.post1++) { 254 divisors.m = 5 * divisors.m1 + divisors.m2; 255 divisors.post = divisors.post1 * divisors.post2; 256 257 if (!valid_pll_divisors(divisors, limits)) 258 continue; 259 260 float error = fabs(requestedPixelClock 261 - ((referenceClock * divisors.m) / divisors.n) 262 / divisors.post); 263 if (error < best) { 264 best = error; 265 bestDivisors = divisors; 266 267 if (error == 0) 268 break; 269 } 270 } 271 } 272 } 273 } 274 275 divisors = bestDivisors; 276 277 TRACE("%s: found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu " 278 "(m1 = %lu, m2 = %lu)\n", __func__, 279 ((referenceClock * divisors.m) / divisors.n) / divisors.post, 280 divisors.post, divisors.post1, divisors.post2, divisors.n, 281 divisors.m, divisors.m1, divisors.m2); 282 } 283 284 285 static void 286 retrieve_current_mode(display_mode& mode, uint32 pllRegister) 287 { 288 uint32 pll = read32(pllRegister); 289 uint32 pllDivisor; 290 uint32 hTotalRegister; 291 uint32 vTotalRegister; 292 uint32 hSyncRegister; 293 uint32 vSyncRegister; 294 uint32 imageSizeRegister; 295 uint32 controlRegister; 296 297 if (pllRegister == INTEL_DISPLAY_A_PLL) { 298 pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0 299 ? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0); 300 301 hTotalRegister = INTEL_DISPLAY_A_HTOTAL; 302 vTotalRegister = INTEL_DISPLAY_A_VTOTAL; 303 hSyncRegister = INTEL_DISPLAY_A_HSYNC; 304 vSyncRegister = INTEL_DISPLAY_A_VSYNC; 305 imageSizeRegister = INTEL_DISPLAY_A_IMAGE_SIZE; 306 controlRegister = INTEL_DISPLAY_A_CONTROL; 307 } else if (pllRegister == INTEL_DISPLAY_B_PLL) { 308 pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0 309 ? INTEL_DISPLAY_B_PLL_DIVISOR_1 : INTEL_DISPLAY_B_PLL_DIVISOR_0); 310 311 hTotalRegister = INTEL_DISPLAY_B_HTOTAL; 312 vTotalRegister = INTEL_DISPLAY_B_VTOTAL; 313 hSyncRegister = INTEL_DISPLAY_B_HSYNC; 314 vSyncRegister = INTEL_DISPLAY_B_VSYNC; 315 imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE; 316 controlRegister = INTEL_DISPLAY_B_CONTROL; 317 } else { 318 // TODO: not supported 319 return; 320 } 321 322 pll_divisors divisors; 323 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 324 divisors.m1 = 0; 325 divisors.m2 = (pllDivisor & DISPLAY_PLL_IGD_M2_DIVISOR_MASK) 326 >> DISPLAY_PLL_M2_DIVISOR_SHIFT; 327 divisors.n = ((pllDivisor & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 328 >> DISPLAY_PLL_N_DIVISOR_SHIFT) - 1; 329 } else { 330 divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK) 331 >> DISPLAY_PLL_M1_DIVISOR_SHIFT; 332 divisors.m2 = (pllDivisor & DISPLAY_PLL_M2_DIVISOR_MASK) 333 >> DISPLAY_PLL_M2_DIVISOR_SHIFT; 334 divisors.n = (pllDivisor & DISPLAY_PLL_N_DIVISOR_MASK) 335 >> DISPLAY_PLL_N_DIVISOR_SHIFT; 336 } 337 338 pll_limits limits; 339 get_pll_limits(limits); 340 341 if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) { 342 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 343 divisors.post1 = (pll & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK) 344 >> DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT; 345 } else { 346 divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) 347 >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; 348 } 349 350 if (pllRegister == INTEL_DISPLAY_B_PLL 351 && !gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) { 352 // TODO: Fix this? Need to support dual channel LVDS. 353 divisors.post2 = LVDS_POST2_RATE_SLOW; 354 } else { 355 if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0) 356 divisors.post2 = limits.max.post2; 357 else 358 divisors.post2 = limits.min.post2; 359 } 360 } else { 361 // 8xx 362 divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK) 363 >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; 364 365 if ((pll & DISPLAY_PLL_DIVIDE_4X) != 0) 366 divisors.post2 = limits.max.post2; 367 else 368 divisors.post2 = limits.min.post2; 369 } 370 371 divisors.m = 5 * divisors.m1 + divisors.m2; 372 divisors.post = divisors.post1 * divisors.post2; 373 374 float referenceClock 375 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 376 float pixelClock 377 = ((referenceClock * divisors.m) / divisors.n) / divisors.post; 378 379 // timing 380 381 mode.timing.pixel_clock = uint32(pixelClock * 1000); 382 mode.timing.flags = 0; 383 384 uint32 value = read32(hTotalRegister); 385 mode.timing.h_total = (value >> 16) + 1; 386 mode.timing.h_display = (value & 0xffff) + 1; 387 388 value = read32(hSyncRegister); 389 mode.timing.h_sync_end = (value >> 16) + 1; 390 mode.timing.h_sync_start = (value & 0xffff) + 1; 391 392 value = read32(vTotalRegister); 393 mode.timing.v_total = (value >> 16) + 1; 394 mode.timing.v_display = (value & 0xffff) + 1; 395 396 value = read32(vSyncRegister); 397 mode.timing.v_sync_end = (value >> 16) + 1; 398 mode.timing.v_sync_start = (value & 0xffff) + 1; 399 400 // image size and color space 401 402 value = read32(imageSizeRegister); 403 mode.virtual_width = (value >> 16) + 1; 404 mode.virtual_height = (value & 0xffff) + 1; 405 406 // using virtual size based on image size is the 'proper' way to do it, 407 // however the bios appears to be suggesting scaling or somesuch, so ignore 408 // the proper virtual dimension for now if they'd suggest a smaller size. 409 if (mode.virtual_width < mode.timing.h_display) 410 mode.virtual_width = mode.timing.h_display; 411 if (mode.virtual_height < mode.timing.v_display) 412 mode.virtual_height = mode.timing.v_display; 413 414 value = read32(controlRegister); 415 switch (value & DISPLAY_CONTROL_COLOR_MASK) { 416 case DISPLAY_CONTROL_RGB32: 417 default: 418 mode.space = B_RGB32; 419 break; 420 case DISPLAY_CONTROL_RGB16: 421 mode.space = B_RGB16; 422 break; 423 case DISPLAY_CONTROL_RGB15: 424 mode.space = B_RGB15; 425 break; 426 case DISPLAY_CONTROL_CMAP8: 427 mode.space = B_CMAP8; 428 break; 429 } 430 431 mode.h_display_start = 0; 432 mode.v_display_start = 0; 433 mode.flags = B_8_BIT_DAC | B_HARDWARE_CURSOR | B_PARALLEL_ACCESS 434 | B_DPMS | B_SUPPORTS_OVERLAYS; 435 } 436 437 438 static void 439 get_color_space_format(const display_mode &mode, uint32 &colorMode, 440 uint32 &bytesPerRow, uint32 &bitsPerPixel) 441 { 442 uint32 bytesPerPixel; 443 444 switch (mode.space) { 445 case B_RGB32_LITTLE: 446 colorMode = DISPLAY_CONTROL_RGB32; 447 bytesPerPixel = 4; 448 bitsPerPixel = 32; 449 break; 450 case B_RGB16_LITTLE: 451 colorMode = DISPLAY_CONTROL_RGB16; 452 bytesPerPixel = 2; 453 bitsPerPixel = 16; 454 break; 455 case B_RGB15_LITTLE: 456 colorMode = DISPLAY_CONTROL_RGB15; 457 bytesPerPixel = 2; 458 bitsPerPixel = 15; 459 break; 460 case B_CMAP8: 461 default: 462 colorMode = DISPLAY_CONTROL_CMAP8; 463 bytesPerPixel = 1; 464 bitsPerPixel = 8; 465 break; 466 } 467 468 bytesPerRow = mode.virtual_width * bytesPerPixel; 469 470 // Make sure bytesPerRow is a multiple of 64 471 // TODO: check if the older chips have the same restriction! 472 if ((bytesPerRow & 63) != 0) 473 bytesPerRow = (bytesPerRow + 63) & ~63; 474 } 475 476 477 static bool 478 sanitize_display_mode(display_mode& mode) 479 { 480 // Some cards only support even pixel counts, while others require an odd 481 // one. 482 bool olderCard = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_Gxx); 483 olderCard |= gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x); 484 olderCard |= gInfo->shared_info->device_type.InGroup(INTEL_TYPE_94x); 485 olderCard |= gInfo->shared_info->device_type.InGroup(INTEL_TYPE_91x); 486 olderCard |= gInfo->shared_info->device_type.InFamily(INTEL_TYPE_8xx); 487 olderCard |= gInfo->shared_info->device_type.InFamily(INTEL_TYPE_7xx); 488 489 // TODO: verify constraints - these are more or less taken from the 490 // radeon driver! 491 const display_constraints constraints = { 492 // resolution 493 320, 8192, 200, 4096, 494 // pixel clock 495 gInfo->shared_info->pll_info.min_frequency, 496 gInfo->shared_info->pll_info.max_frequency, 497 // horizontal 498 {olderCard ? 2 : 1, 0, 8160, 32, 8192, 0, 8192}, 499 {1, 1, 4092, 2, 63, 1, 4096} 500 }; 501 502 return sanitize_display_mode(mode, constraints, 503 gInfo->has_edid ? &gInfo->edid_info : NULL); 504 } 505 506 507 static bool 508 check_and_sanitize_display_mode(display_mode* mode) 509 { 510 uint16 width = mode->timing.h_display; 511 uint16 height = mode->timing.v_display; 512 513 // Only accept the mode if it is within the supported resolution 514 // TODO: sanitize_display_mode() should report resolution changes 515 // differently! 516 return !sanitize_display_mode(*mode) || (width == mode->timing.h_display 517 && height == mode->timing.v_display); 518 } 519 520 521 // #pragma mark - 522 523 524 void 525 set_frame_buffer_base() 526 { 527 intel_shared_info &sharedInfo = *gInfo->shared_info; 528 display_mode &mode = sharedInfo.current_mode; 529 uint32 baseRegister; 530 uint32 surfaceRegister; 531 532 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { 533 baseRegister = INTEL_DISPLAY_A_BASE; 534 surfaceRegister = INTEL_DISPLAY_A_SURFACE; 535 } else { 536 baseRegister = INTEL_DISPLAY_B_BASE; 537 surfaceRegister = INTEL_DISPLAY_B_SURFACE; 538 } 539 540 if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x) 541 || sharedInfo.device_type.InGroup(INTEL_TYPE_G4x) 542 || sharedInfo.device_type.InGroup(INTEL_TYPE_ILK) 543 || sharedInfo.device_type.InGroup(INTEL_TYPE_SNB) 544 || sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)) { 545 write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row 546 + mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8); 547 read32(baseRegister); 548 write32(surfaceRegister, sharedInfo.frame_buffer_offset); 549 read32(surfaceRegister); 550 } else { 551 write32(baseRegister, sharedInfo.frame_buffer_offset 552 + mode.v_display_start * sharedInfo.bytes_per_row 553 + mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8); 554 read32(baseRegister); 555 } 556 } 557 558 559 /*! Creates the initial mode list of the primary accelerant. 560 It's called from intel_init_accelerant(). 561 */ 562 status_t 563 create_mode_list(void) 564 { 565 i2c_bus bus; 566 bus.cookie = (void*)INTEL_I2C_IO_A; 567 bus.set_signals = &set_i2c_signals; 568 bus.get_signals = &get_i2c_signals; 569 ddc2_init_timing(&bus); 570 571 status_t error = ddc2_read_edid1(&bus, &gInfo->edid_info, NULL, NULL); 572 if (error == B_OK) { 573 edid_dump(&gInfo->edid_info); 574 gInfo->has_edid = true; 575 } else { 576 TRACE("getting EDID on port A (analog) failed : %s. " 577 "Trying on port C (lvds)\n", strerror(error)); 578 bus.cookie = (void*)INTEL_I2C_IO_C; 579 error = ddc2_read_edid1(&bus, &gInfo->edid_info, NULL, NULL); 580 if (error == B_OK) { 581 edid_dump(&gInfo->edid_info); 582 gInfo->has_edid = true; 583 } else { 584 TRACE("getting EDID on port C failed : %s\n", 585 strerror(error)); 586 587 // We could not read any EDID info. Fallback to creating a list with 588 // only the mode set up by the BIOS. 589 // TODO: support lower modes via scaling and windowing 590 if ((gInfo->head_mode & HEAD_MODE_LVDS_PANEL) != 0 591 && (gInfo->head_mode & HEAD_MODE_A_ANALOG) == 0) { 592 size_t size = (sizeof(display_mode) + B_PAGE_SIZE - 1) 593 & ~(B_PAGE_SIZE - 1); 594 595 display_mode* list; 596 area_id area = create_area("intel extreme modes", 597 (void**)&list, B_ANY_ADDRESS, size, B_NO_LOCK, 598 B_READ_AREA | B_WRITE_AREA); 599 if (area < B_OK) 600 return area; 601 602 memcpy(list, &gInfo->lvds_panel_mode, sizeof(display_mode)); 603 604 gInfo->mode_list_area = area; 605 gInfo->mode_list = list; 606 gInfo->shared_info->mode_list_area = gInfo->mode_list_area; 607 gInfo->shared_info->mode_count = 1; 608 return B_OK; 609 } 610 } 611 } 612 613 // Otherwise return the 'real' list of modes 614 display_mode* list; 615 uint32 count = 0; 616 gInfo->mode_list_area = create_display_modes("intel extreme modes", 617 gInfo->has_edid ? &gInfo->edid_info : NULL, NULL, 0, NULL, 0, 618 &check_and_sanitize_display_mode, &list, &count); 619 if (gInfo->mode_list_area < B_OK) 620 return gInfo->mode_list_area; 621 622 gInfo->mode_list = list; 623 gInfo->shared_info->mode_list_area = gInfo->mode_list_area; 624 gInfo->shared_info->mode_count = count; 625 626 return B_OK; 627 } 628 629 630 void 631 wait_for_vblank(void) 632 { 633 acquire_sem_etc(gInfo->shared_info->vblank_sem, 1, B_RELATIVE_TIMEOUT, 634 25000); 635 // With the output turned off via DPMS, we might not get any interrupts 636 // anymore that's why we don't wait forever for it. 637 } 638 639 640 /*! Store away panel information if identified on startup 641 (used for pipe B->lvds). 642 */ 643 void 644 save_lvds_mode(void) 645 { 646 // dump currently programmed mode. 647 display_mode biosMode; 648 retrieve_current_mode(biosMode, INTEL_DISPLAY_B_PLL); 649 650 sanitize_display_mode(biosMode); 651 // The BIOS mode may not be a valid mode, as LVDS output does not 652 // really care about the sync values 653 654 gInfo->lvds_panel_mode = biosMode; 655 } 656 657 658 // #pragma mark - 659 660 661 uint32 662 intel_accelerant_mode_count(void) 663 { 664 CALLED(); 665 return gInfo->shared_info->mode_count; 666 } 667 668 669 status_t 670 intel_get_mode_list(display_mode* modeList) 671 { 672 CALLED(); 673 memcpy(modeList, gInfo->mode_list, 674 gInfo->shared_info->mode_count * sizeof(display_mode)); 675 return B_OK; 676 } 677 678 679 status_t 680 intel_propose_display_mode(display_mode* target, const display_mode* low, 681 const display_mode* high) 682 { 683 CALLED(); 684 685 // first search for the specified mode in the list, if no mode is found 686 // try to fix the target mode in sanitize_display_mode 687 // TODO: Only sanitize_display_mode should be used. However, at the moment 688 // the mode constraints are not optimal and do not work for all 689 // configurations. 690 for (uint32 i = 0; i < gInfo->shared_info->mode_count; i++) { 691 display_mode *mode = &gInfo->mode_list[i]; 692 693 // TODO: improve this, ie. adapt pixel clock to allowed values!!! 694 695 if (target->virtual_width != mode->virtual_width 696 || target->virtual_height != mode->virtual_height 697 || target->space != mode->space) 698 continue; 699 700 *target = *mode; 701 return B_OK; 702 } 703 704 sanitize_display_mode(*target); 705 706 return is_display_mode_within_bounds(*target, *low, *high) 707 ? B_OK : B_BAD_VALUE; 708 } 709 710 711 status_t 712 intel_set_display_mode(display_mode* mode) 713 { 714 TRACE("%s(%" B_PRIu16 "x%" B_PRIu16 ")\n", __func__, 715 mode->virtual_width, mode->virtual_height); 716 717 if (mode == NULL) 718 return B_BAD_VALUE; 719 720 display_mode target = *mode; 721 722 // TODO: it may be acceptable to continue when using panel fitting or 723 // centering, since the data from propose_display_mode will not actually be 724 // used as is in this case. 725 if (sanitize_display_mode(target)) { 726 TRACE("%s: invalid mode set!\n", __func__); 727 return B_BAD_VALUE; 728 } 729 730 uint32 colorMode, bytesPerRow, bitsPerPixel; 731 get_color_space_format(target, colorMode, bytesPerRow, bitsPerPixel); 732 733 // TODO: do not go further if the mode is identical to the current one. 734 // This would avoid the screen being off when switching workspaces when they 735 // have the same resolution. 736 737 #if 0 738 static bool first = true; 739 if (first) { 740 int fd = open("/boot/home/ie_.regs", O_CREAT | O_WRONLY, 0644); 741 if (fd >= 0) { 742 for (int32 i = 0; i < 0x80000; i += 16) { 743 char line[512]; 744 int length = sprintf(line, "%05lx: %08lx %08lx %08lx %08lx\n", 745 i, read32(i), read32(i + 4), read32(i + 8), read32(i + 12)); 746 write(fd, line, length); 747 } 748 close(fd); 749 sync(); 750 } 751 first = false; 752 } 753 #endif 754 755 intel_shared_info &sharedInfo = *gInfo->shared_info; 756 Autolock locker(sharedInfo.accelerant_lock); 757 758 // TODO: This may not be neccesary 759 set_display_power_mode(B_DPMS_OFF); 760 761 // free old and allocate new frame buffer in graphics memory 762 763 intel_free_memory(sharedInfo.frame_buffer); 764 765 uint32 base; 766 if (intel_allocate_memory(bytesPerRow * target.virtual_height, 0, 767 base) < B_OK) { 768 // oh, how did that happen? Unfortunately, there is no really good way 769 // back 770 if (intel_allocate_memory(sharedInfo.current_mode.virtual_height 771 * sharedInfo.bytes_per_row, 0, base) == B_OK) { 772 sharedInfo.frame_buffer = base; 773 sharedInfo.frame_buffer_offset = base 774 - (addr_t)sharedInfo.graphics_memory; 775 set_frame_buffer_base(); 776 } 777 778 TRACE("%s: Failed to allocate framebuffer !\n", __func__); 779 return B_NO_MEMORY; 780 } 781 782 // clear frame buffer before using it 783 memset((uint8*)base, 0, bytesPerRow * target.virtual_height); 784 sharedInfo.frame_buffer = base; 785 sharedInfo.frame_buffer_offset = base - (addr_t)sharedInfo.graphics_memory; 786 787 // make sure VGA display is disabled 788 write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED); 789 read32(INTEL_VGA_DISPLAY_CONTROL); 790 791 if ((gInfo->head_mode & HEAD_MODE_B_DIGITAL) != 0) { 792 // For LVDS panels, we actually always set the native mode in hardware 793 // Then we use the panel fitter to scale the picture to that. 794 display_mode hardwareTarget; 795 bool needsScaling = false; 796 797 // Try to get the panel preferred screen mode from EDID info 798 if (gInfo->has_edid) { 799 hardwareTarget.space = target.space; 800 hardwareTarget.virtual_width 801 = gInfo->edid_info.std_timing[0].h_size; 802 hardwareTarget.virtual_height 803 = gInfo->edid_info.std_timing[0].v_size; 804 for (int i = 0; i < EDID1_NUM_DETAILED_MONITOR_DESC; i++) { 805 if (gInfo->edid_info.detailed_monitor[i].monitor_desc_type 806 == EDID1_IS_DETAILED_TIMING) { 807 hardwareTarget.virtual_width = gInfo->edid_info 808 .detailed_monitor[i].data.detailed_timing.h_active; 809 hardwareTarget.virtual_height = gInfo->edid_info 810 .detailed_monitor[i].data.detailed_timing.v_active; 811 break; 812 } 813 } 814 TRACE("%s: hardware mode will actually be %dx%d\n", __func__, 815 hardwareTarget.virtual_width, hardwareTarget.virtual_height); 816 if ((hardwareTarget.virtual_width <= target.virtual_width 817 && hardwareTarget.virtual_height <= target.virtual_height 818 && hardwareTarget.space <= target.space) 819 || intel_propose_display_mode(&hardwareTarget, mode, mode)) { 820 hardwareTarget = target; 821 } else 822 needsScaling = true; 823 } else { 824 // We don't have EDID data, try to set the requested mode directly 825 hardwareTarget = target; 826 } 827 828 pll_divisors divisors; 829 if (needsScaling) 830 compute_pll_divisors(hardwareTarget, divisors, true); 831 else 832 compute_pll_divisors(target, divisors, true); 833 834 uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_ENABLED; 835 if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) { 836 dpll |= LVDS_PLL_MODE_LVDS; 837 // DPLL mode LVDS for i915+ 838 } 839 840 // Compute bitmask from p1 value 841 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 842 dpll |= (1 << (divisors.post1 - 1)) 843 << DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT; 844 } else { 845 dpll |= (1 << (divisors.post1 - 1)) 846 << DISPLAY_PLL_POST1_DIVISOR_SHIFT; 847 } 848 switch (divisors.post2) { 849 case 5: 850 case 7: 851 dpll |= DISPLAY_PLL_DIVIDE_HIGH; 852 break; 853 } 854 855 // Disable panel fitting, but enable 8 to 6-bit dithering 856 write32(INTEL_PANEL_FIT_CONTROL, 0x4); 857 // TODO: do not do this if the connected panel is 24-bit 858 // (I don't know how to detect that) 859 860 if ((dpll & DISPLAY_PLL_ENABLED) != 0) { 861 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 862 write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, 863 (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 864 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 865 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 866 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 867 } else { 868 write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, 869 (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 870 & DISPLAY_PLL_N_DIVISOR_MASK) 871 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 872 & DISPLAY_PLL_M1_DIVISOR_MASK) 873 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 874 & DISPLAY_PLL_M2_DIVISOR_MASK)); 875 } 876 write32(INTEL_DISPLAY_B_PLL, dpll & ~DISPLAY_PLL_ENABLED); 877 read32(INTEL_DISPLAY_B_PLL); 878 spin(150); 879 } 880 881 uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT) | LVDS_PORT_EN 882 | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; 883 884 lvds |= LVDS_18BIT_DITHER; 885 // TODO: do not do this if the connected panel is 24-bit 886 // (I don't know how to detect that) 887 888 float referenceClock = gInfo->shared_info->pll_info.reference_frequency 889 / 1000.0f; 890 891 // Set the B0-B3 data pairs corresponding to whether we're going to 892 // set the DPLLs for dual-channel mode or not. 893 if (divisors.post2 == LVDS_POST2_RATE_FAST) 894 lvds |= LVDS_B0B3PAIRS_POWER_UP | LVDS_CLKB_POWER_UP; 895 else 896 lvds &= ~(LVDS_B0B3PAIRS_POWER_UP | LVDS_CLKB_POWER_UP); 897 898 write32(INTEL_DISPLAY_LVDS_PORT, lvds); 899 read32(INTEL_DISPLAY_LVDS_PORT); 900 901 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 902 write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, 903 (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 904 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 905 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 906 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 907 } else { 908 write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, 909 (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 910 & DISPLAY_PLL_N_DIVISOR_MASK) 911 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 912 & DISPLAY_PLL_M1_DIVISOR_MASK) 913 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 914 & DISPLAY_PLL_M2_DIVISOR_MASK)); 915 } 916 917 write32(INTEL_DISPLAY_B_PLL, dpll); 918 read32(INTEL_DISPLAY_B_PLL); 919 920 // Wait for the clocks to stabilize 921 spin(150); 922 923 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) { 924 float adjusted = ((referenceClock * divisors.m) / divisors.n) 925 / divisors.post; 926 uint32 pixelMultiply; 927 if (needsScaling) { 928 pixelMultiply = uint32(adjusted 929 / (hardwareTarget.timing.pixel_clock / 1000.0f)); 930 } else { 931 pixelMultiply = uint32(adjusted 932 / (target.timing.pixel_clock / 1000.0f)); 933 } 934 935 write32(INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR, (0 << 24) 936 | ((pixelMultiply - 1) << 8)); 937 } else 938 write32(INTEL_DISPLAY_B_PLL, dpll); 939 940 read32(INTEL_DISPLAY_B_PLL); 941 spin(150); 942 943 // update timing parameters 944 if (needsScaling) { 945 // TODO: Alternatively, it should be possible to use the panel 946 // fitter and scale the picture. 947 948 // TODO: Perform some sanity check, for example if the target is 949 // wider than the hardware mode we end up with negative borders and 950 // broken timings 951 uint32 borderWidth = hardwareTarget.timing.h_display 952 - target.timing.h_display; 953 954 uint32 syncWidth = hardwareTarget.timing.h_sync_end 955 - hardwareTarget.timing.h_sync_start; 956 957 uint32 syncCenter = target.timing.h_display 958 + (hardwareTarget.timing.h_total 959 - target.timing.h_display) / 2; 960 961 write32(INTEL_DISPLAY_B_HTOTAL, 962 ((uint32)(hardwareTarget.timing.h_total - 1) << 16) 963 | ((uint32)target.timing.h_display - 1)); 964 write32(INTEL_DISPLAY_B_HBLANK, 965 ((uint32)(hardwareTarget.timing.h_total - borderWidth / 2 - 1) 966 << 16) 967 | ((uint32)target.timing.h_display + borderWidth / 2 - 1)); 968 write32(INTEL_DISPLAY_B_HSYNC, 969 ((uint32)(syncCenter + syncWidth / 2 - 1) << 16) 970 | ((uint32)syncCenter - syncWidth / 2 - 1)); 971 972 uint32 borderHeight = hardwareTarget.timing.v_display 973 - target.timing.v_display; 974 975 uint32 syncHeight = hardwareTarget.timing.v_sync_end 976 - hardwareTarget.timing.v_sync_start; 977 978 syncCenter = target.timing.v_display 979 + (hardwareTarget.timing.v_total 980 - target.timing.v_display) / 2; 981 982 write32(INTEL_DISPLAY_B_VTOTAL, 983 ((uint32)(hardwareTarget.timing.v_total - 1) << 16) 984 | ((uint32)target.timing.v_display - 1)); 985 write32(INTEL_DISPLAY_B_VBLANK, 986 ((uint32)(hardwareTarget.timing.v_total - borderHeight / 2 - 1) 987 << 16) 988 | ((uint32)target.timing.v_display 989 + borderHeight / 2 - 1)); 990 write32(INTEL_DISPLAY_B_VSYNC, 991 ((uint32)(syncCenter + syncHeight / 2 - 1) << 16) 992 | ((uint32)syncCenter - syncHeight / 2 - 1)); 993 994 // This is useful for debugging: it sets the border to red, so you 995 // can see what is border and what is porch (black area around the 996 // sync) 997 // write32(0x61020, 0x00FF0000); 998 } else { 999 write32(INTEL_DISPLAY_B_HTOTAL, 1000 ((uint32)(target.timing.h_total - 1) << 16) 1001 | ((uint32)target.timing.h_display - 1)); 1002 write32(INTEL_DISPLAY_B_HBLANK, 1003 ((uint32)(target.timing.h_total - 1) << 16) 1004 | ((uint32)target.timing.h_display - 1)); 1005 write32(INTEL_DISPLAY_B_HSYNC, 1006 ((uint32)(target.timing.h_sync_end - 1) << 16) 1007 | ((uint32)target.timing.h_sync_start - 1)); 1008 1009 write32(INTEL_DISPLAY_B_VTOTAL, 1010 ((uint32)(target.timing.v_total - 1) << 16) 1011 | ((uint32)target.timing.v_display - 1)); 1012 write32(INTEL_DISPLAY_B_VBLANK, 1013 ((uint32)(target.timing.v_total - 1) << 16) 1014 | ((uint32)target.timing.v_display - 1)); 1015 write32(INTEL_DISPLAY_B_VSYNC, ( 1016 (uint32)(target.timing.v_sync_end - 1) << 16) 1017 | ((uint32)target.timing.v_sync_start - 1)); 1018 } 1019 1020 write32(INTEL_DISPLAY_B_IMAGE_SIZE, 1021 ((uint32)(target.virtual_width - 1) << 16) 1022 | ((uint32)target.virtual_height - 1)); 1023 1024 write32(INTEL_DISPLAY_B_POS, 0); 1025 write32(INTEL_DISPLAY_B_PIPE_SIZE, 1026 ((uint32)(target.timing.v_display - 1) << 16) 1027 | ((uint32)target.timing.h_display - 1)); 1028 1029 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 1030 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 1031 | colorMode); 1032 1033 write32(INTEL_DISPLAY_B_PIPE_CONTROL, 1034 read32(INTEL_DISPLAY_B_PIPE_CONTROL) | DISPLAY_PIPE_ENABLED); 1035 read32(INTEL_DISPLAY_B_PIPE_CONTROL); 1036 } 1037 1038 if ((gInfo->head_mode & HEAD_MODE_A_ANALOG) != 0) { 1039 pll_divisors divisors; 1040 compute_pll_divisors(target, divisors, false); 1041 1042 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 1043 write32(INTEL_DISPLAY_A_PLL_DIVISOR_0, 1044 (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 1045 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 1046 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 1047 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 1048 } else { 1049 write32(INTEL_DISPLAY_A_PLL_DIVISOR_0, 1050 (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 1051 & DISPLAY_PLL_N_DIVISOR_MASK) 1052 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 1053 & DISPLAY_PLL_M1_DIVISOR_MASK) 1054 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 1055 & DISPLAY_PLL_M2_DIVISOR_MASK)); 1056 } 1057 1058 uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL; 1059 if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) { 1060 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) { 1061 pll |= ((1 << (divisors.post1 - 1)) 1062 << DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT) 1063 & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK; 1064 } else { 1065 pll |= ((1 << (divisors.post1 - 1)) 1066 << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 1067 & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 1068 // pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 1069 // & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 1070 } 1071 if (divisors.post2_high) 1072 pll |= DISPLAY_PLL_DIVIDE_HIGH; 1073 1074 pll |= DISPLAY_PLL_MODE_ANALOG; 1075 1076 if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) 1077 pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; 1078 } else { 1079 if (!divisors.post2_high) 1080 pll |= DISPLAY_PLL_DIVIDE_4X; 1081 1082 pll |= DISPLAY_PLL_2X_CLOCK; 1083 1084 if (divisors.post1 > 2) { 1085 pll |= ((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 1086 & DISPLAY_PLL_POST1_DIVISOR_MASK; 1087 } else 1088 pll |= DISPLAY_PLL_POST1_DIVIDE_2; 1089 } 1090 1091 write32(INTEL_DISPLAY_A_PLL, pll); 1092 read32(INTEL_DISPLAY_A_PLL); 1093 spin(150); 1094 write32(INTEL_DISPLAY_A_PLL, pll); 1095 read32(INTEL_DISPLAY_A_PLL); 1096 spin(150); 1097 1098 // update timing parameters 1099 write32(INTEL_DISPLAY_A_HTOTAL, 1100 ((uint32)(target.timing.h_total - 1) << 16) 1101 | ((uint32)target.timing.h_display - 1)); 1102 write32(INTEL_DISPLAY_A_HBLANK, 1103 ((uint32)(target.timing.h_total - 1) << 16) 1104 | ((uint32)target.timing.h_display - 1)); 1105 write32(INTEL_DISPLAY_A_HSYNC, 1106 ((uint32)(target.timing.h_sync_end - 1) << 16) 1107 | ((uint32)target.timing.h_sync_start - 1)); 1108 1109 write32(INTEL_DISPLAY_A_VTOTAL, 1110 ((uint32)(target.timing.v_total - 1) << 16) 1111 | ((uint32)target.timing.v_display - 1)); 1112 write32(INTEL_DISPLAY_A_VBLANK, 1113 ((uint32)(target.timing.v_total - 1) << 16) 1114 | ((uint32)target.timing.v_display - 1)); 1115 write32(INTEL_DISPLAY_A_VSYNC, 1116 ((uint32)(target.timing.v_sync_end - 1) << 16) 1117 | ((uint32)target.timing.v_sync_start - 1)); 1118 1119 write32(INTEL_DISPLAY_A_IMAGE_SIZE, 1120 ((uint32)(target.virtual_width - 1) << 16) 1121 | ((uint32)target.virtual_height - 1)); 1122 1123 write32(INTEL_DISPLAY_A_ANALOG_PORT, 1124 (read32(INTEL_DISPLAY_A_ANALOG_PORT) 1125 & ~(DISPLAY_MONITOR_POLARITY_MASK 1126 | DISPLAY_MONITOR_VGA_POLARITY)) 1127 | ((target.timing.flags & B_POSITIVE_HSYNC) != 0 1128 ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0) 1129 | ((target.timing.flags & B_POSITIVE_VSYNC) != 0 1130 ? DISPLAY_MONITOR_POSITIVE_VSYNC : 0)); 1131 1132 // TODO: verify the two comments below: the X driver doesn't seem to 1133 // care about both of them! 1134 1135 // These two have to be set for display B, too - this obviously means 1136 // that the second head always must adopt the color space of the first 1137 // head. 1138 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 1139 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 1140 | colorMode); 1141 1142 if ((gInfo->head_mode & HEAD_MODE_B_DIGITAL) != 0) { 1143 write32(INTEL_DISPLAY_B_IMAGE_SIZE, 1144 ((uint32)(target.virtual_width - 1) << 16) 1145 | ((uint32)target.virtual_height - 1)); 1146 1147 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 1148 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 1149 | colorMode); 1150 } 1151 } 1152 1153 set_display_power_mode(sharedInfo.dpms_mode); 1154 1155 // Changing bytes per row seems to be ignored if the plane/pipe is turned 1156 // off 1157 1158 if (gInfo->head_mode & HEAD_MODE_A_ANALOG) 1159 write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow); 1160 if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) 1161 write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow); 1162 1163 set_frame_buffer_base(); 1164 // triggers writing back double-buffered registers 1165 1166 // update shared info 1167 sharedInfo.bytes_per_row = bytesPerRow; 1168 sharedInfo.current_mode = target; 1169 sharedInfo.bits_per_pixel = bitsPerPixel; 1170 1171 return B_OK; 1172 } 1173 1174 1175 status_t 1176 intel_get_display_mode(display_mode* _currentMode) 1177 { 1178 CALLED(); 1179 1180 retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL); 1181 return B_OK; 1182 } 1183 1184 1185 status_t 1186 intel_get_edid_info(void* info, size_t size, uint32* _version) 1187 { 1188 CALLED(); 1189 1190 if (!gInfo->has_edid) 1191 return B_ERROR; 1192 if (size < sizeof(struct edid1_info)) 1193 return B_BUFFER_OVERFLOW; 1194 1195 memcpy(info, &gInfo->edid_info, sizeof(struct edid1_info)); 1196 *_version = EDID_VERSION_1; 1197 return B_OK; 1198 } 1199 1200 1201 status_t 1202 intel_get_frame_buffer_config(frame_buffer_config* config) 1203 { 1204 CALLED(); 1205 1206 uint32 offset = gInfo->shared_info->frame_buffer_offset; 1207 1208 config->frame_buffer = gInfo->shared_info->graphics_memory + offset; 1209 config->frame_buffer_dma 1210 = (uint8*)gInfo->shared_info->physical_graphics_memory + offset; 1211 config->bytes_per_row = gInfo->shared_info->bytes_per_row; 1212 1213 return B_OK; 1214 } 1215 1216 1217 status_t 1218 intel_get_pixel_clock_limits(display_mode* mode, uint32* _low, uint32* _high) 1219 { 1220 CALLED(); 1221 1222 if (_low != NULL) { 1223 // lower limit of about 48Hz vertical refresh 1224 uint32 totalClocks = (uint32)mode->timing.h_total 1225 * (uint32)mode->timing.v_total; 1226 uint32 low = (totalClocks * 48L) / 1000L; 1227 if (low < gInfo->shared_info->pll_info.min_frequency) 1228 low = gInfo->shared_info->pll_info.min_frequency; 1229 else if (low > gInfo->shared_info->pll_info.max_frequency) 1230 return B_ERROR; 1231 1232 *_low = low; 1233 } 1234 1235 if (_high != NULL) 1236 *_high = gInfo->shared_info->pll_info.max_frequency; 1237 1238 return B_OK; 1239 } 1240 1241 1242 status_t 1243 intel_move_display(uint16 horizontalStart, uint16 verticalStart) 1244 { 1245 CALLED(); 1246 1247 intel_shared_info &sharedInfo = *gInfo->shared_info; 1248 Autolock locker(sharedInfo.accelerant_lock); 1249 1250 display_mode &mode = sharedInfo.current_mode; 1251 1252 if (horizontalStart + mode.timing.h_display > mode.virtual_width 1253 || verticalStart + mode.timing.v_display > mode.virtual_height) 1254 return B_BAD_VALUE; 1255 1256 mode.h_display_start = horizontalStart; 1257 mode.v_display_start = verticalStart; 1258 1259 set_frame_buffer_base(); 1260 1261 return B_OK; 1262 } 1263 1264 1265 status_t 1266 intel_get_timing_constraints(display_timing_constraints* constraints) 1267 { 1268 CALLED(); 1269 return B_ERROR; 1270 } 1271 1272 1273 void 1274 intel_set_indexed_colors(uint count, uint8 first, uint8* colors, uint32 flags) 1275 { 1276 TRACE("%s(colors = %p, first = %u)\n", __func__, colors, first); 1277 1278 if (colors == NULL) 1279 return; 1280 1281 Autolock locker(gInfo->shared_info->accelerant_lock); 1282 1283 for (; count-- > 0; first++) { 1284 uint32 color = colors[0] << 16 | colors[1] << 8 | colors[2]; 1285 colors += 3; 1286 1287 write32(INTEL_DISPLAY_A_PALETTE + first * sizeof(uint32), color); 1288 write32(INTEL_DISPLAY_B_PALETTE + first * sizeof(uint32), color); 1289 } 1290 } 1291 1292