xref: /haiku/src/add-ons/accelerants/intel_extreme/accelerant.h (revision 6f80a9801fedbe7355c4360bd204ba746ec3ec2d)
1 /*
2  * Copyright 2006-2008, Haiku, Inc. All Rights Reserved.
3  * Distributed under the terms of the MIT License.
4  *
5  * Authors:
6  *		Axel Dörfler, axeld@pinc-software.de
7  */
8 #ifndef INTEL_EXTREME_ACCELERANT_H
9 #define INTEL_EXTREME_ACCELERANT_H
10 
11 
12 #include "intel_extreme.h"
13 
14 #include <Debug.h>
15 
16 #include <edid.h>
17 #include <video_overlay.h>
18 
19 #include "Ports.h"
20 #include "Pipes.h"
21 
22 
23 struct overlay {
24 	overlay_buffer	buffer;
25 	addr_t			buffer_base;
26 	uint32			buffer_offset;
27 	addr_t			state_base;
28 	uint32			state_offset;
29 };
30 
31 struct overlay_frame {
32 	int16			h_start;
33 	int16			v_start;
34 	uint16			width;
35 	uint16			height;
36 };
37 
38 struct accelerant_info {
39 	uint8*			registers;
40 	area_id			regs_area;
41 
42 	intel_shared_info* shared_info;
43 	area_id			shared_info_area;
44 
45 	display_mode*	mode_list;		// cloned list of standard display modes
46 	area_id			mode_list_area;
47 
48 	struct overlay_registers* overlay_registers;
49 	overlay*		current_overlay;
50 	overlay_view	last_overlay_view;
51 	overlay_frame	last_overlay_frame;
52 	uint32			last_horizontal_overlay_scale;
53 	uint32			last_vertical_overlay_scale;
54 	uint32			overlay_position_buffer_offset;
55 
56 	uint32			port_count;
57 	Port*			ports[MAX_PORTS];
58 
59 	uint32			pipe_count;
60 	Pipe*			pipes[MAX_PIPES];
61 
62 	edid1_info		edid_info;
63 	bool			has_edid;
64 
65 	// limited 3D support for overlay on i965
66 	addr_t			context_base;
67 	uint32			context_offset;
68 	bool			context_set;
69 
70 	int				device;
71 	uint8			head_mode;
72 	bool			is_clone;
73 };
74 
75 
76 #define HEAD_MODE_A_ANALOG		0x0001
77 #define HEAD_MODE_B_DIGITAL		0x0002
78 #define HEAD_MODE_LVDS_PANEL	0x0008
79 
80 extern accelerant_info* gInfo;
81 
82 // register access
83 
84 inline uint32
85 read32(uint32 encodedRegister)
86 {
87 	return *(volatile uint32*)(gInfo->registers
88 		+ gInfo->shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)]
89 		+ REGISTER_REGISTER(encodedRegister));
90 }
91 
92 inline void
93 write32(uint32 encodedRegister, uint32 value)
94 {
95 	*(volatile uint32*)(gInfo->registers
96 		+ gInfo->shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)]
97 		+ REGISTER_REGISTER(encodedRegister)) = value;
98 }
99 
100 void dump_registers(void);
101 
102 // dpms.cpp
103 extern void enable_display_plane(bool enable);
104 extern void set_display_power_mode(uint32 mode);
105 
106 // engine.cpp
107 extern void uninit_ring_buffer(ring_buffer &ringBuffer);
108 extern void setup_ring_buffer(ring_buffer &ringBuffer, const char* name);
109 
110 // modes.cpp
111 extern void wait_for_vblank(void);
112 extern void set_frame_buffer_base(void);
113 extern status_t create_mode_list(void);
114 
115 // memory.cpp
116 extern void intel_free_memory(addr_t base);
117 extern status_t intel_allocate_memory(size_t size, uint32 flags, addr_t &base);
118 
119 #endif	/* INTEL_EXTREME_ACCELERANT_H */
120