1 /* 2 * Copyright 2011-2015, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz, mmlr@mlotz.ch 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #include "Pipes.h" 10 11 #include "accelerant.h" 12 #include "intel_extreme.h" 13 #include <KernelExport.h> 14 15 #include <stdlib.h> 16 #include <string.h> 17 18 #include <new> 19 20 21 #define TRACE_PIPE 22 #ifdef TRACE_PIPE 23 extern "C" void _sPrintf(const char* format, ...); 24 # define TRACE(x...) _sPrintf("intel_extreme: " x) 25 #else 26 # define TRACE(x...) ; 27 #endif 28 29 #define ERROR(x...) _sPrintf("intel_extreme: " x) 30 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 31 32 33 // PIPE: 6 34 // PLANE: 7 35 36 37 void 38 program_pipe_color_modes(uint32 colorMode) 39 { 40 // All pipes get the same color mode 41 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 42 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 43 | colorMode); 44 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 45 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 46 | colorMode); 47 } 48 49 50 // #pragma mark - Pipe 51 52 53 Pipe::Pipe(pipe_index pipeIndex) 54 : 55 fHasTranscoder(false), 56 fFDILink(NULL), 57 // fPanelFitter(NULL), 58 fPipeIndex(pipeIndex), 59 fPipeOffset(0), 60 fPlaneOffset(0) 61 { 62 if (pipeIndex == INTEL_PIPE_B) { 63 fPipeOffset = INTEL_DISPLAY_OFFSET; 64 fPlaneOffset = INTEL_PLANE_OFFSET; 65 } 66 67 // IvyBridge: Analog + Digital Ports behind FDI (on northbridge) 68 // Haswell: Only VGA behind FDI (on northbridge) 69 // SkyLake: FDI gone. No more northbridge video. 70 if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) { 71 TRACE("%s: Pipe %s routed through FDI\n", __func__, 72 (pipeIndex == INTEL_PIPE_A) ? "A" : "B"); 73 74 fHasTranscoder = true; 75 76 // Program FDILink if PCH 77 fFDILink = new(std::nothrow) FDILink(pipeIndex); 78 } 79 80 TRACE("Pipe %s. Pipe Base: 0x%" B_PRIxADDR 81 " Plane Base: 0x% " B_PRIxADDR "\n", (pipeIndex == INTEL_PIPE_A) 82 ? "A" : "B", fPipeOffset, fPlaneOffset); 83 } 84 85 86 Pipe::~Pipe() 87 { 88 } 89 90 91 bool 92 Pipe::IsEnabled() 93 { 94 CALLED(); 95 96 return (read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset) 97 & INTEL_PIPE_ENABLED) != 0; 98 } 99 100 101 void 102 Pipe::Configure(display_mode* mode) 103 { 104 #if 0 105 // FIXME the previous values are never masked out from the 106 // register, so we just OR things together and hope to fall on a working 107 // mode. Better do nothing at all for now. 108 uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); 109 110 // TODO: Haswell+ dithering changes. 111 if (gInfo->shared_info->device_type.Generation() >= 4) { 112 pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP); 113 // FIXME this makes no sense, if only because B_CMAP8, B_RGB24 and 114 // B_RGB32 have the same color precision (8bit per component). 115 // Also because the color mode is a property of the hardware 116 // (depends on which LVDS panel is used, typically), not the video mode. 117 switch (mode->space) { 118 case B_CMAP8: 119 case B_RGB15_LITTLE: 120 case B_RGB16_LITTLE: 121 pipeControl |= INTEL_PIPE_6BPC; 122 break; 123 case B_RGB24_LITTLE: 124 pipeControl |= INTEL_PIPE_8BPC; 125 break; 126 case B_RGB32_LITTLE: 127 default: 128 pipeControl |= INTEL_PIPE_10BPC; 129 break; 130 } 131 } 132 133 // TODO: CxSR downclocking? 134 135 // TODO: Interlaced modes 136 pipeControl |= INTEL_PIPE_PROGRESSIVE; 137 138 write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl); 139 read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); 140 #endif 141 142 // According to SandyBridge modesetting sequence, pipe must be enabled 143 // before PLL are configured. 144 addr_t pipeReg = INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset; 145 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); 146 147 } 148 149 150 void 151 Pipe::_ConfigureTranscoder(display_mode* target) 152 { 153 CALLED(); 154 155 TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset); 156 157 // update timing (fPipeOffset bumps the DISPLAY_A to B when needed) 158 write32(INTEL_TRANSCODER_A_HTOTAL + fPipeOffset, 159 ((uint32)(target->timing.h_total - 1) << 16) 160 | ((uint32)target->timing.h_display - 1)); 161 write32(INTEL_TRANSCODER_A_HBLANK + fPipeOffset, 162 ((uint32)(target->timing.h_total - 1) << 16) 163 | ((uint32)target->timing.h_display - 1)); 164 write32(INTEL_TRANSCODER_A_HSYNC + fPipeOffset, 165 ((uint32)(target->timing.h_sync_end - 1) << 16) 166 | ((uint32)target->timing.h_sync_start - 1)); 167 168 write32(INTEL_TRANSCODER_A_VTOTAL + fPipeOffset, 169 ((uint32)(target->timing.v_total - 1) << 16) 170 | ((uint32)target->timing.v_display - 1)); 171 write32(INTEL_TRANSCODER_A_VBLANK + fPipeOffset, 172 ((uint32)(target->timing.v_total - 1) << 16) 173 | ((uint32)target->timing.v_display - 1)); 174 write32(INTEL_TRANSCODER_A_VSYNC + fPipeOffset, 175 ((uint32)(target->timing.v_sync_end - 1) << 16) 176 | ((uint32)target->timing.v_sync_start - 1)); 177 178 #if 0 179 // XXX: Is it ok to do these on non-digital? 180 write32(INTEL_TRANSCODER_A_POS + fPipeOffset, 0); 181 write32(INTEL_TRANSCODER_A_IMAGE_SIZE + fPipeOffset, 182 ((uint32)(target->virtual_width - 1) << 16) 183 | ((uint32)target->virtual_height - 1)); 184 #endif 185 } 186 187 188 void 189 Pipe::ConfigureTimings(display_mode* target, bool hardware) 190 { 191 CALLED(); 192 193 TRACE("%s(%d): fPipeOffset: 0x%" B_PRIx32"\n", __func__, hardware, 194 fPipeOffset); 195 196 if (target == NULL) { 197 ERROR("%s: Invalid display mode!\n", __func__); 198 return; 199 } 200 201 /* If using the transcoder, leave the display at its native resolution, 202 * and configure only the transcoder (panel fitting will match them 203 * together). */ 204 if (!fHasTranscoder || hardware) 205 { 206 // update timing (fPipeOffset bumps the DISPLAY_A to B when needed) 207 write32(INTEL_DISPLAY_A_HTOTAL + fPipeOffset, 208 ((uint32)(target->timing.h_total - 1) << 16) 209 | ((uint32)target->timing.h_display - 1)); 210 write32(INTEL_DISPLAY_A_HBLANK + fPipeOffset, 211 ((uint32)(target->timing.h_total - 1) << 16) 212 | ((uint32)target->timing.h_display - 1)); 213 write32(INTEL_DISPLAY_A_HSYNC + fPipeOffset, 214 ((uint32)(target->timing.h_sync_end - 1) << 16) 215 | ((uint32)target->timing.h_sync_start - 1)); 216 217 write32(INTEL_DISPLAY_A_VTOTAL + fPipeOffset, 218 ((uint32)(target->timing.v_total - 1) << 16) 219 | ((uint32)target->timing.v_display - 1)); 220 write32(INTEL_DISPLAY_A_VBLANK + fPipeOffset, 221 ((uint32)(target->timing.v_total - 1) << 16) 222 | ((uint32)target->timing.v_display - 1)); 223 write32(INTEL_DISPLAY_A_VSYNC + fPipeOffset, 224 ((uint32)(target->timing.v_sync_end - 1) << 16) 225 | ((uint32)target->timing.v_sync_start - 1)); 226 } 227 228 if (gInfo->shared_info->device_type.Generation() < 6) { 229 // FIXME check on which generations this register exists 230 // (it appears it would be available only for cursor planes, not 231 // display planes) 232 // Since we set the plane to be the same size as the display, we can 233 // just show it starting at top-left. 234 write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0); 235 } 236 237 // The only thing that really matters: set the image size and let the 238 // panel fitter or the transcoder worry about the rest 239 write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset, 240 ((uint32)(target->virtual_width - 1) << 16) 241 | ((uint32)target->virtual_height - 1)); 242 243 // Set the plane size as well while we're at it (this is independant, we 244 // could have a larger plane and scroll through it). 245 if (gInfo->shared_info->device_type.Generation() <= 4) { 246 // This is "reserved" on G35 and GMA965, but needed on 945 (for which 247 // there is no public documentation), and I assume earlier devices as 248 // well. Note that the height and width are swapped when compared to 249 // the other registers. 250 write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset, 251 ((uint32)(target->virtual_height - 1) << 16) 252 | ((uint32)target->virtual_width - 1)); 253 } 254 255 if (fHasTranscoder && hardware) { 256 _ConfigureTranscoder(target); 257 } 258 } 259 260 261 void 262 Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, 263 uint32 extraFlags) 264 { 265 CALLED(); 266 267 addr_t pllDivisorA = INTEL_DISPLAY_A_PLL_DIVISOR_0; 268 addr_t pllDivisorB = INTEL_DISPLAY_A_PLL_DIVISOR_1; 269 addr_t pllControl = INTEL_DISPLAY_A_PLL; 270 addr_t pllMD = INTEL_DISPLAY_A_PLL_MD; 271 272 if (fPipeIndex == INTEL_PIPE_B) { 273 pllDivisorA = INTEL_DISPLAY_B_PLL_DIVISOR_0; 274 pllDivisorB = INTEL_DISPLAY_B_PLL_DIVISOR_1; 275 pllControl = INTEL_DISPLAY_B_PLL; 276 pllMD = INTEL_DISPLAY_B_PLL_MD; 277 } 278 279 float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 280 281 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) { 282 float adjusted = ((refFreq * divisors.m) / divisors.n) / divisors.p; 283 uint32 pixelMultiply = uint32(adjusted / (pixelClock / 1000.0f)); 284 write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8)); 285 } 286 287 // XXX: For now we assume no LVDS downclocking and program the same divisor 288 // value to both divisor 0 (standard) and 1 (reduced divisor) 289 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { 290 write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 291 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 292 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 293 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 294 write32(pllDivisorB, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 295 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 296 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 297 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 298 } else { 299 write32(pllDivisorA, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 300 & DISPLAY_PLL_N_DIVISOR_MASK) 301 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 302 & DISPLAY_PLL_M1_DIVISOR_MASK) 303 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 304 & DISPLAY_PLL_M2_DIVISOR_MASK)); 305 write32(pllDivisorB, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 306 & DISPLAY_PLL_N_DIVISOR_MASK) 307 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 308 & DISPLAY_PLL_M1_DIVISOR_MASK) 309 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 310 & DISPLAY_PLL_M2_DIVISOR_MASK)); 311 } 312 313 uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags; 314 315 if (gInfo->shared_info->device_type.Generation() >= 3) { 316 // p1 divisor << 1 , 1-8 317 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { 318 pll |= ((1 << (divisors.p1 - 1)) 319 << DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT) 320 & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK; 321 } else { 322 pll |= ((1 << (divisors.p1 - 1)) 323 << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 324 & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 325 // pll |= ((divisors.p1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 326 // & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 327 } 328 329 // Also configure the FP0 divisor on SandyBridge 330 if (gInfo->shared_info->device_type.Generation() == 6) { 331 pll |= ((1 << (divisors.p1 - 1)) 332 << DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT) 333 & DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK; 334 } 335 336 if (divisors.p2 == 5 || divisors.p2 == 7) 337 pll |= DISPLAY_PLL_DIVIDE_HIGH; 338 339 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) 340 pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; 341 } else { 342 if (divisors.p2 != 5 && divisors.p2 != 7) 343 pll |= DISPLAY_PLL_DIVIDE_4X; 344 345 pll |= DISPLAY_PLL_2X_CLOCK; 346 347 // TODO: Is this supposed to be DISPLAY_PLL_IGD_POST1_DIVISOR_MASK?? 348 if (divisors.p1 > 2) { 349 pll |= ((divisors.p1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 350 & DISPLAY_PLL_POST1_DIVISOR_MASK; 351 } else 352 pll |= DISPLAY_PLL_POST1_DIVIDE_2; 353 } 354 355 write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL); 356 // FIXME what is this doing? Why put the PLL back under VGA_CONTROL 357 // here? 358 read32(pllControl); 359 spin(150); 360 361 // Configure and enable the PLL 362 write32(pllControl, pll); 363 read32(pllControl); 364 365 // Allow the PLL to warm up. 366 spin(150); 367 368 if (gInfo->shared_info->device_type.Generation() >= 6) { 369 // SandyBridge has 3 transcoders, but only 2 PLLs. So there is a new 370 // register which routes the PLL output to the transcoder that we need 371 // to configure 372 uint32 pllSel = read32(SNB_DPLL_SEL); 373 TRACE("Old PLL selection: %x\n", pllSel); 374 uint32 shift = 0; 375 uint32 pllIndex = 0; 376 377 // FIXME we assume that pipe A is used with transcoder A, and pipe B 378 // with transcoder B, that may not always be the case 379 if (fPipeIndex == INTEL_PIPE_A) { 380 shift = 0; 381 pllIndex = 0; 382 TRACE("Route PLL A to transcoder A\n"); 383 } else if (fPipeIndex == INTEL_PIPE_B) { 384 shift = 4; 385 pllIndex = 1; 386 TRACE("Route PLL B to transcoder B\n"); 387 } else { 388 ERROR("Attempting to configure PLL for unhandled pipe"); 389 return; 390 } 391 392 // Mask out the previous PLL configuration for this transcoder 393 pllSel &= ~(0xF << shift); 394 395 // Set up the new configuration for this transcoder and enable it 396 pllSel |= (8 | pllIndex) << shift; 397 398 TRACE("New PLL selection: %x\n", pllSel); 399 write32(SNB_DPLL_SEL, pllSel); 400 } 401 } 402 403 404 void 405 Pipe::Enable(bool enable) 406 { 407 CALLED(); 408 409 addr_t pipeReg = INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset; 410 addr_t planeReg = INTEL_DISPLAY_A_CONTROL + fPlaneOffset; 411 412 // Planes always have to operate on an enabled pipe 413 414 if (enable) { 415 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); 416 wait_for_vblank(); 417 write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED); 418 } else { 419 write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED); 420 wait_for_vblank(); 421 write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED); 422 } 423 424 read32(INTEL_DISPLAY_A_BASE); 425 // flush the eventually cached PCI bus writes 426 } 427