1 /* 2 * Copyright 2011-2015, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz, mmlr@mlotz.ch 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #include "Pipes.h" 10 11 #include "accelerant.h" 12 #include "intel_extreme.h" 13 #include <KernelExport.h> 14 15 #include <stdlib.h> 16 #include <string.h> 17 18 #include <new> 19 20 21 #define TRACE_PIPE 22 #ifdef TRACE_PIPE 23 extern "C" void _sPrintf(const char* format, ...); 24 # define TRACE(x...) _sPrintf("intel_extreme: " x) 25 #else 26 # define TRACE(x...) ; 27 #endif 28 29 #define ERROR(x...) _sPrintf("intel_extreme: " x) 30 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 31 32 33 // PIPE: 6 34 // PLANE: 7 35 36 37 void 38 program_pipe_color_modes(uint32 colorMode) 39 { 40 // All pipes get the same color mode 41 if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { 42 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 43 & ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA)) 44 | colorMode); 45 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 46 & ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA)) 47 | colorMode); 48 } else { 49 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 50 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 51 | colorMode); 52 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 53 & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) 54 | colorMode); 55 } 56 } 57 58 59 // #pragma mark - Pipe 60 61 62 Pipe::Pipe(pipe_index pipeIndex) 63 : 64 fHasTranscoder(false), 65 fFDILink(NULL), 66 fPanelFitter(NULL), 67 fPipeIndex(pipeIndex), 68 fPipeOffset(0), 69 fPlaneOffset(0) 70 { 71 if (pipeIndex == INTEL_PIPE_B) { 72 fPlaneOffset = INTEL_PLANE_OFFSET; 73 } 74 switch (pipeIndex) { 75 case INTEL_PIPE_B: 76 TRACE("Pipe B.\n"); 77 fPipeOffset = 0x1000; 78 break; 79 case INTEL_PIPE_C: 80 TRACE("Pipe C.\n"); 81 fPipeOffset = 0x2000; 82 break; 83 case INTEL_PIPE_D: 84 TRACE("Pipe D.\n"); 85 fPipeOffset = 0xf000; 86 break; 87 default: 88 TRACE("Pipe A.\n"); 89 break; 90 } 91 92 // IvyBridge: Analog + Digital Ports behind FDI (on northbridge) 93 // Haswell: Only VGA behind FDI (on northbridge) 94 // SkyLake: FDI gone. No more northbridge video. 95 if ((gInfo->shared_info->pch_info != INTEL_PCH_NONE) && 96 (gInfo->shared_info->device_type.Generation() <= 8)) { 97 TRACE("%s: Pipe %s routed through FDI\n", __func__, 98 (pipeIndex == INTEL_PIPE_A) ? "A" : "B"); 99 100 // Program FDILink if PCH 101 fFDILink = new(std::nothrow) FDILink(pipeIndex); 102 } 103 if (gInfo->shared_info->pch_info != INTEL_PCH_NONE) { 104 // DDI also has transcoders 105 fHasTranscoder = true; 106 // Program gen5(+) style panelfitter as well (DDI has this as well..) 107 fPanelFitter = new(std::nothrow) PanelFitter(pipeIndex); 108 } 109 110 TRACE("Pipe Base: 0x%" B_PRIxADDR " Plane Base: 0x% " B_PRIxADDR "\n", 111 fPipeOffset, fPlaneOffset); 112 } 113 114 115 Pipe::~Pipe() 116 { 117 } 118 119 120 bool 121 Pipe::IsEnabled() 122 { 123 CALLED(); 124 125 return (read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset) 126 & INTEL_PIPE_ENABLED) != 0; 127 } 128 129 130 void 131 Pipe::Configure(display_mode* mode) 132 { 133 uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); 134 135 // TODO: Haswell+ dithering changes. 136 //if (gInfo->shared_info->device_type.Generation() >= 4) { 137 // pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP); 138 139 //Link bit depth: this should be globally known per FDI link (i.e. laptop panel 3x6, rest 3x8) 140 //currently using BIOS preconfigured setup 141 //pipeControl = (pipeControl & ~INTEL_PIPE_BPC_MASK) | INTEL_PIPE_BPC(INTEL_PIPE_8BPC); 142 143 // TODO: CxSR downclocking? 144 145 // TODO: Interlaced modes 146 pipeControl = (pipeControl & ~(0x7 << 21)) | INTEL_PIPE_PROGRESSIVE; 147 148 write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl); 149 read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); 150 151 if (gInfo->shared_info->device_type.Generation() >= 6) { 152 // According to SandyBridge modesetting sequence, pipe must be enabled 153 // before PLL are configured. 154 addr_t pipeReg = INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset; 155 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); 156 } 157 } 158 159 160 void 161 Pipe::_ConfigureTranscoder(display_mode* target) 162 { 163 CALLED(); 164 165 TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset); 166 167 if (gInfo->shared_info->device_type.Generation() < 9) { 168 // update timing (fPipeOffset bumps the DISPLAY_A to B when needed) 169 write32(INTEL_TRANSCODER_A_HTOTAL + fPipeOffset, 170 ((uint32)(target->timing.h_total - 1) << 16) 171 | ((uint32)target->timing.h_display - 1)); 172 write32(INTEL_TRANSCODER_A_HBLANK + fPipeOffset, 173 ((uint32)(target->timing.h_total - 1) << 16) 174 | ((uint32)target->timing.h_display - 1)); 175 write32(INTEL_TRANSCODER_A_HSYNC + fPipeOffset, 176 ((uint32)(target->timing.h_sync_end - 1) << 16) 177 | ((uint32)target->timing.h_sync_start - 1)); 178 179 write32(INTEL_TRANSCODER_A_VTOTAL + fPipeOffset, 180 ((uint32)(target->timing.v_total - 1) << 16) 181 | ((uint32)target->timing.v_display - 1)); 182 write32(INTEL_TRANSCODER_A_VBLANK + fPipeOffset, 183 ((uint32)(target->timing.v_total - 1) << 16) 184 | ((uint32)target->timing.v_display - 1)); 185 write32(INTEL_TRANSCODER_A_VSYNC + fPipeOffset, 186 ((uint32)(target->timing.v_sync_end - 1) << 16) 187 | ((uint32)target->timing.v_sync_start - 1)); 188 189 #if 0 190 // XXX: Is it ok to do these on non-digital? 191 write32(INTEL_TRANSCODER_A_POS + fPipeOffset, 0); 192 write32(INTEL_TRANSCODER_A_IMAGE_SIZE + fPipeOffset, 193 ((uint32)(target->timing.h_display - 1) << 16) 194 | ((uint32)target->timing.v_display - 1)); 195 #endif 196 } else { 197 //on Skylake timing is already done in ConfigureTimings() 198 199 TRACE("%s: trans conf reg: 0x%" B_PRIx32"\n", __func__, 200 read32(DDI_SKL_TRANS_CONF_A + fPipeOffset)); 201 TRACE("%s: trans DDI func ctl reg: 0x%" B_PRIx32"\n", __func__, 202 read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset)); 203 switch ((read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset) & PIPE_DDI_MODESEL_MASK) 204 >> PIPE_DDI_MODESEL_SHIFT) { 205 case PIPE_DDI_MODE_DVI: 206 TRACE("%s: Transcoder uses DVI mode\n", __func__); 207 break; 208 case PIPE_DDI_MODE_DP_SST: 209 TRACE("%s: Transcoder uses DP SST mode\n", __func__); 210 break; 211 case PIPE_DDI_MODE_DP_MST: 212 TRACE("%s: Transcoder uses DP MST mode\n", __func__); 213 break; 214 default: 215 TRACE("%s: Transcoder uses HDMI mode\n", __func__); 216 break; 217 } 218 } 219 } 220 221 222 status_t 223 Pipe::SetFDILink(const display_timing& timing, uint32 linkBandwidth, uint32 lanes, uint32 bitsPerPixel) 224 { 225 TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset); 226 TRACE("%s: FDI/PIPE link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f); 227 TRACE("%s: FDI/PIPE M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset)); 228 TRACE("%s: FDI/PIPE N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset)); 229 TRACE("%s: FDI/PIPE M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset)); 230 TRACE("%s: FDI/PIPE N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset)); 231 232 if ((bitsPerPixel < 18) || (bitsPerPixel > 36)) { 233 ERROR("%s: FDI/PIPE illegal colordepth set.\n", __func__); 234 return B_ERROR; 235 } 236 TRACE("%s: FDI/PIPE link colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel); 237 238 if (lanes > 4) { 239 ERROR("%s: FDI/PIPE illegal number of lanes set.\n", __func__); 240 return B_ERROR; 241 } 242 TRACE("%s: FDI/PIPE link with %" B_PRIx32 " lane(s) in use\n", __func__, lanes); 243 244 //Setup Data M/N 245 uint64 linkspeed = lanes * linkBandwidth * 8; 246 uint64 ret_n = 1; 247 while(ret_n < linkspeed) { 248 ret_n *= 2; 249 } 250 if (ret_n > 0x800000) { 251 ret_n = 0x800000; 252 } 253 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed; 254 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) { 255 ret_m >>= 1; 256 ret_n >>= 1; 257 } 258 //Set TU size bits (to default, max) before link training so that error detection works 259 write32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset, ret_m | FDI_PIPE_MN_TU_SIZE_MASK); 260 write32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset, ret_n); 261 262 //Setup Link M/N 263 linkspeed = linkBandwidth; 264 ret_n = 1; 265 while(ret_n < linkspeed) { 266 ret_n *= 2; 267 } 268 if (ret_n > 0x800000) { 269 ret_n = 0x800000; 270 } 271 ret_m = timing.pixel_clock * ret_n / linkspeed; 272 while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) { 273 ret_m >>= 1; 274 ret_n >>= 1; 275 } 276 write32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset, ret_m); 277 //Writing Link N triggers all four registers to be activated also (on next VBlank) 278 write32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset, ret_n); 279 280 TRACE("%s: FDI/PIPE M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset)); 281 TRACE("%s: FDI/PIPE N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset)); 282 TRACE("%s: FDI/PIPE M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset)); 283 TRACE("%s: FDI/PIPE N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset)); 284 285 return B_OK; 286 } 287 288 289 void 290 Pipe::ConfigureScalePos(display_mode* target) 291 { 292 CALLED(); 293 294 TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset); 295 296 if (target == NULL) { 297 ERROR("%s: Invalid display mode!\n", __func__); 298 return; 299 } 300 301 if (gInfo->shared_info->device_type.Generation() < 6) { 302 // FIXME check on which generations this register exists 303 // (it appears it would be available only for cursor planes, not 304 // display planes) 305 // Since we set the plane to be the same size as the display, we can 306 // just show it starting at top-left. 307 write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0); 308 } 309 310 // The only thing that really matters: set the image size and let the 311 // panel fitter or the transcoder worry about the rest 312 write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset, 313 ((uint32)(target->timing.h_display - 1) << 16) 314 | ((uint32)target->timing.v_display - 1)); 315 316 // Set the plane size as well while we're at it (this is independant, we 317 // could have a larger plane and scroll through it). 318 if ((gInfo->shared_info->device_type.Generation() <= 4) 319 || gInfo->shared_info->device_type.HasDDI()) { 320 // This is "reserved" on G35 and GMA965, but needed on 945 (for which 321 // there is no public documentation), and I assume earlier devices as 322 // well. 323 // 324 // IMPORTANT WARNING: height and width are swapped when compared to the other registers! 325 // Be careful when editing this code and don't accidentally swap them! 326 write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset, 327 ((uint32)(target->timing.v_display - 1) << 16) 328 | ((uint32)target->timing.h_display - 1)); 329 } 330 } 331 332 333 void 334 Pipe::ConfigureTimings(display_mode* target, bool hardware) 335 { 336 CALLED(); 337 338 TRACE("%s(%d): fPipeOffset: 0x%" B_PRIx32"\n", __func__, hardware, 339 fPipeOffset); 340 341 if (target == NULL) { 342 ERROR("%s: Invalid display mode!\n", __func__); 343 return; 344 } 345 346 /* If using the transcoder, leave the display at its native resolution, 347 * and configure only the transcoder (panel fitting will match them 348 * together). */ 349 if (!fHasTranscoder || hardware) 350 { 351 // update timing (fPipeOffset bumps the DISPLAY_A to B when needed) 352 // Note: on Skylake below registers are part of the transcoder 353 write32(INTEL_DISPLAY_A_HTOTAL + fPipeOffset, 354 ((uint32)(target->timing.h_total - 1) << 16) 355 | ((uint32)target->timing.h_display - 1)); 356 write32(INTEL_DISPLAY_A_HBLANK + fPipeOffset, 357 ((uint32)(target->timing.h_total - 1) << 16) 358 | ((uint32)target->timing.h_display - 1)); 359 write32(INTEL_DISPLAY_A_HSYNC + fPipeOffset, 360 ((uint32)(target->timing.h_sync_end - 1) << 16) 361 | ((uint32)target->timing.h_sync_start - 1)); 362 363 write32(INTEL_DISPLAY_A_VTOTAL + fPipeOffset, 364 ((uint32)(target->timing.v_total - 1) << 16) 365 | ((uint32)target->timing.v_display - 1)); 366 write32(INTEL_DISPLAY_A_VBLANK + fPipeOffset, 367 ((uint32)(target->timing.v_total - 1) << 16) 368 | ((uint32)target->timing.v_display - 1)); 369 write32(INTEL_DISPLAY_A_VSYNC + fPipeOffset, 370 ((uint32)(target->timing.v_sync_end - 1) << 16) 371 | ((uint32)target->timing.v_sync_start - 1)); 372 } 373 374 ConfigureScalePos(target); 375 376 if (fHasTranscoder && hardware) { 377 _ConfigureTranscoder(target); 378 } 379 } 380 381 382 void 383 Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, 384 uint32 extraFlags) 385 { 386 CALLED(); 387 388 addr_t pllDivisorA = INTEL_DISPLAY_A_PLL_DIVISOR_0; 389 addr_t pllDivisorB = INTEL_DISPLAY_A_PLL_DIVISOR_1; 390 addr_t pllControl = INTEL_DISPLAY_A_PLL; 391 addr_t pllMD = INTEL_DISPLAY_A_PLL_MD; 392 393 if (fPipeIndex == INTEL_PIPE_B) { 394 pllDivisorA = INTEL_DISPLAY_B_PLL_DIVISOR_0; 395 pllDivisorB = INTEL_DISPLAY_B_PLL_DIVISOR_1; 396 pllControl = INTEL_DISPLAY_B_PLL; 397 pllMD = INTEL_DISPLAY_B_PLL_MD; 398 } 399 400 // Disable DPLL first 401 write32(pllControl, read32(pllControl) & ~DISPLAY_PLL_ENABLED); 402 spin(150); 403 404 float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 405 406 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) { 407 float adjusted = ((refFreq * divisors.m) / divisors.n) / divisors.p; 408 uint32 pixelMultiply = uint32(adjusted / (pixelClock / 1000.0f)); 409 write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8)); 410 } 411 412 // XXX: For now we assume no LVDS downclocking and program the same divisor 413 // value to both divisor 0 (standard) and 1 (reduced divisor) 414 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { 415 write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 416 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 417 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 418 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 419 write32(pllDivisorB, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT) 420 & DISPLAY_PLL_IGD_N_DIVISOR_MASK) 421 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 422 & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)); 423 } else { 424 write32(pllDivisorA, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 425 & DISPLAY_PLL_N_DIVISOR_MASK) 426 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 427 & DISPLAY_PLL_M1_DIVISOR_MASK) 428 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 429 & DISPLAY_PLL_M2_DIVISOR_MASK)); 430 write32(pllDivisorB, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) 431 & DISPLAY_PLL_N_DIVISOR_MASK) 432 | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) 433 & DISPLAY_PLL_M1_DIVISOR_MASK) 434 | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) 435 & DISPLAY_PLL_M2_DIVISOR_MASK)); 436 } 437 438 //note: bit DISPLAY_PLL_NO_VGA_CONTROL does not exist on IvyBridge and should be left 439 // zero there. It does not influence it though. 440 uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags; 441 442 if (gInfo->shared_info->device_type.Generation() >= 3) { 443 // p1 divisor << 1 , 1-8 444 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { 445 pll |= ((1 << (divisors.p1 - 1)) 446 << DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT) 447 & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK; 448 } else { 449 pll |= ((1 << (divisors.p1 - 1)) 450 << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 451 & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 452 // pll |= ((divisors.p1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 453 // & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; 454 } 455 456 // Also configure the FP0 divisor on SandyBridge 457 if (gInfo->shared_info->device_type.Generation() == 6) { 458 pll |= ((1 << (divisors.p1 - 1)) 459 << DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT) 460 & DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK; 461 } 462 463 if (divisors.p2 == 5 || divisors.p2 == 7) 464 pll |= DISPLAY_PLL_DIVIDE_HIGH; 465 466 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) 467 pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; 468 } else { 469 if (divisors.p2 != 5 && divisors.p2 != 7) 470 pll |= DISPLAY_PLL_DIVIDE_4X; 471 472 pll |= DISPLAY_PLL_2X_CLOCK; 473 474 // TODO: Is this supposed to be DISPLAY_PLL_IGD_POST1_DIVISOR_MASK?? 475 if (divisors.p1 > 2) { 476 pll |= ((divisors.p1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) 477 & DISPLAY_PLL_POST1_DIVISOR_MASK; 478 } else 479 pll |= DISPLAY_PLL_POST1_DIVIDE_2; 480 } 481 482 // Configure PLL while -keeping- it disabled 483 //note: on older chipsets DISPLAY_PLL_NO_VGA_CONTROL probably enables the PLL and locks regs; 484 // on newer chipsets DISPLAY_PLL_ENABLED does this. 485 write32(pllControl, pll & ~DISPLAY_PLL_ENABLED & ~DISPLAY_PLL_NO_VGA_CONTROL); 486 read32(pllControl); 487 spin(150); 488 489 // enable pre-configured PLL (locks PLL settings directly blocking changes in this write even) 490 write32(pllControl, pll); 491 read32(pllControl); 492 493 // Allow the PLL to warm up. 494 spin(150); 495 496 if (gInfo->shared_info->device_type.Generation() >= 6) { 497 // SandyBridge has 3 transcoders, but only 2 PLLs. So there is a new 498 // register which routes the PLL output to the transcoder that we need 499 // to configure 500 uint32 pllSel = read32(SNB_DPLL_SEL); 501 TRACE("Old PLL selection: 0x%" B_PRIx32 "\n", pllSel); 502 uint32 shift = 0; 503 uint32 pllIndex = 0; 504 505 // FIXME we assume that pipe A is used with transcoder A, and pipe B 506 // with transcoder B, that may not always be the case 507 if (fPipeIndex == INTEL_PIPE_A) { 508 shift = 0; 509 pllIndex = 0; 510 TRACE("Route PLL A to transcoder A\n"); 511 } else if (fPipeIndex == INTEL_PIPE_B) { 512 shift = 4; 513 pllIndex = 1; 514 TRACE("Route PLL B to transcoder B\n"); 515 } else { 516 ERROR("Attempting to configure PLL for unhandled pipe"); 517 return; 518 } 519 520 // Mask out the previous PLL configuration for this transcoder 521 pllSel &= ~(0xF << shift); 522 523 // Set up the new configuration for this transcoder and enable it 524 pllSel |= (8 | pllIndex) << shift; 525 526 TRACE("New PLL selection: 0x%" B_PRIx32 "\n", pllSel); 527 write32(SNB_DPLL_SEL, pllSel); 528 } 529 } 530 531 void 532 Pipe::ConfigureClocksSKL(const skl_wrpll_params& wrpll_params, uint32 pixelClock, 533 port_index pllForPort, uint32* pllSel) 534 { 535 CALLED(); 536 537 //find our PLL as set by the BIOS 538 uint32 portSel = read32(SKL_DPLL_CTRL2); 539 *pllSel = 0xff; 540 switch (pllForPort) { 541 case INTEL_PORT_A: 542 *pllSel = (portSel & 0x0006) >> 1; 543 break; 544 case INTEL_PORT_B: 545 *pllSel = (portSel & 0x0030) >> 4; 546 break; 547 case INTEL_PORT_C: 548 *pllSel = (portSel & 0x0180) >> 7; 549 break; 550 case INTEL_PORT_D: 551 *pllSel = (portSel & 0x0c00) >> 10; 552 break; 553 case INTEL_PORT_E: 554 *pllSel = (portSel & 0x6000) >> 13; 555 break; 556 default: 557 TRACE("No port selected!"); 558 return; 559 } 560 TRACE("PLL selected is %" B_PRIx32 "\n", *pllSel); 561 562 TRACE("Skylake DPLL_CFGCR1 0x%" B_PRIx32 "\n", 563 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8)); 564 TRACE("Skylake DPLL_CFGCR2 0x%" B_PRIx32 "\n", 565 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8)); 566 567 // only program PLL's that are in non-DP mode (otherwise the linkspeed sets refresh) 568 portSel = read32(SKL_DPLL_CTRL1); 569 if ((portSel & (1 << (*pllSel * 6 + 5))) && *pllSel) { // DPLL0 might only know DP mode 570 // enable pgm on our PLL in case that's currently disabled 571 write32(SKL_DPLL_CTRL1, portSel | (1 << (*pllSel * 6))); 572 573 write32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8, 574 1 << 31 | 575 wrpll_params.dco_fraction << 9 | 576 wrpll_params.dco_integer); 577 write32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8, 578 wrpll_params.qdiv_ratio << 8 | 579 wrpll_params.qdiv_mode << 7 | 580 wrpll_params.kdiv << 5 | 581 wrpll_params.pdiv << 2 | 582 wrpll_params.central_freq); 583 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8); 584 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8); 585 586 //assuming DPLL0 and 1 are already enabled by the BIOS if in use (LCPLL1,2 regs) 587 588 spin(5); 589 if (read32(SKL_DPLL_STATUS) & (1 << (*pllSel * 8))) { 590 TRACE("Programmed PLL; PLL is locked\n"); 591 } else { 592 TRACE("Programmed PLL; PLL did not lock\n"); 593 } 594 TRACE("Skylake DPLL_CFGCR1 now: 0x%" B_PRIx32 "\n", 595 read32(SKL_DPLL1_CFGCR1 + (*pllSel - 1) * 8)); 596 TRACE("Skylake DPLL_CFGCR2 now: 0x%" B_PRIx32 "\n", 597 read32(SKL_DPLL1_CFGCR2 + (*pllSel - 1) * 8)); 598 } else { 599 TRACE("PLL programming not needed, skipping.\n"); 600 } 601 602 TRACE("Skylake DPLL_CTRL1: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL1)); 603 TRACE("Skylake DPLL_CTRL2: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL2)); 604 TRACE("Skylake DPLL_STATUS: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_STATUS)); 605 } 606 607 void 608 Pipe::Enable(bool enable) 609 { 610 CALLED(); 611 612 addr_t pipeReg = INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset; 613 addr_t planeReg = INTEL_DISPLAY_A_CONTROL + fPlaneOffset; 614 615 // Planes always have to operate on an enabled pipe 616 617 if (enable) { 618 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); 619 wait_for_vblank(); 620 write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED); 621 622 //Enable default display main watermarks 623 if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) { 624 if (fPipeOffset == 0) 625 write32(INTEL_DISPLAY_A_PIPE_WATERMARK, 0x0783818); 626 else 627 write32(INTEL_DISPLAY_B_PIPE_WATERMARK, 0x0783818); 628 } 629 } else { 630 write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED); 631 wait_for_vblank(); 632 //Sandy+: when link training is to be done re-enable this line but otherwise don't touch! 633 //GMA(Q45): must disable PIPE or DPLL programming fails. 634 if (gInfo->shared_info->device_type.Generation() <= 5) { 635 write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED); 636 } 637 } 638 639 // flush the eventually cached PCI bus writes 640 read32(INTEL_DISPLAY_A_BASE); 641 } 642