1 /* 2 Haiku ATI video driver adapted from the X.org ATI driver. 3 4 Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, 5 Precision Insight, Inc., Cedar Park, Texas, and 6 VA Linux Systems Inc., Fremont, California. 7 8 Copyright 2009 Haiku, Inc. All rights reserved. 9 Distributed under the terms of the MIT license. 10 11 Authors: 12 Gerald Zajac 2009 13 */ 14 15 16 #ifndef __RAGE128_H__ 17 #define __RAGE128_H__ 18 19 20 #define CURSOR_BYTES 1024 // bytes used for cursor image in video memory 21 22 #define R128_TIMEOUT 2000000 // Fall out of wait loops after this count 23 24 25 // Register MMIO addresses. 26 //------------------------- 27 28 #define R128_AUX_SC_CNTL 0x1660 29 30 #define R128_BUS_CNTL 0x0030 31 # define R128_BUS_MASTER_DIS (1 << 6) 32 # define R128_BUS_RD_DISCARD_EN (1 << 24) 33 # define R128_BUS_RD_ABORT_EN (1 << 25) 34 # define R128_BUS_MSTR_DISCONNECT_EN (1 << 28) 35 # define R128_BUS_WRT_BURST (1 << 29) 36 # define R128_BUS_READ_BURST (1 << 30) 37 38 #define R128_CAP0_TRIG_CNTL 0x0950 // ? 39 #define R128_CAP1_TRIG_CNTL 0x09c0 // ? 40 #define R128_CLOCK_CNTL_DATA 0x000c 41 #define R128_CLOCK_CNTL_INDEX 0x0008 42 # define R128_PLL_WR_EN (1 << 7) 43 # define R128_PLL_DIV_SEL (3 << 8) 44 #define R128_CONFIG_MEMSIZE 0x00f8 45 #define R128_CRTC_EXT_CNTL 0x0054 46 # define R128_CRTC_VGA_XOVERSCAN (1 << 0) 47 # define R128_VGA_ATI_LINEAR (1 << 3) 48 # define R128_XCRT_CNT_EN (1 << 6) 49 # define R128_CRTC_HSYNC_DIS (1 << 8) 50 # define R128_CRTC_VSYNC_DIS (1 << 9) 51 # define R128_CRTC_DISPLAY_DIS (1 << 10) 52 # define R128_CRTC_CRT_ON (1 << 15) 53 # define R128_FP_OUT_EN (1 << 22) 54 # define R128_FP_ACTIVE (1 << 23) 55 #define R128_CRTC_GEN_CNTL 0x0050 56 # define R128_CRTC_CUR_EN (1 << 16) 57 # define R128_CRTC_EXT_DISP_EN (1 << 24) 58 # define R128_CRTC_EN (1 << 25) 59 #define R128_CRTC_H_SYNC_STRT_WID 0x0204 60 # define R128_CRTC_H_SYNC_POL (1 << 23) 61 #define R128_CRTC_H_TOTAL_DISP 0x0200 62 #define R128_CRTC_OFFSET 0x0224 63 #define R128_CRTC_OFFSET_CNTL 0x0228 64 #define R128_CRTC_PITCH 0x022c 65 #define R128_CRTC_V_SYNC_STRT_WID 0x020c 66 # define R128_CRTC_V_SYNC_POL (1 << 23) 67 #define R128_CRTC_V_TOTAL_DISP 0x0208 68 #define R128_CUR_CLR0 0x026c 69 #define R128_CUR_CLR1 0x0270 70 #define R128_CUR_HORZ_VERT_OFF 0x0268 71 #define R128_CUR_HORZ_VERT_POSN 0x0264 72 #define R128_CUR_OFFSET 0x0260 73 # define R128_CUR_LOCK (1 << 31) 74 75 #define R128_DAC_CNTL 0x0058 76 # define R128_DAC_RANGE_CNTL (3 << 0) 77 # define R128_DAC_BLANKING (1 << 2) 78 # define R128_DAC_CRT_SEL_CRTC2 (1 << 4) 79 # define R128_DAC_PALETTE_ACC_CTL (1 << 5) 80 # define R128_DAC_8BIT_EN (1 << 8) 81 # define R128_DAC_VGA_ADR_EN (1 << 13) 82 # define R128_DAC_MASK_ALL (0xff << 24) 83 #define R128_DDA_CONFIG 0x02e0 84 #define R128_DDA_ON_OFF 0x02e4 85 #define R128_DEFAULT_OFFSET 0x16e0 86 #define R128_DEFAULT_PITCH 0x16e4 87 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 88 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 89 # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 90 #define R128_DP_BRUSH_BKGD_CLR 0x1478 91 #define R128_DP_BRUSH_FRGD_CLR 0x147c 92 #define R128_DP_CNTL 0x16c0 93 # define R128_DST_X_LEFT_TO_RIGHT (1 << 0) 94 # define R128_DST_Y_TOP_TO_BOTTOM (1 << 1) 95 #define R128_DP_DATATYPE 0x16c4 96 # define R128_HOST_BIG_ENDIAN_EN (1 << 29) 97 #define R128_DP_GUI_MASTER_CNTL 0x146c 98 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 99 # define R128_GMC_AUX_CLIP_DIS (1 << 29) 100 # define R128_GMC_BRUSH_NONE (15 << 4) 101 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 102 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 103 # define R128_GMC_DST_DATATYPE_SHIFT 8 104 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 105 # define R128_ROP3_Dn 0x00550000 106 # define R128_ROP3_P 0x00f00000 107 # define R128_ROP3_S 0x00cc0000 108 #define R128_DP_SRC_BKGD_CLR 0x15dc 109 #define R128_DP_SRC_FRGD_CLR 0x15d8 110 #define R128_DP_WRITE_MASK 0x16cc 111 #define R128_DST_BRES_DEC 0x1630 112 #define R128_DST_BRES_ERR 0x1628 113 #define R128_DST_BRES_INC 0x162c 114 #define R128_DST_HEIGHT_WIDTH 0x143c 115 #define R128_DST_WIDTH_HEIGHT 0x1598 116 #define R128_DST_Y_X 0x1438 117 118 #define R128_FP_CRTC_H_TOTAL_DISP 0x0250 119 #define R128_FP_CRTC_V_TOTAL_DISP 0x0254 120 #define R128_FP_GEN_CNTL 0x0284 121 # define R128_FP_FPON (1 << 0) 122 # define R128_FP_BLANK_DIS (1 << 1) 123 # define R128_FP_TDMS_EN (1 << 2) 124 # define R128_FP_DETECT_SENSE (1 << 8) 125 # define R128_FP_SEL_CRTC2 (1 << 13) 126 # define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 127 # define R128_FP_CRTC_DONT_SHADOW_HEND (1 << 17) 128 # define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18) 129 # define R128_FP_CRTC_USE_SHADOW_ROWCUR (1 << 19) 130 # define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20) 131 # define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21) 132 # define R128_FP_CRT_SYNC_SEL (1 << 23) 133 # define R128_FP_USE_SHADOW_EN (1 << 24) 134 #define R128_FP_H_SYNC_STRT_WID 0x02c4 135 #define R128_FP_HORZ_STRETCH 0x028c 136 # define R128_HORZ_STRETCH_RATIO_MASK 0xfff 137 # define R128_HORZ_STRETCH_RATIO_SHIFT 0 138 # define R128_HORZ_STRETCH_RATIO_MAX 4096 139 # define R128_HORZ_PANEL_SIZE (0xff << 16) 140 # define R128_HORZ_PANEL_SHIFT 16 141 # define R128_AUTO_HORZ_RATIO (0 << 24) 142 # define R128_HORZ_STRETCH_PIXREP (0 << 25) 143 # define R128_HORZ_STRETCH_BLEND (1 << 25) 144 # define R128_HORZ_STRETCH_ENABLE (1 << 26) 145 # define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27) 146 # define R128_HORZ_STRETCH_RESERVED (1 << 30) 147 # define R128_HORZ_AUTO_RATIO_FIX_EN (1 << 31) 148 149 #define R128_FP_PANEL_CNTL 0x0288 150 # define R128_FP_DIGON (1 << 0) 151 # define R128_FP_BLON (1 << 1) 152 #define R128_FP_V_SYNC_STRT_WID 0x02c8 153 #define R128_FP_VERT_STRETCH 0x0290 154 # define R128_VERT_PANEL_SIZE (0x7ff << 0) 155 # define R128_VERT_PANEL_SHIFT 0 156 # define R128_VERT_STRETCH_RATIO_MASK 0x3ff 157 # define R128_VERT_STRETCH_RATIO_SHIFT 11 158 # define R128_VERT_STRETCH_RATIO_MAX 1024 159 # define R128_VERT_STRETCH_ENABLE (1 << 24) 160 # define R128_VERT_STRETCH_LINEREP (0 << 25) 161 # define R128_VERT_STRETCH_BLEND (1 << 25) 162 # define R128_VERT_AUTO_RATIO_EN (1 << 26) 163 # define R128_VERT_STRETCH_RESERVED 0xf8e00000 164 165 #define R128_GEN_INT_CNTL 0x0040 166 #define R128_GEN_RESET_CNTL 0x00f0 167 # define R128_SOFT_RESET_GUI (1 << 0) 168 #define R128_GPIO_MONID 0x0068 169 # define R128_GPIO_MONID_A_0 (1 << 0) 170 # define R128_GPIO_MONID_A_3 (1 << 3) 171 # define R128_GPIO_MONID_Y_0 (1 << 8) 172 # define R128_GPIO_MONID_Y_3 (1 << 11) 173 # define R128_GPIO_MONID_EN_0 (1 << 16) 174 # define R128_GPIO_MONID_EN_3 (1 << 19) 175 # define R128_GPIO_MONID_MASK_0 (1 << 24) 176 # define R128_GPIO_MONID_MASK_3 (1 << 27) 177 #define R128_GUI_PROBE 0x16bc 178 #define R128_GUI_STAT 0x1740 179 # define R128_GUI_FIFOCNT_MASK 0x0fff 180 # define R128_GUI_ACTIVE (1 << 31) 181 182 #define R128_HTOTAL_CNTL 0x0009 // PLL 183 184 #define R128_I2C_CNTL_1 0x0094 // ? 185 186 #define R128_LVDS_GEN_CNTL 0x02d0 187 # define R128_LVDS_ON (1 << 0) 188 # define R128_LVDS_DISPLAY_DIS (1 << 1) 189 # define R128_LVDS_EN (1 << 7) 190 # define R128_LVDS_DIGON (1 << 18) 191 # define R128_LVDS_BLON (1 << 19) 192 # define R128_LVDS_SEL_CRTC2 (1 << 23) 193 # define R128_HSYNC_DELAY_SHIFT 28 194 # define R128_HSYNC_DELAY_MASK (0xf << 28) 195 196 #define R128_MCLK_CNTL 0x000f /* PLL */ 197 # define R128_FORCE_GCP (1 << 16) 198 # define R128_FORCE_PIPE3D_CP (1 << 17) 199 #define R128_MEM_CNTL 0x0140 200 #define R128_MPP_TB_CONFIG 0x01c0 // ? 201 #define R128_MPP_GP_CONFIG 0x01c8 // ? 202 203 #define R128_OVR_CLR 0x0230 204 #define R128_OVR_WID_LEFT_RIGHT 0x0234 205 #define R128_OVR_WID_TOP_BOTTOM 0x0238 206 #define R128_OV0_SCALE_CNTL 0x0420 207 208 #define R128_PALETTE_DATA 0x00b4 209 #define R128_PALETTE_INDEX 0x00b0 210 #define R128_PC_NGUI_CTLSTAT 0x0184 211 # define R128_PC_FLUSH_ALL 0x00ff 212 # define R128_PC_BUSY (1 << 31) 213 #define R128_PPLL_CNTL 0x0002 // PLL 214 # define R128_PPLL_RESET (1 << 0) 215 # define R128_PPLL_SLEEP (1 << 1) 216 # define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16) 217 # define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 218 #define R128_PPLL_DIV_3 0x0007 // PLL 219 # define R128_PPLL_FB3_DIV_MASK 0x07ff 220 # define R128_PPLL_POST3_DIV_MASK 0x00070000 221 #define R128_PPLL_REF_DIV 0x0003 // PLL 222 # define R128_PPLL_REF_DIV_MASK 0x03ff 223 # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) // same as _W 224 # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) // same as _R 225 226 #define R128_SC_BOTTOM_RIGHT 0x16f0 227 #define R128_SC_TOP_LEFT 0x16ec 228 #define R128_SCALE_3D_CNTL 0x1a00 229 #define R128_SRC_Y_X 0x1434 230 #define R128_SUBPIC_CNTL 0x0540 // ? 231 232 #define R128_TMDS_CRC 0x02a0 233 234 #define R128_VCLK_ECP_CNTL 0x0008 // PLL 235 # define R128_VCLK_SRC_SEL_MASK 0x03 236 # define R128_VCLK_SRC_SEL_CPUCLK 0x00 237 # define R128_VCLK_SRC_SEL_PPLLCLK 0x03 238 #define R128_VIPH_CONTROL 0x01D0 // ? 239 240 241 242 // Functions to get/set PLL registers. 243 //======================================= 244 245 static inline uint32 246 GetPLLReg(uint8 index) 247 { 248 OUTREG8(R128_CLOCK_CNTL_INDEX, index & 0x3f); 249 return INREG(R128_CLOCK_CNTL_DATA); 250 } 251 252 253 static inline void 254 SetPLLReg(uint8 index, uint32 value) 255 { 256 OUTREG8(R128_CLOCK_CNTL_INDEX, ((index) & 0x3f) | R128_PLL_WR_EN); 257 OUTREG(R128_CLOCK_CNTL_DATA, value); 258 } 259 260 261 static inline void 262 SetPLLReg(uint8 index, uint32 value, uint32 mask) 263 { 264 // Write a value to a PLL reg using a mask. The mask selects the 265 // bits to be modified. 266 267 SetPLLReg(index, (GetPLLReg(index) & ~mask) | (value & mask)); 268 } 269 270 271 #endif // __RAGE128_H__ 272