1 /* 2 Haiku ATI video driver adapted from the X.org ATI driver. 3 4 Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina. 5 6 Copyright 2009 Haiku, Inc. All rights reserved. 7 Distributed under the terms of the MIT license. 8 9 Authors: 10 Gerald Zajac 2009 11 */ 12 13 #ifndef __MACH64_H__ 14 #define __MACH64_H__ 15 16 17 #define CURSOR_BYTES 1024 // bytes used for cursor image in video memory 18 19 // Memory types for Mach64 chips. 20 21 enum Mach64_MemoryType 22 { 23 MEM_NONE, 24 MEM_DRAM, 25 MEM_EDO, 26 MEM_PSEUDO_EDO, 27 MEM_SDRAM, 28 MEM_SGRAM, 29 MEM_SGRAM32, 30 MEM_TYPE_7 31 }; 32 33 34 // Macros to get/set a contiguous bit field. Arguments should not be 35 // self-modifying. 36 37 #define UnitOf(___Value) (((((___Value) ^ ((___Value) - 1)) + 1) >> 1) \ 38 | ((((___Value) ^ ((___Value) - 1)) >> 1) + 1)) 39 40 #define GetBits(__Value, _Mask) (((__Value) & (_Mask)) / UnitOf(_Mask)) 41 #define SetBits(__Value, _Mask) (((__Value) * UnitOf(_Mask)) & (_Mask)) 42 43 44 // Register MMIO addresses - expressed in BYTE offsets. 45 //----------------------------------------------------- 46 47 #define CRTC_H_TOTAL_DISP (0x0c00 + 0x0000) // Dword offset 00 48 #define CRTC_H_SYNC_STRT_WID (0x0c00 + 0x0004) // Dword offset 01 49 #define CRTC_V_TOTAL_DISP (0x0c00 + 0x0008) // Dword offset 02 50 #define CRTC_V_SYNC_STRT_WID (0x0c00 + 0x000C) // Dword offset 03 51 #define CRTC_VLINE_CRNT_VLINE (0x0c00 + 0x0010) // Dword offset 04 52 #define CRTC_OFF_PITCH (0x0c00 + 0x0014) // Dword offset 05 53 #define CRTC_INT_CNTL (0x0c00 + 0x0018) // Dword offset 06 54 #define CRTC_GEN_CNTL (0x0c00 + 0x001C) // Dword offset 07 55 56 #define DSP_CONFIG (0x0c00 + 0x0020) // Dword offset 08 57 #define DSP_ON_OFF (0x0c00 + 0x0024) // Dword offset 09 58 59 #define SHARED_CNTL (0x0c00 + 0x0038) // Dword offset 0E 60 61 #define OVR_CLR (0x0c00 + 0x0040) // Dword offset 10 62 #define OVR_WID_LEFT_RIGHT (0x0c00 + 0x0044) // Dword offset 11 63 #define OVR_WID_TOP_BOTTOM (0x0c00 + 0x0048) // Dword offset 12 64 65 #define CUR_CLR0 (0x0c00 + 0x0060) // Dword offset 18 66 #define CUR_CLR1 (0x0c00 + 0x0064) // Dword offset 19 67 #define CUR_OFFSET (0x0c00 + 0x0068) // Dword offset 1A 68 #define CUR_HORZ_VERT_POSN (0x0c00 + 0x006C) // Dword offset 1B 69 #define CUR_HORZ_VERT_OFF (0x0c00 + 0x0070) // Dword offset 1C 70 71 #define HW_DEBUG (0x0c00 + 0x007C) // Dword offset 1F 72 73 #define SCRATCH_REG0 (0x0c00 + 0x0080) // Dword offset 20 74 #define SCRATCH_REG1 (0x0c00 + 0x0084) // Dword offset 21 75 76 #define CLOCK_CNTL (0x0c00 + 0x0090) // Dword offset 24 77 78 #define BUS_CNTL (0x0c00 + 0x00A0) // Dword offset 28 79 80 #define LCD_INDEX (0x0c00 + 0x00A4) // Dword offset 29 81 #define LCD_DATA (0x0c00 + 0x00A8) // Dword offset 2A 82 83 #define MEM_CNTL (0x0c00 + 0x00B0) // Dword offset 2C 84 85 #define MEM_VGA_WP_SEL (0x0c00 + 0x00B4) // Dword offset 2D 86 #define MEM_VGA_RP_SEL (0x0c00 + 0x00B8) // Dword offset 2E 87 88 #define DAC_REGS (0x0c00 + 0x00C0) // Dword offset 30 89 #define DAC_W_INDEX (DAC_REGS + 0) 90 #define DAC_DATA (DAC_REGS + 1) 91 #define DAC_MASK (DAC_REGS + 2) 92 #define DAC_R_INDEX (DAC_REGS + 3) 93 #define DAC_CNTL (0x0c00 + 0x00C4) // Dword offset 31 94 95 #define GEN_TEST_CNTL (0x0c00 + 0x00D0) // Dword offset 34 96 97 #define CONFIG_CNTL (0x0c00 + 0x00DC // Dword offset 37 (CT, ET, VT) 98 #define CONFIG_CHIP_ID (0x0c00 + 0x00E0) // Dword offset 38 99 #define CONFIG_STAT0 (0x0c00 + 0x00E4) // Dword offset 39 100 #define CONFIG_STAT1 (0x0c00 + 0x00E8) // Dword offset 3A 101 102 #define DST_OFF_PITCH (0x0c00 + 0x0100) // Dword offset 40 103 #define DST_X (0x0c00 + 0x0104) // Dword offset 41 104 #define DST_Y (0x0c00 + 0x0108) // Dword offset 42 105 #define DST_Y_X (0x0c00 + 0x010C) // Dword offset 43 106 #define DST_WIDTH (0x0c00 + 0x0110) // Dword offset 44 107 #define DST_HEIGHT (0x0c00 + 0x0114) // Dword offset 45 108 #define DST_HEIGHT_WIDTH (0x0c00 + 0x0118) // Dword offset 46 109 #define DST_X_WIDTH (0x0c00 + 0x011C) // Dword offset 47 110 #define DST_BRES_LNTH (0x0c00 + 0x0120) // Dword offset 48 111 #define DST_BRES_ERR (0x0c00 + 0x0124) // Dword offset 49 112 #define DST_BRES_INC (0x0c00 + 0x0128) // Dword offset 4A 113 #define DST_BRES_DEC (0x0c00 + 0x012C) // Dword offset 4B 114 #define DST_CNTL (0x0c00 + 0x0130) // Dword offset 4C 115 116 #define SRC_OFF_PITCH (0x0c00 + 0x0180) // Dword offset 60 117 #define SRC_X (0x0c00 + 0x0184) // Dword offset 61 118 #define SRC_Y (0x0c00 + 0x0188) // Dword offset 62 119 #define SRC_Y_X (0x0c00 + 0x018C) // Dword offset 63 120 #define SRC_WIDTH1 (0x0c00 + 0x0190) // Dword offset 64 121 #define SRC_HEIGHT1 (0x0c00 + 0x0194) // Dword offset 65 122 #define SRC_HEIGHT1_WIDTH1 (0x0c00 + 0x0198) // Dword offset 66 123 #define SRC_X_START (0x0c00 + 0x019C) // Dword offset 67 124 #define SRC_Y_START (0x0c00 + 0x01A0) // Dword offset 68 125 #define SRC_Y_X_START (0x0c00 + 0x01A4) // Dword offset 69 126 #define SRC_WIDTH2 (0x0c00 + 0x01A8) // Dword offset 6A 127 #define SRC_HEIGHT2 (0x0c00 + 0x01AC) // Dword offset 6B 128 #define SRC_HEIGHT2_WIDTH2 (0x0c00 + 0x01B0) // Dword offset 6C 129 #define SRC_CNTL (0x0c00 + 0x01B4) // Dword offset 6D 130 131 #define HOST_DATA0 (0x0c00 + 0x0200) // Dword offset 80 132 #define HOST_DATA1 (0x0c00 + 0x0204) // Dword offset 81 133 #define HOST_DATA2 (0x0c00 + 0x0208) // Dword offset 82 134 #define HOST_DATA3 (0x0c00 + 0x020C) // Dword offset 83 135 #define HOST_DATA4 (0x0c00 + 0x0210) // Dword offset 84 136 #define HOST_DATA5 (0x0c00 + 0x0214) // Dword offset 85 137 #define HOST_DATA6 (0x0c00 + 0x0218) // Dword offset 86 138 #define HOST_DATA7 (0x0c00 + 0x021C) // Dword offset 87 139 #define HOST_DATA8 (0x0c00 + 0x0220) // Dword offset 88 140 #define HOST_DATA9 (0x0c00 + 0x0224) // Dword offset 89 141 #define HOST_DATAA (0x0c00 + 0x0228) // Dword offset 8A 142 #define HOST_DATAB (0x0c00 + 0x022C) // Dword offset 8B 143 #define HOST_DATAC (0x0c00 + 0x0230) // Dword offset 8C 144 #define HOST_DATAD (0x0c00 + 0x0234) // Dword offset 8D 145 #define HOST_DATAE (0x0c00 + 0x0238) // Dword offset 8E 146 #define HOST_DATAF (0x0c00 + 0x023C) // Dword offset 8F 147 #define HOST_CNTL (0x0c00 + 0x0240) // Dword offset 90 148 149 #define PAT_REG0 (0x0c00 + 0x0280) // Dword offset A0 150 #define PAT_REG1 (0x0c00 + 0x0284) // Dword offset A1 151 #define PAT_CNTL (0x0c00 + 0x0288) // Dword offset A2 152 153 #define SC_LEFT (0x0c00 + 0x02A0) // Dword offset A8 154 #define SC_RIGHT (0x0c00 + 0x02A4) // Dword offset A9 155 #define SC_LEFT_RIGHT (0x0c00 + 0x02A8) // Dword offset AA 156 #define SC_TOP (0x0c00 + 0x02AC) // Dword offset AB 157 #define SC_BOTTOM (0x0c00 + 0x02B0) // Dword offset AC 158 #define SC_TOP_BOTTOM (0x0c00 + 0x02B4) // Dword offset AD 159 160 #define DP_BKGD_CLR (0x0c00 + 0x02C0) // Dword offset B0 161 #define DP_FRGD_CLR (0x0c00 + 0x02C4) // Dword offset B1 162 #define DP_WRITE_MASK (0x0c00 + 0x02C8) // Dword offset B2 163 #define DP_CHAIN_MASK (0x0c00 + 0x02CC) // Dword offset B3 164 #define DP_PIX_WIDTH (0x0c00 + 0x02D0) // Dword offset B4 165 #define DP_MIX (0x0c00 + 0x02D4) // Dword offset B5 166 #define DP_SRC (0x0c00 + 0x02D8) // Dword offset B6 167 168 #define CLR_CMP_CLR (0x0c00 + 0x0300) // Dword offset C0 169 #define CLR_CMP_MASK (0x0c00 + 0x0304) // Dword offset C1 170 #define CLR_CMP_CNTL (0x0c00 + 0x0308) // Dword offset C2 171 172 #define FIFO_STAT (0x0c00 + 0x0310) // Dword offset C4 173 174 #define CONTEXT_MASK (0x0c00 + 0x0320) // Dword offset C8 175 #define CONTEXT_LOAD_CNTL (0x0c00 + 0x032C) // Dword offset CB 176 177 #define GUI_TRAJ_CNTL (0x0c00 + 0x0330) // Dword offset CC 178 #define GUI_STAT (0x0c00 + 0x0338) // Dword offset CE 179 180 181 // CRTC control values. 182 183 #define CRTC_H_SYNC_NEG 0x00200000 184 #define CRTC_V_SYNC_NEG 0x00200000 185 186 #define CRTC_DBL_SCAN_EN 0x00000001 187 #define CRTC_INTERLACE_EN 0x00000002 188 #define CRTC_HSYNC_DIS 0x00000004 189 #define CRTC_VSYNC_DIS 0x00000008 190 #define CRTC_CSYNC_EN 0x00000010 191 #define CRTC_PIX_BY_2_EN 0x00000020 192 #define CRTC_DISPLAY_DIS 0x00000040 193 #define CRTC_VGA_XOVERSCAN 0x00000080 194 195 #define CRTC_PIX_WIDTH 0x00000700 196 #define CRTC_PIX_WIDTH_4BPP 0x00000100 197 #define CRTC_PIX_WIDTH_8BPP 0x00000200 198 #define CRTC_PIX_WIDTH_15BPP 0x00000300 199 #define CRTC_PIX_WIDTH_16BPP 0x00000400 200 #define CRTC_PIX_WIDTH_24BPP 0x00000500 201 #define CRTC_PIX_WIDTH_32BPP 0x00000600 202 203 #define CRTC_BYTE_PIX_ORDER 0x00000800 204 #define CRTC_PIX_ORDER_MSN_LSN 0x00000000 205 #define CRTC_PIX_ORDER_LSN_MSN 0x00000800 206 207 #define CRTC_FIFO_LWM 0x000f0000 208 #define CRTC2_PIX_WIDTH 0x000e0000 209 #define CRTC_VGA_128KAP_PAGING 0x00100000 210 #define CRTC_VFC_SYNC_TRISTATE 0x00200000 211 #define CRTC2_EN 0x00200000 212 #define CRTC_LOCK_REGS 0x00400000 213 #define CRTC_SYNC_TRISTATE 0x00800000 214 #define CRTC_EXT_DISP_EN 0x01000000 215 #define CRTC_EN 0x02000000 216 #define CRTC_DISP_REQ_EN 0x04000000 217 #define CRTC_VGA_LINEAR 0x08000000 218 #define CRTC_VGA_TEXT_132 0x20000000 219 #define CRTC_CNT_EN 0x40000000 220 #define CRTC_CUR_B_TEST 0x80000000 221 222 #define CRTC_CRNT_VLINE 0x07f00000 223 #define CRTC_VBLANK 0x00000001 224 225 #define CRTC_PITCH 0xffc00000 226 227 // DAC control values. 228 229 #define DAC_8BIT_EN 0x00000100 230 231 // Mix control values. 232 233 #define MIX_NOT_DST 0x0000 234 #define MIX_0 0x0001 235 #define MIX_1 0x0002 236 #define MIX_DST 0x0003 237 #define MIX_NOT_SRC 0x0004 238 #define MIX_XOR 0x0005 239 #define MIX_XNOR 0x0006 240 #define MIX_SRC 0x0007 241 #define MIX_NAND 0x0008 242 #define MIX_NOT_SRC_OR_DST 0x0009 243 #define MIX_SRC_OR_NOT_DST 0x000a 244 #define MIX_OR 0x000b 245 #define MIX_AND 0x000c 246 #define MIX_SRC_AND_NOT_DST 0x000d 247 #define MIX_NOT_SRC_AND_DST 0x000e 248 #define MIX_NOR 0x000f 249 250 // BUS_CNTL register constants. 251 #define BUS_FIFO_ERR_ACK 0x00200000 252 #define BUS_HOST_ERR_ACK 0x00800000 253 #define BUS_APER_REG_DIS 0x00000010 254 255 // GEN_TEST_CNTL register constants. 256 #define GEN_OVR_OUTPUT_EN 0x20 257 #define HWCURSOR_ENABLE 0x80 258 #define GUI_ENGINE_ENABLE 0x100 259 260 // DSP_CONFIG register constants. 261 #define DSP_XCLKS_PER_QW 0x00003fff 262 #define DSP_LOOP_LATENCY 0x000f0000 263 #define DSP_PRECISION 0x00700000 264 265 // DSP_ON_OFF register constants. 266 #define DSP_OFF 0x000007ff 267 #define DSP_ON 0x07ff0000 268 269 // CLOCK_CNTL register constants. 270 #define CLOCK_SEL 0x0f 271 #define CLOCK_DIV 0x30 272 #define CLOCK_DIV1 0x00 273 #define CLOCK_DIV2 0x10 274 #define CLOCK_DIV4 0x20 275 #define CLOCK_STROBE 0x40 276 #define PLL_WR_EN 0x02 277 #define PLL_ADDR 0xfc 278 279 // PLL registers. 280 #define PLL_MACRO_CNTL 0x01 281 #define PLL_REF_DIV 0x02 282 #define PLL_GEN_CNTL 0x03 283 #define PLL_MCLK_FB_DIV 0x04 284 #define PLL_VCLK_CNTL 0x05 285 #define PLL_VCLK_POST_DIV 0x06 286 #define PLL_VCLK0_FB_DIV 0x07 287 #define PLL_VCLK1_FB_DIV 0x08 288 #define PLL_VCLK2_FB_DIV 0x09 289 #define PLL_VCLK3_FB_DIV 0x0A 290 #define PLL_XCLK_CNTL 0x0B 291 #define PLL_TEST_CTRL 0x0E 292 #define PLL_TEST_COUNT 0x0F 293 294 // Fields in PLL registers. 295 #define PLL_PC_GAIN 0x07 296 #define PLL_VC_GAIN 0x18 297 #define PLL_DUTY_CYC 0xE0 298 #define PLL_MFB_TIMES_4_2B 0x08 299 #define PLL_VCLK0_XDIV 0x10 300 #define PLL_OVERRIDE 0x01 301 #define PLL_MCLK_RST 0x02 302 #define OSC_EN 0x04 303 #define EXT_CLK_EN 0x08 304 #define MCLK_SRC_SEL 0x70 305 #define EXT_CLK_CNTL 0x80 306 #define PLL_VCLK_SRC_SEL 0x03 307 #define PLL_VCLK_RESET 0x04 308 #define VCLK_INVERT 0x08 309 #define VCLK0_POST 0x03 310 #define VCLK1_POST 0x0C 311 #define VCLK2_POST 0x30 312 #define VCLK3_POST 0xC0 313 314 // MEM_CNTL register constants. 315 #define CTL_MEM_TRP 0x00000300 316 #define CTL_MEM_TRCD 0x00000C00 317 #define CTL_MEM_TCRD 0x00001000 318 #define CTL_MEM_TRAS 0x00070000 319 320 // DST_CNTL register constants. 321 #define DST_X_LEFT_TO_RIGHT 1 322 #define DST_Y_TOP_TO_BOTTOM 2 323 #define DST_LAST_PEL 0x20 324 325 // SRC_CNTL register constants. 326 #define SRC_LINE_X_LEFT_TO_RIGHT 0x10 327 328 // HOST_CNTL register constants. 329 #define HOST_BYTE_ALIGN 1 330 331 // DP_CHAIN_MASK register constants. 332 #define DP_CHAIN_4BPP 0x8888 333 #define DP_CHAIN_7BPP 0xD2D2 334 #define DP_CHAIN_8BPP 0x8080 335 #define DP_CHAIN_8BPP_RGB 0x9292 336 #define DP_CHAIN_15BPP 0x4210 337 #define DP_CHAIN_16BPP 0x8410 338 #define DP_CHAIN_24BPP 0x8080 339 #define DP_CHAIN_32BPP 0x8080 340 341 // DP_PIX_WIDTH register constants. 342 #define DST_1BPP 0 343 #define DST_4BPP 1 344 #define DST_8BPP 2 345 #define DST_15BPP 3 346 #define DST_16BPP 4 347 #define DST_32BPP 6 348 #define SRC_1BPP 0 349 #define SRC_4BPP 0x100 350 #define SRC_8BPP 0x200 351 #define SRC_15BPP 0x300 352 #define SRC_16BPP 0x400 353 #define SRC_32BPP 0x600 354 #define HOST_1BPP 0 355 #define HOST_4BPP 0x10000 356 #define HOST_8BPP 0x20000 357 #define HOST_15BPP 0x30000 358 #define HOST_16BPP 0x40000 359 #define HOST_32BPP 0x60000 360 #define BYTE_ORDER_MSB_TO_LSB 0 361 #define BYTE_ORDER_LSB_TO_MSB 0x1000000 362 363 // DP_SRC register constants. 364 #define BKGD_SRC_BKGD_CLR 0 365 #define FRGD_SRC_FRGD_CLR 0x100 366 #define FRGD_SRC_BLIT 0x300 367 #define MONO_SRC_ONE 0 368 369 // GUI_STAT register constants. 370 #define ENGINE_BUSY 1 371 372 // LCD Index register constants. 373 #define LCD_REG_INDEX 0x0000003F 374 #define LCD_DISPLAY_DIS 0x00000100 375 #define LCD_SRC_SEL 0x00000200 376 #define CRTC2_DISPLAY_DIS 0x00000400 377 378 // LCD register indices. 379 #define LCD_CONFIG_PANEL 0x00 380 #define LCD_GEN_CNTL 0x01 381 #define LCD_DSTN_CONTROL 0x02 382 #define LCD_HFB_PITCH_ADDR 0x03 383 #define LCD_HORZ_STRETCHING 0x04 384 #define LCD_VERT_STRETCHING 0x05 385 #define LCD_EXT_VERT_STRETCH 0x06 386 #define LCD_LT_GIO 0x07 387 #define LCD_POWER_MANAGEMENT 0x08 388 389 // LCD_CONFIG_PANEL register constants. 390 #define DONT_SHADOW_HEND 0x00004000 391 392 // LCD_GEN_CNTL register constants. 393 #define CRT_ON 0x00000001 394 #define LCD_ON 0x00000002 395 #define HORZ_DIVBY2_EN 0x00000004 396 #define LOCK_8DOT 0x00000010 397 #define DONT_SHADOW_VPAR 0x00000040 398 #define DIS_HOR_CRT_DIVBY2 0x00000400 399 #define MCLK_PM_EN 0x00010000 400 #define VCLK_DAC_PM_EN 0x00020000 401 #define CRTC_RW_SELECT 0x08000000 402 #define USE_SHADOWED_VEND 0x10000000 403 #define USE_SHADOWED_ROWCUR 0x20000000 404 #define SHADOW_EN 0x40000000 405 #define SHADOW_RW_EN 0x80000000 406 407 // LCD_HORZ_STRETCHING register constants. 408 #define HORZ_STRETCH_BLEND 0x00000fff 409 #define HORZ_STRETCH_RATIO 0x0000ffff 410 #define HORZ_STRETCH_LOOP 0x00070000 411 #define HORZ_PANEL_SIZE 0x0ff00000 412 #define AUTO_HORZ_RATIO 0x20000000 413 #define HORZ_STRETCH_MODE 0x40000000 414 #define HORZ_STRETCH_EN 0x80000000 415 416 // LCD_VERT_STRETCHING register constants. 417 #define VERT_STRETCH_RATIO0 0x000003ff 418 #define VERT_STRETCH_RATIO1 0x000ffc00 419 #define VERT_STRETCH_RATIO2 0x3ff00000 420 #define VERT_STRETCH_USE0 0x40000000 421 #define VERT_STRETCH_EN 0x80000000 422 423 // LCD_EXT_VERT_STRETCH register constants. 424 #define VERT_STRETCH_RATIO3 0x000003ff 425 #define FORCE_DAC_DATA 0x000000ff 426 #define FORCE_DAC_DATA_SEL 0x00000300 427 #define VERT_STRETCH_MODE 0x00000400 428 #define VERT_PANEL_SIZE 0x003ff800 429 #define AUTO_VERT_RATIO 0x00400000 430 #define USE_AUTO_FP_POS 0x00800000 431 #define USE_AUTO_LCD_VSYNC 0x01000000 432 433 // LCD_POWER_MANAGEMENT register constants. 434 #define AUTO_POWER_UP 0x00000008 435 #define POWER_BLON 0x02000000 436 #define STANDBY_NOW 0x10000000 437 #define SUSPEND_NOW 0x20000000 438 439 440 441 // Functions to get/set PLL registers. 442 //======================================= 443 444 static inline uint8 445 Mach64_GetPLLReg(uint8 index) 446 { 447 OUTREG8(CLOCK_CNTL + 1, (index << 2) & PLL_ADDR); 448 return INREG8(CLOCK_CNTL + 2); 449 } 450 451 452 static inline void 453 Mach64_SetPLLReg(uint8 index, uint8 value) 454 { 455 OUTREG8(CLOCK_CNTL + 1, ((index << 2) & PLL_ADDR) | PLL_WR_EN); 456 OUTREG8(CLOCK_CNTL + 2, value); 457 } 458 459 460 static inline uint32 461 Mach64_GetLCDReg(int index) 462 { 463 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX); 464 return INREG(LCD_DATA); 465 } 466 467 468 static inline void 469 Mach64_PutLCDReg(int index, uint32 value) 470 { 471 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX); 472 OUTREG(LCD_DATA, value); 473 } 474 475 476 #endif // __MACH64_H__ 477