1b3d94504SStephan Aßmus /* 2b3d94504SStephan Aßmus * This file is a part of BeOS USBVision driver project. 3b3d94504SStephan Aßmus * Copyright (c) 2003 by Siarzuk Zharski <imker@gmx.li> 4b3d94504SStephan Aßmus * 5b3d94504SStephan Aßmus * This file may be used under the terms of the BSD License 6b3d94504SStephan Aßmus * Look into the file "License" for details. 7b3d94504SStephan Aßmus * 8b3d94504SStephan Aßmus * Skeletal part of this code was inherired from original BeOS sample code, 9b3d94504SStephan Aßmus * that is distributed under the terms of the Be Sample Code License. 10b3d94504SStephan Aßmus * Look into the file "Be License" for details. 11b3d94504SStephan Aßmus * 12b3d94504SStephan Aßmus * $Source: /cvsroot/sis4be/usbvision/include/nt100x.h,v $ 13b3d94504SStephan Aßmus * $Author: zharik $ 14b3d94504SStephan Aßmus * $Revision: 1.1 $ 15b3d94504SStephan Aßmus * $Date: 2003/07/15 18:58:05 $ 16b3d94504SStephan Aßmus * 17b3d94504SStephan Aßmus */ 18b3d94504SStephan Aßmus 19b3d94504SStephan Aßmus #ifndef _NT100X_H_ 20b3d94504SStephan Aßmus #define _NT100X_H_ 21b3d94504SStephan Aßmus 22b3d94504SStephan Aßmus #define READ_CMD_PREFIX 0x33C2 23b3d94504SStephan Aßmus #define WRITE_CMD_PREFIX 0x3342 24b3d94504SStephan Aßmus 25b3d94504SStephan Aßmus #define COMMAND_DATA_LENGTH 0x08 26b3d94504SStephan Aßmus typedef struct{ 27b3d94504SStephan Aßmus uint8 reg; 28b3d94504SStephan Aßmus uint8 data_length; 29b3d94504SStephan Aßmus uint8 data[COMMAND_DATA_LENGTH]; 30b3d94504SStephan Aßmus }xet_nt100x_reg; 31b3d94504SStephan Aßmus 32b3d94504SStephan Aßmus #define NT_IOCTL_READ_REGISTER B_DEVICE_OP_CODES_END + 1 33b3d94504SStephan Aßmus #define NT_IOCTL_WRITE_REGISTER B_DEVICE_OP_CODES_END + 2 34b3d94504SStephan Aßmus 35b3d94504SStephan Aßmus /*General Control Registers (Power, Restart EP, USB, IOpins, Camera Control)*/ 36b3d94504SStephan Aßmus #define PWR_REG 0x00 /*0*/ 37b3d94504SStephan Aßmus #define CONFIG_REG 0x01 /*1*/ 38b3d94504SStephan Aßmus #define ADRS_REG 0x02 /*2*/ 39b3d94504SStephan Aßmus #define ALTER_REG 0x03 /*3*/ 40b3d94504SStephan Aßmus #define FORCE_ALTER_REG 0x04 /*4*/ 41b3d94504SStephan Aßmus #define STATUS_REG 0x05 /*5*/ 42b3d94504SStephan Aßmus #define IOPIN_REG 0x06 /*6*/ 43b3d94504SStephan Aßmus #define SER_MODE 0x07 /*7*/ 44b3d94504SStephan Aßmus #define SER_ADRS 0x08 /*8*/ 45b3d94504SStephan Aßmus #define SER_CONT 0x09 /*9*/ 46b3d94504SStephan Aßmus #define SER_DAT1 0x0a /*10*/ 47b3d94504SStephan Aßmus #define SER_DAT2 0x0b /*11*/ 48b3d94504SStephan Aßmus #define SER_DAT3 0x0c /*12*/ 49b3d94504SStephan Aßmus #define SER_DAT4 0x0d /*13*/ 50b3d94504SStephan Aßmus 51b3d94504SStephan Aßmus /*EEPROM Read/Write Registers*/ 52b3d94504SStephan Aßmus #define EE_DATA 0x0e /*14*/ 53b3d94504SStephan Aßmus #define EE_LSBAD 0x0f /*15*/ 54b3d94504SStephan Aßmus #define EE_CONT 0x10 /*16*/ 55b3d94504SStephan Aßmus 56b3d94504SStephan Aßmus /*17: 0x11*/ 57b3d94504SStephan Aßmus 58b3d94504SStephan Aßmus /*DRAM and Memory Buffers Setup Registers*/ 59b3d94504SStephan Aßmus #define DRM_CONT 0x12 /*18*/ 60b3d94504SStephan Aßmus #define DRM_PRM1 0x13 /*19*/ 61b3d94504SStephan Aßmus #define DRM_PRM2 0x14 /*20*/ 62b3d94504SStephan Aßmus #define DRM_PRM3 0x15 /*21*/ 63b3d94504SStephan Aßmus #define DRM_PRM4 0x16 /*22*/ 64b3d94504SStephan Aßmus #define DRM_PRM5 0x17 /*23*/ 65b3d94504SStephan Aßmus #define DRM_PRM6 0x18 /*24*/ 66b3d94504SStephan Aßmus #define DRM_PRM7 0x19 /*25*/ 67b3d94504SStephan Aßmus #define DRM_PRM8 0x1a /*26*/ 68b3d94504SStephan Aßmus 69b3d94504SStephan Aßmus /*Video Setup and Control Registers*/ 70b3d94504SStephan Aßmus #define VIN_REG1 0x1b /*27*/ 71b3d94504SStephan Aßmus #define VIN_REG2 0x1c /*28*/ 72b3d94504SStephan Aßmus #define LXSIZE_IN 0x1d /*29*/ 73b3d94504SStephan Aßmus #define MXSIZE_IN 0x1e /*30*/ 74b3d94504SStephan Aßmus #define LYSIZE_IN 0x1f /*31*/ 75b3d94504SStephan Aßmus #define MYSIZE_IN 0x20 /*32*/ 76b3d94504SStephan Aßmus #define LX_OFFST 0x21 /*33*/ 77b3d94504SStephan Aßmus #define MX_OFFST 0x22 /*34*/ 78b3d94504SStephan Aßmus #define LY_OFFST 0x23 /*35*/ 79b3d94504SStephan Aßmus #define MY_OFFST 0x24 /*36*/ 80b3d94504SStephan Aßmus #define FRM_RATE 0x25 /*37*/ 81b3d94504SStephan Aßmus #define LXSIZE_O 0x26 /*38*/ 82b3d94504SStephan Aßmus #define MXSIZE_O 0x27 /*39*/ 83b3d94504SStephan Aßmus #define LYSIZE_O 0x28 /*40*/ 84b3d94504SStephan Aßmus #define MYSIZE_O 0x29 /*41*/ 85b3d94504SStephan Aßmus #define FILT_CONT 0x2a /*42*/ 86b3d94504SStephan Aßmus #define VO_MODE 0x2b /*43*/ 87b3d94504SStephan Aßmus #define INTRA_CYC 0x2c /*44*/ 88b3d94504SStephan Aßmus #define STRIP_SZ 0x2d /*45*/ 89b3d94504SStephan Aßmus #define FORCE_INTRA 0x2e /*46*/ 90b3d94504SStephan Aßmus #define FORCE_UP 0x2f /*47*/ 91b3d94504SStephan Aßmus #define BUF_THR 0x30 /*48*/ 92b3d94504SStephan Aßmus #define DVI_YUV 0x31 /*49*/ 93b3d94504SStephan Aßmus #define AUDIO_CONT 0x32 /*50*/ 94b3d94504SStephan Aßmus #define AUD_PK_LEN 0x33 /*51*/ 95b3d94504SStephan Aßmus #define BLK_PK_LEN 0x34 /*52*/ 96b3d94504SStephan Aßmus 97*d25dd4b9SJérôme Duval /*USB WatchDog Register*/ 98b3d94504SStephan Aßmus #define WD_COUNT 0x35 /*53*/ 99b3d94504SStephan Aßmus 100b3d94504SStephan Aßmus /*54 0x36*/ 101b3d94504SStephan Aßmus /*55 0x37*/ 102b3d94504SStephan Aßmus 103b3d94504SStephan Aßmus /*Compression Ratio Management Registers*/ 104b3d94504SStephan Aßmus #define PCM_THR1 0x38 /*56*/ 105b3d94504SStephan Aßmus #define PCM_THR2 0x39 /*57*/ 106b3d94504SStephan Aßmus #define DIST_THR_I 0x3a /*58*/ 107b3d94504SStephan Aßmus #define DIST_THR_A 0x3b /*59*/ 108b3d94504SStephan Aßmus #define MAX_DIST_I 0x3c /*60*/ 109b3d94504SStephan Aßmus #define MAX_DIST_A 0x3d /*61*/ 110b3d94504SStephan Aßmus #define VID_BUF_ 0x3e /*62*/ 111b3d94504SStephan Aßmus #define LFP_LSB 0x3f /*63*/ 112b3d94504SStephan Aßmus #define LFP_MSB 0x40 /*64*/ 113b3d94504SStephan Aßmus #define VID_LPF 0x41 /*65*/ 114b3d94504SStephan Aßmus 115b3d94504SStephan Aßmus #endif //_NT100X_H_ 116