1 /* 2 * Copyright 2022, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Copyright 2010, Ingo Weinhold, ingo_weinhold@gmx.de. 6 * Distributed under the terms of the MIT License. 7 */ 8 #ifndef _SYSTEM_ARCH_ARM_DEFS_H 9 #define _SYSTEM_ARCH_ARM_DEFS_H 10 11 12 #define SPINLOCK_PAUSE() do {} while (false) 13 14 #define CPSR_MODE_MASK 0x1f 15 #define CPSR_MODE_USR 0x10 16 #define CPSR_MODE_FIQ 0x11 17 #define CPSR_MODE_IRQ 0x12 18 #define CPSR_MODE_SVC 0x13 19 #define CPSR_MODE_ABT 0x17 20 #define CPSR_MODE_UND 0x1b 21 #define CPSR_MODE_SYS 0x1f 22 23 #define CPSR_T 0x20 24 #define CPSR_F 0x40 25 #define CPSR_I 0x80 26 27 #define SCTLR_HIGH_VECTORS 0x00002000 28 29 #define FSR_WNR 0x800 30 #define FSR_LPAE 0x200 31 32 #define FSR_FS_ALIGNMENT_FAULT 0x01 33 #define FSR_FS_ACCESS_FLAG_FAULT 0x06 34 #define FSR_FS_PERMISSION_FAULT_L1 0x0d 35 #define FSR_FS_PERMISSION_FAULT_L2 0x0f 36 37 #define FSR_FS_MASK 0x040f 38 #define FSR_LPAE_MASK 0x0200 39 40 #endif /* _SYSTEM_ARCH_ARM_DEFS_H */ 41