1 /* 2 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 3 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 4 * Distributed under the terms of the MIT License. 5 * 6 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 7 * Distributed under the terms of the NewOS License. 8 */ 9 #ifndef _KERNEL_ARCH_x86_CPU_H 10 #define _KERNEL_ARCH_x86_CPU_H 11 12 13 #ifndef _ASSEMBLER 14 15 #include <module.h> 16 17 #include <arch_thread_types.h> 18 19 #include <arch/x86/descriptors.h> 20 21 #ifdef __x86_64__ 22 # include <arch/x86/64/cpu.h> 23 #endif 24 25 #endif // !_ASSEMBLER 26 27 28 #define CPU_MAX_CACHE_LEVEL 8 29 30 #define CACHE_LINE_SIZE 64 31 32 33 // MSR registers (possibly Intel specific) 34 #define IA32_MSR_TSC 0x10 35 #define IA32_MSR_APIC_BASE 0x1b 36 37 #define IA32_MSR_PLATFORM_INFO 0xce 38 #define IA32_MSR_MPERF 0xe7 39 #define IA32_MSR_APERF 0xe8 40 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 41 #define IA32_MSR_SYSENTER_CS 0x174 42 #define IA32_MSR_SYSENTER_ESP 0x175 43 #define IA32_MSR_SYSENTER_EIP 0x176 44 #define IA32_MSR_PERF_STATUS 0x198 45 #define IA32_MSR_PERF_CTL 0x199 46 #define IA32_MSR_TURBO_RATIO_LIMIT 0x1ad 47 #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 48 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 49 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 50 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 51 52 #define IA32_MSR_EFER 0xc0000080 53 54 55 // MSR APIC BASE bits 56 #define IA32_MSR_APIC_BASE_BSP 0x00000100 57 #define IA32_MSR_APIC_BASE_X2APIC 0x00000400 58 #define IA32_MSR_APIC_BASE_ENABLED 0x00000800 59 #define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000 60 61 // MSR EFER bits 62 // reference 63 #define IA32_MSR_EFER_SYSCALL (1 << 0) 64 #define IA32_MSR_EFER_NX (1 << 11) 65 66 // X2APIC MSRs. 67 #define IA32_MSR_APIC_ID 0x00000802 68 #define IA32_MSR_APIC_VERSION 0x00000803 69 #define IA32_MSR_APIC_TASK_PRIORITY 0x00000808 70 #define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a 71 #define IA32_MSR_APIC_EOI 0x0000080b 72 #define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d 73 #define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f 74 #define IA32_MSR_APIC_ERROR_STATUS 0x00000828 75 #define IA32_MSR_APIC_INTR_COMMAND 0x00000830 76 #define IA32_MSR_APIC_LVT_TIMER 0x00000832 77 #define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833 78 #define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834 79 #define IA32_MSR_APIC_LVT_LINT0 0x00000835 80 #define IA32_MSR_APIC_LVT_LINT1 0x00000836 81 #define IA32_MSR_APIC_LVT_ERROR 0x00000837 82 #define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838 83 #define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839 84 #define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e 85 86 // x86_64 MSRs. 87 #define IA32_MSR_STAR 0xc0000081 88 #define IA32_MSR_LSTAR 0xc0000082 89 #define IA32_MSR_FMASK 0xc0000084 90 #define IA32_MSR_FS_BASE 0xc0000100 91 #define IA32_MSR_GS_BASE 0xc0000101 92 #define IA32_MSR_KERNEL_GS_BASE 0xc0000102 93 94 // K8 MSR registers 95 #define K8_MSR_IPM 0xc0010055 96 97 // x86 features from cpuid eax 1, edx register 98 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5) 99 #define IA32_FEATURE_FPU (1 << 0) // x87 fpu 100 #define IA32_FEATURE_VME (1 << 1) // virtual 8086 101 #define IA32_FEATURE_DE (1 << 2) // debugging extensions 102 #define IA32_FEATURE_PSE (1 << 3) // page size extensions 103 #define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction 104 #define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction 105 #define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing 106 #define IA32_FEATURE_MCE (1 << 7) // machine check exception 107 #define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction 108 #define IA32_FEATURE_APIC (1 << 9) // local apic on chip 109 // (1 << 10) // Reserved 110 #define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT 111 #define IA32_FEATURE_MTRR (1 << 12) // MTRR 112 #define IA32_FEATURE_PGE (1 << 13) // paging global bit 113 #define IA32_FEATURE_MCA (1 << 14) // machine check architecture 114 #define IA32_FEATURE_CMOV (1 << 15) // cmov instruction 115 #define IA32_FEATURE_PAT (1 << 16) // page attribute table 116 #define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages 117 #define IA32_FEATURE_PSN (1 << 18) // processor serial number 118 #define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction 119 // (1 << 20) // Reserved 120 #define IA32_FEATURE_DS (1 << 21) // debug store 121 #define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl 122 #define IA32_FEATURE_MMX (1 << 23) // mmx instructions 123 #define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction 124 #define IA32_FEATURE_SSE (1 << 25) // SSE 125 #define IA32_FEATURE_SSE2 (1 << 26) // SSE2 126 #define IA32_FEATURE_SS (1 << 27) // self snoop 127 #define IA32_FEATURE_HTT (1 << 28) // hyperthreading 128 #define IA32_FEATURE_TM (1 << 29) // thermal monitor 129 #define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86 130 #define IA32_FEATURE_PBE (1 << 31) // pending break enable 131 132 // x86 features from cpuid eax 1, ecx register 133 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4) 134 #define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3 135 #define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction 136 #define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store 137 #define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT 138 #define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store 139 #define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions 140 #define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions 141 #define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep 142 #define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2 143 #define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3 144 #define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID 145 // (1 << 11) // Reserved 146 #define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add 147 #define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B 148 #define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control 149 #define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability 150 // (1 << 16) // Reserved 151 #define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers 152 #define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access 153 #define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1 154 #define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2 155 #define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support 156 #define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction 157 #define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction 158 #define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline 159 #define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions 160 #define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States 161 #define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE 162 #define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions 163 #define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion 164 #define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction 165 #define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor 166 167 // x86 features from cpuid eax 0x80000001, ecx register (AMD) 168 #define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode 169 #define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions 170 171 // x86 features from cpuid eax 0x80000001, edx register (AMD) 172 // only care about the ones that are unique to this register 173 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 174 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 175 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 176 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 177 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 178 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 179 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 180 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 181 182 // some of the features from cpuid eax 0x80000001, edx register (AMD) are also 183 // available on Intel processors 184 #define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \ 185 | IA32_FEATURE_AMD_EXT_NX \ 186 | IA32_FEATURE_AMD_EXT_RDTSCP \ 187 | IA32_FEATURE_AMD_EXT_LONG) 188 189 // x86 defined features from cpuid eax 5, ecx register 190 #define IA32_FEATURE_POWER_MWAIT (1 << 0) 191 #define IA32_FEATURE_INTERRUPT_MWAIT (1 << 1) 192 193 // x86 defined features from cpuid eax 6, eax register 194 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 195 #define IA32_FEATURE_DTS (1 << 0) //Digital Thermal Sensor 196 #define IA32_FEATURE_ITB (1 << 1) //Intel Turbo Boost Technology 197 #define IA32_FEATURE_ARAT (1 << 2) //Always running APIC Timer 198 #define IA32_FEATURE_PLN (1 << 4) //Power Limit Notification 199 #define IA32_FEATURE_ECMD (1 << 5) //Extended Clock Modulation Duty 200 #define IA32_FEATURE_PTM (1 << 6) //Package Thermal Management 201 202 // x86 defined features from cpuid eax 6, ecx register 203 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 204 #define IA32_FEATURE_APERFMPERF (1 << 0) //IA32_APERF, IA32_MPERF 205 #define IA32_FEATURE_EPB (1 << 3) //IA32_ENERGY_PERF_BIAS 206 207 // x86 defined features from cpuid eax 0x80000007, edx register 208 #define IA32_FEATURE_INVARIANT_TSC (1 << 8) 209 210 // cr4 flags 211 #define IA32_CR4_PAE (1UL << 5) 212 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 213 214 // Memory type ranges 215 #define IA32_MTR_UNCACHED 0 216 #define IA32_MTR_WRITE_COMBINING 1 217 #define IA32_MTR_WRITE_THROUGH 4 218 #define IA32_MTR_WRITE_PROTECTED 5 219 #define IA32_MTR_WRITE_BACK 6 220 221 // EFLAGS register 222 #define X86_EFLAGS_CARRY 0x00000001 223 #define X86_EFLAGS_RESERVED1 0x00000002 224 #define X86_EFLAGS_PARITY 0x00000004 225 #define X86_EFLAGS_AUXILIARY_CARRY 0x00000010 226 #define X86_EFLAGS_ZERO 0x00000040 227 #define X86_EFLAGS_SIGN 0x00000080 228 #define X86_EFLAGS_TRAP 0x00000100 229 #define X86_EFLAGS_INTERRUPT 0x00000200 230 #define X86_EFLAGS_DIRECTION 0x00000400 231 #define X86_EFLAGS_OVERFLOW 0x00000800 232 #define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000 233 #define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12 234 #define X86_EFLAGS_NESTED_TASK 0x00004000 235 #define X86_EFLAGS_RESUME 0x00010000 236 #define X86_EFLAGS_V86_MODE 0x00020000 237 #define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000 238 #define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000 239 #define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000 240 #define X86_EFLAGS_ID 0x00200000 241 242 #define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \ 243 | X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \ 244 | X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW) 245 246 #define CR0_CACHE_DISABLE (1UL << 30) 247 #define CR0_NOT_WRITE_THROUGH (1UL << 29) 248 #define CR0_FPU_EMULATION (1UL << 2) 249 #define CR0_MONITOR_FPU (1UL << 1) 250 251 #define CR4_OS_FXSR (1UL << 9) 252 #define CR4_OS_XMM_EXCEPTION (1UL << 10) 253 254 255 // iframe types 256 #define IFRAME_TYPE_SYSCALL 0x1 257 #define IFRAME_TYPE_OTHER 0x2 258 #define IFRAME_TYPE_MASK 0xf 259 260 261 #ifndef _ASSEMBLER 262 263 264 struct X86PagingStructures; 265 266 267 typedef struct x86_mtrr_info { 268 uint64 base; 269 uint64 size; 270 uint8 type; 271 } x86_mtrr_info; 272 273 typedef struct x86_cpu_module_info { 274 module_info info; 275 uint32 (*count_mtrrs)(void); 276 void (*init_mtrrs)(void); 277 278 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 279 uint8 type); 280 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 281 uint8* _type); 282 void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos, 283 uint32 count); 284 } x86_cpu_module_info; 285 286 // features 287 enum x86_feature_type { 288 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 289 FEATURE_EXT, // cpuid eax=1, edx register 290 FEATURE_EXT_AMD_ECX, // cpuid eax=0x80000001, ecx register (AMD) 291 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 292 FEATURE_5_ECX, // cpuid eax=5, ecx register 293 FEATURE_6_EAX, // cpuid eax=6, eax registers 294 FEATURE_6_ECX, // cpuid eax=6, ecx registers 295 FEATURE_EXT_7_EDX, // cpuid eax=0x80000007, edx register 296 297 FEATURE_NUM 298 }; 299 300 enum x86_vendors { 301 VENDOR_INTEL = 0, 302 VENDOR_AMD, 303 VENDOR_CYRIX, 304 VENDOR_UMC, 305 VENDOR_NEXGEN, 306 VENDOR_CENTAUR, 307 VENDOR_RISE, 308 VENDOR_TRANSMETA, 309 VENDOR_NSC, 310 311 VENDOR_NUM, 312 VENDOR_UNKNOWN, 313 }; 314 315 316 typedef struct arch_cpu_info { 317 // saved cpu info 318 enum x86_vendors vendor; 319 uint32 feature[FEATURE_NUM]; 320 char model_name[49]; 321 const char* vendor_name; 322 int type; 323 int family; 324 int extended_family; 325 int stepping; 326 int model; 327 int extended_model; 328 329 uint32 logical_apic_id; 330 331 struct X86PagingStructures* active_paging_structures; 332 333 size_t dr6; // temporary storage for debug registers (cf. 334 size_t dr7; // x86_exit_user_debug_at_kernel_entry()) 335 336 // local TSS for this cpu 337 struct tss tss; 338 #ifndef __x86_64__ 339 struct tss double_fault_tss; 340 void* kernel_tls; 341 #endif 342 } arch_cpu_info; 343 344 345 #define nop() __asm__ ("nop"::) 346 347 #define x86_read_cr0() ({ \ 348 size_t _v; \ 349 __asm__("mov %%cr0,%0" : "=r" (_v)); \ 350 _v; \ 351 }) 352 353 #define x86_write_cr0(value) \ 354 __asm__("mov %0,%%cr0" : : "r" (value)) 355 356 #define x86_read_cr2() ({ \ 357 size_t _v; \ 358 __asm__("mov %%cr2,%0" : "=r" (_v)); \ 359 _v; \ 360 }) 361 362 #define x86_read_cr3() ({ \ 363 size_t _v; \ 364 __asm__("mov %%cr3,%0" : "=r" (_v)); \ 365 _v; \ 366 }) 367 368 #define x86_write_cr3(value) \ 369 __asm__("mov %0,%%cr3" : : "r" (value)) 370 371 #define x86_read_cr4() ({ \ 372 size_t _v; \ 373 __asm__("mov %%cr4,%0" : "=r" (_v)); \ 374 _v; \ 375 }) 376 377 #define x86_write_cr4(value) \ 378 __asm__("mov %0,%%cr4" : : "r" (value)) 379 380 #define x86_read_dr3() ({ \ 381 size_t _v; \ 382 __asm__("mov %%dr3,%0" : "=r" (_v)); \ 383 _v; \ 384 }) 385 386 #define x86_write_dr3(value) \ 387 __asm__("mov %0,%%dr3" : : "r" (value)) 388 389 #define invalidate_TLB(va) \ 390 __asm__("invlpg (%0)" : : "r" (va)) 391 392 #define wbinvd() \ 393 __asm__("wbinvd") 394 395 #define out8(value,port) \ 396 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 397 398 #define out16(value,port) \ 399 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 400 401 #define out32(value,port) \ 402 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 403 404 #define in8(port) ({ \ 405 uint8 _v; \ 406 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 407 _v; \ 408 }) 409 410 #define in16(port) ({ \ 411 uint16 _v; \ 412 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 413 _v; \ 414 }) 415 416 #define in32(port) ({ \ 417 uint32 _v; \ 418 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 419 _v; \ 420 }) 421 422 #define out8_p(value,port) \ 423 __asm__ ("outb %%al,%%dx\n" \ 424 "\tjmp 1f\n" \ 425 "1:\tjmp 1f\n" \ 426 "1:" : : "a" (value), "d" (port)) 427 428 #define in8_p(port) ({ \ 429 uint8 _v; \ 430 __asm__ volatile ("inb %%dx,%%al\n" \ 431 "\tjmp 1f\n" \ 432 "1:\tjmp 1f\n" \ 433 "1:" : "=a" (_v) : "d" (port)); \ 434 _v; \ 435 }) 436 437 438 extern void (*gCpuIdleFunc)(void); 439 440 441 #ifdef __cplusplus 442 extern "C" { 443 #endif 444 445 struct arch_thread; 446 447 #ifdef __x86_64__ 448 void __x86_setup_system_time(uint64 conversionFactor, 449 uint64 conversionFactorNsecs); 450 #else 451 void __x86_setup_system_time(uint32 conversionFactor, 452 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 453 #endif 454 455 void x86_userspace_thread_exit(void); 456 void x86_end_userspace_thread_exit(void); 457 458 addr_t x86_get_stack_frame(); 459 uint32 x86_count_mtrrs(void); 460 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 461 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 462 uint8* _type); 463 void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, 464 uint32 count); 465 void x86_init_fpu(); 466 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 467 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 468 int32 x86_double_fault_get_cpu(void); 469 470 void x86_invalid_exception(iframe* frame); 471 void x86_fatal_exception(iframe* frame); 472 void x86_unexpected_exception(iframe* frame); 473 void x86_hardware_interrupt(iframe* frame); 474 void x86_page_fault_exception(iframe* iframe); 475 476 #ifndef __x86_64__ 477 478 void x86_swap_pgdir(addr_t newPageDir); 479 480 uint64 x86_read_msr(uint32 registerNumber); 481 void x86_write_msr(uint32 registerNumber, uint64 value); 482 483 void x86_context_switch(struct arch_thread* oldState, 484 struct arch_thread* newState); 485 486 void x86_fnsave(void* fpuState); 487 void x86_frstor(const void* fpuState); 488 489 void x86_fxsave(void* fpuState); 490 void x86_fxrstor(const void* fpuState); 491 492 void x86_noop_swap(void* oldFpuState, const void* newFpuState); 493 void x86_fnsave_swap(void* oldFpuState, const void* newFpuState); 494 void x86_fxsave_swap(void* oldFpuState, const void* newFpuState); 495 496 #endif 497 498 499 static inline void 500 arch_cpu_idle(void) 501 { 502 gCpuIdleFunc(); 503 } 504 505 506 static inline void 507 arch_cpu_pause(void) 508 { 509 asm volatile("pause" : : : "memory"); 510 } 511 512 513 #ifdef __cplusplus 514 } // extern "C" { 515 #endif 516 517 #endif // !_ASSEMBLER 518 519 #endif /* _KERNEL_ARCH_x86_CPU_H */ 520