1 /* 2 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 3 * Distributed under the terms of the MIT License. 4 * 5 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 6 * Distributed under the terms of the NewOS License. 7 */ 8 #ifndef _KERNEL_ARCH_x86_CPU_H 9 #define _KERNEL_ARCH_x86_CPU_H 10 11 12 #ifndef _ASSEMBLER 13 14 #include <module.h> 15 #include <arch/x86/descriptors.h> 16 17 #endif // !_ASSEMBLER 18 19 20 #undef PAUSE 21 #define PAUSE() asm volatile ("pause;") 22 23 24 // MSR registers (possibly Intel specific) 25 #define IA32_MSR_TSC 0x10 26 #define IA32_MSR_APIC_BASE 0x1b 27 28 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 29 #define IA32_MSR_SYSENTER_CS 0x174 30 #define IA32_MSR_SYSENTER_ESP 0x175 31 #define IA32_MSR_SYSENTER_EIP 0x176 32 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 33 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 34 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 35 36 // x86 features from cpuid eax 1, edx register 37 #define IA32_FEATURE_FPU 0x00000001 // x87 fpu 38 #define IA32_FEATURE_VME 0x00000002 // virtual 8086 39 #define IA32_FEATURE_DE 0x00000004 // debugging extensions 40 #define IA32_FEATURE_PSE 0x00000008 // page size extensions 41 #define IA32_FEATURE_TSC 0x00000010 // rdtsc instruction 42 #define IA32_FEATURE_MSR 0x00000020 // rdmsr/wrmsr instruction 43 #define IA32_FEATURE_PAE 0x00000040 // extended 3 level page table addressing 44 #define IA32_FEATURE_MCE 0x00000080 // machine check exception 45 #define IA32_FEATURE_CX8 0x00000100 // cmpxchg8b instruction 46 #define IA32_FEATURE_APIC 0x00000200 // local apic on chip 47 #define IA32_FEATURE_SEP 0x00000800 // SYSENTER/SYSEXIT 48 #define IA32_FEATURE_MTRR 0x00001000 // MTRR 49 #define IA32_FEATURE_PGE 0x00002000 // paging global bit 50 #define IA32_FEATURE_MCA 0x00004000 // machine check architecture 51 #define IA32_FEATURE_CMOV 0x00008000 // cmov instruction 52 #define IA32_FEATURE_PAT 0x00010000 // page attribute table 53 #define IA32_FEATURE_PSE36 0x00020000 // page size extensions with 4MB pages 54 #define IA32_FEATURE_PSN 0x00040000 // processor serial number 55 #define IA32_FEATURE_CLFSH 0x00080000 // cflush instruction 56 #define IA32_FEATURE_DS 0x00200000 // debug store 57 #define IA32_FEATURE_ACPI 0x00400000 // thermal monitor and clock ctrl 58 #define IA32_FEATURE_MMX 0x00800000 // mmx instructions 59 #define IA32_FEATURE_FXSR 0x01000000 // FXSAVE/FXRSTOR instruction 60 #define IA32_FEATURE_SSE 0x02000000 // SSE 61 #define IA32_FEATURE_SSE2 0x04000000 // SSE2 62 #define IA32_FEATURE_SS 0x08000000 // self snoop 63 #define IA32_FEATURE_HTT 0x10000000 // hyperthreading 64 #define IA32_FEATURE_TM 0x20000000 // thermal monitor 65 #define IA32_FEATURE_PBE 0x80000000 // pending break enable 66 67 // x86 features from cpuid eax 1, ecx register 68 #define IA32_FEATURE_EXT_SSE3 0x00000001 // SSE3 69 #define IA32_FEATURE_EXT_MONITOR 0x00000008 // MONITOR/MWAIT 70 #define IA32_FEATURE_EXT_DSCPL 0x00000010 // CPL qualified debug store 71 #define IA32_FEATURE_EXT_EST 0x00000080 // speedstep 72 #define IA32_FEATURE_EXT_TM2 0x00000100 // thermal monitor 2 73 #define IA32_FEATURE_EXT_CNXTID 0x00000400 // L1 context ID 74 75 // x86 features from cpuid eax 0x80000001, edx register (AMD) 76 // only care about the ones that are unique to this register 77 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 78 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 79 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 80 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 81 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 82 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 83 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 84 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 85 86 // cr4 flags 87 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 88 89 // Memory type ranges 90 #define IA32_MTR_UNCACHED 0 91 #define IA32_MTR_WRITE_COMBINING 1 92 #define IA32_MTR_WRITE_THROUGH 4 93 #define IA32_MTR_WRITE_PROTECTED 5 94 #define IA32_MTR_WRITE_BACK 6 95 96 97 // iframe types 98 #define IFRAME_TYPE_SYSCALL 0x1 99 #define IFRAME_TYPE_OTHER 0x2 100 #define IFRAME_TYPE_MASK 0xf 101 102 103 #ifndef _ASSEMBLER 104 105 typedef struct x86_optimized_functions { 106 void (*memcpy)(void* dest, const void* source, size_t count); 107 void* memcpy_end; 108 void (*memset)(void* dest, int value, size_t count); 109 void* memset_end; 110 } x86_optimized_functions; 111 112 typedef struct x86_cpu_module_info { 113 module_info info; 114 uint32 (*count_mtrrs)(void); 115 void (*init_mtrrs)(void); 116 117 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 118 uint8 type); 119 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 120 uint8* _type); 121 122 void (*get_optimized_functions)(x86_optimized_functions* functions); 123 } x86_cpu_module_info; 124 125 126 struct tss { 127 uint16 prev_task; 128 uint16 unused0; 129 uint32 sp0; 130 uint32 ss0; 131 uint32 sp1; 132 uint32 ss1; 133 uint32 sp2; 134 uint32 ss2; 135 uint32 cr3; 136 uint32 eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi; 137 uint32 es, cs, ss, ds, fs, gs; 138 uint32 ldt_seg_selector; 139 uint16 unused1; 140 uint16 io_map_base; 141 }; 142 143 struct iframe { 144 uint32 type; // iframe type 145 uint32 gs; 146 uint32 fs; 147 uint32 es; 148 uint32 ds; 149 uint32 edi; 150 uint32 esi; 151 uint32 ebp; 152 uint32 esp; 153 uint32 ebx; 154 uint32 edx; 155 uint32 ecx; 156 uint32 eax; 157 uint32 orig_eax; 158 uint32 orig_edx; 159 uint32 vector; 160 uint32 error_code; 161 uint32 eip; 162 uint32 cs; 163 uint32 flags; 164 165 // user_esp and user_ss are only present when the iframe is a userland 166 // iframe (IFRAME_IS_USER()). A kernel iframe is shorter. 167 uint32 user_esp; 168 uint32 user_ss; 169 }; 170 171 struct vm86_iframe { 172 uint32 type; // iframe type 173 uint32 __null_gs; 174 uint32 __null_fs; 175 uint32 __null_es; 176 uint32 __null_ds; 177 uint32 edi; 178 uint32 esi; 179 uint32 ebp; 180 uint32 __kern_esp; 181 uint32 ebx; 182 uint32 edx; 183 uint32 ecx; 184 uint32 eax; 185 uint32 orig_eax; 186 uint32 orig_edx; 187 uint32 vector; 188 uint32 error_code; 189 uint32 eip; 190 uint16 cs, __csh; 191 uint32 flags; 192 uint32 esp; 193 uint16 ss, __ssh; 194 195 /* vm86 mode specific part */ 196 uint16 es, __esh; 197 uint16 ds, __dsh; 198 uint16 fs, __fsh; 199 uint16 gs, __gsh; 200 }; 201 202 #define IFRAME_IS_USER(f) ((f)->cs == USER_CODE_SEG \ 203 || ((f)->flags & 0x20000) != 0) 204 #define IFRAME_IS_VM86(f) (((f)->flags & 0x20000) != 0) 205 206 // features 207 enum x86_feature_type { 208 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 209 FEATURE_EXT, // cpuid eax=1, edx register 210 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 211 212 FEATURE_NUM 213 }; 214 215 enum x86_vendors { 216 VENDOR_INTEL = 0, 217 VENDOR_AMD, 218 VENDOR_CYRIX, 219 VENDOR_UMC, 220 VENDOR_NEXGEN, 221 VENDOR_CENTAUR, 222 VENDOR_RISE, 223 VENDOR_TRANSMETA, 224 VENDOR_NSC, 225 226 VENDOR_NUM, 227 VENDOR_UNKNOWN, 228 }; 229 230 typedef struct arch_cpu_info { 231 // saved cpu info 232 enum x86_vendors vendor; 233 uint32 feature[FEATURE_NUM]; 234 char model_name[49]; 235 const char* vendor_name; 236 int type; 237 int family; 238 int extended_family; 239 int stepping; 240 int model; 241 int extended_model; 242 243 struct vm_translation_map_arch_info* active_translation_map; 244 245 // local TSS for this cpu 246 struct tss tss; 247 struct tss double_fault_tss; 248 } arch_cpu_info; 249 250 #ifdef __cplusplus 251 extern "C" { 252 #endif 253 254 #define nop() __asm__ ("nop"::) 255 256 struct arch_thread; 257 258 void __x86_setup_system_time(uint32 conversionFactor); 259 void i386_context_switch(struct arch_thread* oldState, 260 struct arch_thread* newState, addr_t newPageDir); 261 void x86_userspace_thread_exit(void); 262 void x86_end_userspace_thread_exit(void); 263 void x86_enter_userspace(addr_t entry, addr_t stackTop); 264 void i386_set_tss_and_kstack(addr_t kstack); 265 void i386_switch_stack_and_call(addr_t stack, void (*func)(void*), void* arg); 266 void i386_swap_pgdir(addr_t newPageDir); 267 void i386_fnsave(void* fpuState); 268 void i386_fxsave(void* fpuState); 269 void i386_frstor(const void* fpuState); 270 void i386_fxrstor(const void* fpuState); 271 void i386_fnsave_swap(void* oldFpuState, const void* newFpuState); 272 void i386_fxsave_swap(void* oldFpuState, const void* newFpuState); 273 uint32 x86_read_ebp(); 274 uint32 x86_read_cr0(); 275 void x86_write_cr0(uint32 value); 276 uint32 x86_read_cr4(); 277 void x86_write_cr4(uint32 value); 278 uint64 x86_read_msr(uint32 registerNumber); 279 void x86_write_msr(uint32 registerNumber, uint64 value); 280 void x86_set_task_gate(int32 cpu, int32 n, int32 segment); 281 void* x86_get_idt(int32 cpu); 282 uint32 x86_count_mtrrs(void); 283 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 284 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 285 uint8* _type); 286 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 287 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 288 int32 x86_double_fault_get_cpu(void); 289 void x86_double_fault_exception(struct iframe* frame); 290 void x86_page_fault_exception_double_fault(struct iframe* frame); 291 292 293 #define read_cr3(value) \ 294 __asm__("movl %%cr3,%0" : "=r" (value)) 295 296 #define write_cr3(value) \ 297 __asm__("movl %0,%%cr3" : : "r" (value)) 298 299 #define read_dr3(value) \ 300 __asm__("movl %%dr3,%0" : "=r" (value)) 301 302 #define write_dr3(value) \ 303 __asm__("movl %0,%%dr3" : : "r" (value)) 304 305 #define invalidate_TLB(va) \ 306 __asm__("invlpg (%0)" : : "r" (va)) 307 308 #define wbinvd() \ 309 __asm__("wbinvd") 310 311 #define out8(value,port) \ 312 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 313 314 #define out16(value,port) \ 315 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 316 317 #define out32(value,port) \ 318 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 319 320 #define in8(port) ({ \ 321 uint8 _v; \ 322 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 323 _v; \ 324 }) 325 326 #define in16(port) ({ \ 327 uint16 _v; \ 328 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 329 _v; \ 330 }) 331 332 #define in32(port) ({ \ 333 uint32 _v; \ 334 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 335 _v; \ 336 }) 337 338 #define out8_p(value,port) \ 339 __asm__ ("outb %%al,%%dx\n" \ 340 "\tjmp 1f\n" \ 341 "1:\tjmp 1f\n" \ 342 "1:" : : "a" (value), "d" (port)) 343 344 #define in8_p(port) ({ \ 345 uint8 _v; \ 346 __asm__ volatile ("inb %%dx,%%al\n" \ 347 "\tjmp 1f\n" \ 348 "1:\tjmp 1f\n" \ 349 "1:" : "=a" (_v) : "d" (port)); \ 350 _v; \ 351 }) 352 353 extern segment_descriptor* gGDT; 354 355 356 #ifdef __cplusplus 357 } // extern "C" { 358 #endif 359 360 #endif // !_ASSEMBLER 361 362 #endif /* _KERNEL_ARCH_x86_CPU_H */ 363