1 /* 2 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 3 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 4 * Distributed under the terms of the MIT License. 5 * 6 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 7 * Distributed under the terms of the NewOS License. 8 */ 9 #ifndef _KERNEL_ARCH_x86_CPU_H 10 #define _KERNEL_ARCH_x86_CPU_H 11 12 13 #ifndef _ASSEMBLER 14 15 #include <module.h> 16 #include <arch/x86/descriptors.h> 17 18 #ifdef __x86_64__ 19 # include <arch/x86/64/iframe.h> 20 #else 21 # include <arch/x86/32/iframe.h> 22 #endif 23 24 #endif // !_ASSEMBLER 25 26 27 // MSR registers (possibly Intel specific) 28 #define IA32_MSR_TSC 0x10 29 #define IA32_MSR_APIC_BASE 0x1b 30 31 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 32 #define IA32_MSR_SYSENTER_CS 0x174 33 #define IA32_MSR_SYSENTER_ESP 0x175 34 #define IA32_MSR_SYSENTER_EIP 0x176 35 #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 36 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 37 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 38 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 39 40 #define IA32_MSR_EFER 0xc0000080 41 42 43 // MSR APIC BASE bits 44 #define IA32_MSR_APIC_BASE_BSP 0x00000100 45 #define IA32_MSR_APIC_BASE_X2APIC 0x00000400 46 #define IA32_MSR_APIC_BASE_ENABLED 0x00000800 47 #define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000 48 49 // MSR EFER bits 50 // reference 51 #define IA32_MSR_EFER_SYSCALL (1 << 0) 52 #define IA32_MSR_EFER_NX (1 << 11) 53 54 // X2APIC MSRs. 55 #define IA32_MSR_APIC_ID 0x00000802 56 #define IA32_MSR_APIC_VERSION 0x00000803 57 #define IA32_MSR_APIC_TASK_PRIORITY 0x00000808 58 #define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a 59 #define IA32_MSR_APIC_EOI 0x0000080b 60 #define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d 61 #define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f 62 #define IA32_MSR_APIC_ERROR_STATUS 0x00000828 63 #define IA32_MSR_APIC_INTR_COMMAND 0x00000830 64 #define IA32_MSR_APIC_LVT_TIMER 0x00000832 65 #define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833 66 #define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834 67 #define IA32_MSR_APIC_LVT_LINT0 0x00000835 68 #define IA32_MSR_APIC_LVT_LINT1 0x00000836 69 #define IA32_MSR_APIC_LVT_ERROR 0x00000837 70 #define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838 71 #define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839 72 #define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e 73 74 // x86_64 MSRs. 75 #define IA32_MSR_STAR 0xc0000081 76 #define IA32_MSR_LSTAR 0xc0000082 77 #define IA32_MSR_FMASK 0xc0000084 78 #define IA32_MSR_FS_BASE 0xc0000100 79 #define IA32_MSR_GS_BASE 0xc0000101 80 #define IA32_MSR_KERNEL_GS_BASE 0xc0000102 81 82 // K8 MSR registers 83 #define K8_MSR_IPM 0xc0010055 84 85 // x86 features from cpuid eax 1, edx register 86 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5) 87 #define IA32_FEATURE_FPU (1 << 0) // x87 fpu 88 #define IA32_FEATURE_VME (1 << 1) // virtual 8086 89 #define IA32_FEATURE_DE (1 << 2) // debugging extensions 90 #define IA32_FEATURE_PSE (1 << 3) // page size extensions 91 #define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction 92 #define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction 93 #define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing 94 #define IA32_FEATURE_MCE (1 << 7) // machine check exception 95 #define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction 96 #define IA32_FEATURE_APIC (1 << 9) // local apic on chip 97 // (1 << 10) // Reserved 98 #define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT 99 #define IA32_FEATURE_MTRR (1 << 12) // MTRR 100 #define IA32_FEATURE_PGE (1 << 13) // paging global bit 101 #define IA32_FEATURE_MCA (1 << 14) // machine check architecture 102 #define IA32_FEATURE_CMOV (1 << 15) // cmov instruction 103 #define IA32_FEATURE_PAT (1 << 16) // page attribute table 104 #define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages 105 #define IA32_FEATURE_PSN (1 << 18) // processor serial number 106 #define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction 107 // (1 << 20) // Reserved 108 #define IA32_FEATURE_DS (1 << 21) // debug store 109 #define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl 110 #define IA32_FEATURE_MMX (1 << 23) // mmx instructions 111 #define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction 112 #define IA32_FEATURE_SSE (1 << 25) // SSE 113 #define IA32_FEATURE_SSE2 (1 << 26) // SSE2 114 #define IA32_FEATURE_SS (1 << 27) // self snoop 115 #define IA32_FEATURE_HTT (1 << 28) // hyperthreading 116 #define IA32_FEATURE_TM (1 << 29) // thermal monitor 117 #define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86 118 #define IA32_FEATURE_PBE (1 << 31) // pending break enable 119 120 // x86 features from cpuid eax 1, ecx register 121 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4) 122 #define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3 123 #define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction 124 #define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store 125 #define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT 126 #define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store 127 #define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions 128 #define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions 129 #define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep 130 #define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2 131 #define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3 132 #define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID 133 // (1 << 11) // Reserved 134 #define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add 135 #define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B 136 #define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control 137 #define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability 138 // (1 << 16) // Reserved 139 #define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers 140 #define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access 141 #define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1 142 #define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2 143 #define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support 144 #define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction 145 #define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction 146 #define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline 147 #define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions 148 #define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States 149 #define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE 150 #define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions 151 #define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion 152 #define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction 153 #define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor 154 155 // x86 features from cpuid eax 0x80000001, edx register (AMD) 156 // only care about the ones that are unique to this register 157 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 158 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 159 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 160 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 161 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 162 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 163 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 164 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 165 166 // some of the features from cpuid eax 0x80000001, edx register (AMD) are also 167 // available on Intel processors 168 #define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \ 169 | IA32_FEATURE_AMD_EXT_NX \ 170 | IA32_FEATURE_AMD_EXT_RDTSCP \ 171 | IA32_FEATURE_AMD_EXT_LONG) 172 173 // x86 defined features from cpuid eax 6, eax register 174 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 175 #define IA32_FEATURE_DTS (1 << 0) //Digital Thermal Sensor 176 #define IA32_FEATURE_ITB (1 << 1) //Intel Turbo Boost Technology 177 #define IA32_FEATURE_ARAT (1 << 2) //Always running APIC Timer 178 #define IA32_FEATURE_PLN (1 << 4) //Power Limit Notification 179 #define IA32_FEATURE_ECMD (1 << 5) //Extended Clock Modulation Duty 180 #define IA32_FEATURE_PTM (1 << 6) //Package Thermal Management 181 182 // x86 defined features from cpuid eax 6, ecx register 183 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 184 #define IA32_FEATURE_APERFMPERF (1 << 0) //IA32_APERF, IA32_MPERF 185 #define IA32_FEATURE_EPB (1 << 3) //IA32_ENERGY_PERF_BIAS 186 187 // cr4 flags 188 #define IA32_CR4_PAE (1UL << 5) 189 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 190 191 // Memory type ranges 192 #define IA32_MTR_UNCACHED 0 193 #define IA32_MTR_WRITE_COMBINING 1 194 #define IA32_MTR_WRITE_THROUGH 4 195 #define IA32_MTR_WRITE_PROTECTED 5 196 #define IA32_MTR_WRITE_BACK 6 197 198 // EFLAGS register 199 #define X86_EFLAGS_CARRY 0x00000001 200 #define X86_EFLAGS_RESERVED1 0x00000002 201 #define X86_EFLAGS_PARITY 0x00000004 202 #define X86_EFLAGS_AUXILIARY_CARRY 0x00000010 203 #define X86_EFLAGS_ZERO 0x00000040 204 #define X86_EFLAGS_SIGN 0x00000080 205 #define X86_EFLAGS_TRAP 0x00000100 206 #define X86_EFLAGS_INTERRUPT 0x00000200 207 #define X86_EFLAGS_DIRECTION 0x00000400 208 #define X86_EFLAGS_OVERFLOW 0x00000800 209 #define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000 210 #define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12 211 #define X86_EFLAGS_NESTED_TASK 0x00004000 212 #define X86_EFLAGS_RESUME 0x00010000 213 #define X86_EFLAGS_V86_MODE 0x00020000 214 #define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000 215 #define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000 216 #define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000 217 #define X86_EFLAGS_ID 0x00200000 218 219 #define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \ 220 | X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \ 221 | X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW) 222 223 224 // iframe types 225 #define IFRAME_TYPE_SYSCALL 0x1 226 #define IFRAME_TYPE_OTHER 0x2 227 #define IFRAME_TYPE_MASK 0xf 228 229 230 #ifndef _ASSEMBLER 231 232 233 struct X86PagingStructures; 234 235 236 typedef struct x86_mtrr_info { 237 uint64 base; 238 uint64 size; 239 uint8 type; 240 } x86_mtrr_info; 241 242 typedef struct x86_optimized_functions { 243 void (*memcpy)(void* dest, const void* source, size_t count); 244 void* memcpy_end; 245 void (*memset)(void* dest, int value, size_t count); 246 void* memset_end; 247 } x86_optimized_functions; 248 249 typedef struct x86_cpu_module_info { 250 module_info info; 251 uint32 (*count_mtrrs)(void); 252 void (*init_mtrrs)(void); 253 254 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 255 uint8 type); 256 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 257 uint8* _type); 258 void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos, 259 uint32 count); 260 261 void (*get_optimized_functions)(x86_optimized_functions* functions); 262 } x86_cpu_module_info; 263 264 // features 265 enum x86_feature_type { 266 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 267 FEATURE_EXT, // cpuid eax=1, edx register 268 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 269 FEATURE_6_EAX, // cpuid eax=6, eax registers 270 FEATURE_6_ECX, // cpuid eax=6, ecx registers 271 272 FEATURE_NUM 273 }; 274 275 enum x86_vendors { 276 VENDOR_INTEL = 0, 277 VENDOR_AMD, 278 VENDOR_CYRIX, 279 VENDOR_UMC, 280 VENDOR_NEXGEN, 281 VENDOR_CENTAUR, 282 VENDOR_RISE, 283 VENDOR_TRANSMETA, 284 VENDOR_NSC, 285 286 VENDOR_NUM, 287 VENDOR_UNKNOWN, 288 }; 289 290 291 typedef struct arch_cpu_info { 292 // saved cpu info 293 enum x86_vendors vendor; 294 uint32 feature[FEATURE_NUM]; 295 char model_name[49]; 296 const char* vendor_name; 297 int type; 298 int family; 299 int extended_family; 300 int stepping; 301 int model; 302 int extended_model; 303 304 struct X86PagingStructures* active_paging_structures; 305 306 size_t dr6; // temporary storage for debug registers (cf. 307 size_t dr7; // x86_exit_user_debug_at_kernel_entry()) 308 309 // local TSS for this cpu 310 struct tss tss; 311 #ifndef __x86_64__ 312 struct tss double_fault_tss; 313 #endif 314 } arch_cpu_info; 315 316 317 #undef PAUSE 318 #define PAUSE() asm volatile ("pause;") 319 320 #define nop() __asm__ ("nop"::) 321 322 #define x86_read_cr0() ({ \ 323 size_t _v; \ 324 __asm__("mov %%cr0,%0" : "=r" (_v)); \ 325 _v; \ 326 }) 327 328 #define x86_write_cr0(value) \ 329 __asm__("mov %0,%%cr0" : : "r" (value)) 330 331 #define x86_read_cr2() ({ \ 332 size_t _v; \ 333 __asm__("mov %%cr2,%0" : "=r" (_v)); \ 334 _v; \ 335 }) 336 337 #define x86_read_cr3() ({ \ 338 size_t _v; \ 339 __asm__("mov %%cr3,%0" : "=r" (_v)); \ 340 _v; \ 341 }) 342 343 #define x86_write_cr3(value) \ 344 __asm__("mov %0,%%cr3" : : "r" (value)) 345 346 #define x86_read_cr4() ({ \ 347 size_t _v; \ 348 __asm__("mov %%cr4,%0" : "=r" (_v)); \ 349 _v; \ 350 }) 351 352 #define x86_write_cr4(value) \ 353 __asm__("mov %0,%%cr4" : : "r" (value)) 354 355 #define x86_read_dr3() ({ \ 356 size_t _v; \ 357 __asm__("mov %%dr3,%0" : "=r" (_v)); \ 358 _v; \ 359 }) 360 361 #define x86_write_dr3(value) \ 362 __asm__("mov %0,%%dr3" : : "r" (value)) 363 364 #define invalidate_TLB(va) \ 365 __asm__("invlpg (%0)" : : "r" (va)) 366 367 #define wbinvd() \ 368 __asm__("wbinvd") 369 370 #define out8(value,port) \ 371 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 372 373 #define out16(value,port) \ 374 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 375 376 #define out32(value,port) \ 377 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 378 379 #define in8(port) ({ \ 380 uint8 _v; \ 381 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 382 _v; \ 383 }) 384 385 #define in16(port) ({ \ 386 uint16 _v; \ 387 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 388 _v; \ 389 }) 390 391 #define in32(port) ({ \ 392 uint32 _v; \ 393 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 394 _v; \ 395 }) 396 397 #define out8_p(value,port) \ 398 __asm__ ("outb %%al,%%dx\n" \ 399 "\tjmp 1f\n" \ 400 "1:\tjmp 1f\n" \ 401 "1:" : : "a" (value), "d" (port)) 402 403 #define in8_p(port) ({ \ 404 uint8 _v; \ 405 __asm__ volatile ("inb %%dx,%%al\n" \ 406 "\tjmp 1f\n" \ 407 "1:\tjmp 1f\n" \ 408 "1:" : "=a" (_v) : "d" (port)); \ 409 _v; \ 410 }) 411 412 413 #ifdef __cplusplus 414 extern "C" { 415 #endif 416 417 struct arch_thread; 418 419 #ifdef __x86_64__ 420 void __x86_setup_system_time(uint64 conversionFactor, 421 uint64 conversionFactorNsecs); 422 #else 423 void __x86_setup_system_time(uint32 conversionFactor, 424 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 425 #endif 426 427 void x86_context_switch(struct arch_thread* oldState, 428 struct arch_thread* newState); 429 void x86_userspace_thread_exit(void); 430 void x86_end_userspace_thread_exit(void); 431 void x86_swap_pgdir(addr_t newPageDir); 432 void x86_fxsave(void* fpuState); 433 void x86_fxrstor(const void* fpuState); 434 void x86_noop_swap(void* oldFpuState, const void* newFpuState); 435 void x86_fxsave_swap(void* oldFpuState, const void* newFpuState); 436 addr_t x86_get_stack_frame(); 437 uint64 x86_read_msr(uint32 registerNumber); 438 void x86_write_msr(uint32 registerNumber, uint64 value); 439 uint32 x86_count_mtrrs(void); 440 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 441 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 442 uint8* _type); 443 void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, 444 uint32 count); 445 void x86_init_fpu(); 446 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 447 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 448 int32 x86_double_fault_get_cpu(void); 449 450 void x86_invalid_exception(iframe* frame); 451 void x86_fatal_exception(iframe* frame); 452 void x86_unexpected_exception(iframe* frame); 453 void x86_hardware_interrupt(iframe* frame); 454 void x86_page_fault_exception(iframe* iframe); 455 456 #ifndef __x86_64__ 457 458 void x86_fnsave(void* fpuState); 459 void x86_frstor(const void* fpuState); 460 void x86_fnsave_swap(void* oldFpuState, const void* newFpuState); 461 462 #endif 463 464 465 #ifdef __cplusplus 466 } // extern "C" { 467 #endif 468 469 #endif // !_ASSEMBLER 470 471 #endif /* _KERNEL_ARCH_x86_CPU_H */ 472