1 /* 2 * Copyright 2002-2007, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 6 * Distributed under the terms of the NewOS License. 7 */ 8 #ifndef _KERNEL_ARCH_x86_CPU_H 9 #define _KERNEL_ARCH_x86_CPU_H 10 11 12 #ifndef _ASSEMBLER 13 14 #include <module.h> 15 #include <arch/x86/descriptors.h> 16 17 #endif // !_ASSEMBLER 18 19 20 // MSR registers (possibly Intel specific) 21 #define IA32_MSR_APIC_BASE 0x1b 22 23 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 24 #define IA32_MSR_SYSENTER_CS 0x174 25 #define IA32_MSR_SYSENTER_ESP 0x175 26 #define IA32_MSR_SYSENTER_EIP 0x176 27 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 28 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 29 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 30 31 // x86 features from cpuid eax 1, edx register 32 #define IA32_FEATURE_FPU 0x00000001 // x87 fpu 33 #define IA32_FEATURE_VME 0x00000002 // virtual 8086 34 #define IA32_FEATURE_DE 0x00000004 // debugging extensions 35 #define IA32_FEATURE_PSE 0x00000008 // page size extensions 36 #define IA32_FEATURE_TSC 0x00000010 // rdtsc instruction 37 #define IA32_FEATURE_MSR 0x00000020 // rdmsr/wrmsr instruction 38 #define IA32_FEATURE_PAE 0x00000040 // extended 3 level page table addressing 39 #define IA32_FEATURE_MCE 0x00000080 // machine check exception 40 #define IA32_FEATURE_CX8 0x00000100 // cmpxchg8b instruction 41 #define IA32_FEATURE_APIC 0x00000200 // local apic on chip 42 #define IA32_FEATURE_SEP 0x00000800 // SYSENTER/SYSEXIT 43 #define IA32_FEATURE_MTRR 0x00001000 // MTRR 44 #define IA32_FEATURE_PGE 0x00002000 // paging global bit 45 #define IA32_FEATURE_MCA 0x00004000 // machine check architecture 46 #define IA32_FEATURE_CMOV 0x00008000 // cmov instruction 47 #define IA32_FEATURE_PAT 0x00010000 // page attribute table 48 #define IA32_FEATURE_PSE36 0x00020000 // page size extensions with 4MB pages 49 #define IA32_FEATURE_PSN 0x00040000 // processor serial number 50 #define IA32_FEATURE_CLFSH 0x00080000 // cflush instruction 51 #define IA32_FEATURE_DS 0x00200000 // debug store 52 #define IA32_FEATURE_ACPI 0x00400000 // thermal monitor and clock ctrl 53 #define IA32_FEATURE_MMX 0x00800000 // mmx instructions 54 #define IA32_FEATURE_FXSR 0x01000000 // FXSAVE/FXRSTOR instruction 55 #define IA32_FEATURE_SSE 0x02000000 // SSE 56 #define IA32_FEATURE_SSE2 0x04000000 // SSE2 57 #define IA32_FEATURE_SS 0x08000000 // self snoop 58 #define IA32_FEATURE_HTT 0x10000000 // hyperthreading 59 #define IA32_FEATURE_TM 0x20000000 // thermal monitor 60 #define IA32_FEATURE_PBE 0x80000000 // pending break enable 61 62 // x86 features from cpuid eax 1, ecx register 63 #define IA32_FEATURE_EXT_SSE3 0x00000001 // SSE3 64 #define IA32_FEATURE_EXT_MONITOR 0x00000008 // MONITOR/MWAIT 65 #define IA32_FEATURE_EXT_DSCPL 0x00000010 // CPL qualified debug store 66 #define IA32_FEATURE_EXT_EST 0x00000080 // speedstep 67 #define IA32_FEATURE_EXT_TM2 0x00000100 // thermal monitor 2 68 #define IA32_FEATURE_EXT_CNXTID 0x00000400 // L1 context ID 69 70 // x86 features from cpuid eax 0x80000001, edx register (AMD) 71 // only care about the ones that are unique to this register 72 #define IA32_FEATURE_AMD_EXT_SYSCALL (1<<11) // SYSCALL/SYSRET 73 #define IA32_FEATURE_AMD_EXT_NX (1<<20) // no execute bit 74 #define IA32_FEATURE_AMD_EXT_MMXEXT (1<<22) // mmx extensions 75 #define IA32_FEATURE_AMD_EXT_FFXSR (1<<25) // fast FXSAVE/FXRSTOR 76 #define IA32_FEATURE_AMD_EXT_RDTSCP (1<<27) // rdtscp instruction 77 #define IA32_FEATURE_AMD_EXT_LONG (1<<29) // long mode 78 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1<<30) // 3DNow! extensions 79 #define IA32_FEATURE_AMD_EXT_3DNOW (1<<31) // 3DNow! 80 81 // cr4 flags 82 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 83 84 // Memory type ranges 85 #define IA32_MTR_UNCACHED 0 86 #define IA32_MTR_WRITE_COMBINING 1 87 #define IA32_MTR_WRITE_THROUGH 4 88 #define IA32_MTR_WRITE_PROTECTED 5 89 #define IA32_MTR_WRITE_BACK 6 90 91 92 // iframe types 93 #define IFRAME_TYPE_SYSCALL 0x1 94 #define IFRAME_TYPE_OTHER 0x2 95 #define IFRAME_TYPE_MASK 0xf 96 97 98 #ifndef _ASSEMBLER 99 100 typedef struct x86_optimized_functions { 101 void (*memcpy)(void* dest, const void* source, size_t count); 102 void* memcpy_end; 103 } x86_optimized_functions; 104 105 typedef struct x86_cpu_module_info { 106 module_info info; 107 uint32 (*count_mtrrs)(void); 108 void (*init_mtrrs)(void); 109 110 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, uint8 type); 111 status_t (*get_mtrr)(uint32 index, uint64 *_base, uint64 *_length, 112 uint8 *_type); 113 114 void (*get_optimized_functions)(x86_optimized_functions* functions); 115 } x86_cpu_module_info; 116 117 118 struct tss { 119 uint16 prev_task; 120 uint16 unused0; 121 uint32 sp0; 122 uint32 ss0; 123 uint32 sp1; 124 uint32 ss1; 125 uint32 sp2; 126 uint32 ss2; 127 uint32 cr3; 128 uint32 eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi; 129 uint32 es, cs, ss, ds, fs, gs; 130 uint32 ldt_seg_selector; 131 uint16 unused1; 132 uint16 io_map_base; 133 }; 134 135 struct iframe { 136 uint32 type; // iframe type 137 uint32 gs; 138 uint32 fs; 139 uint32 es; 140 uint32 ds; 141 uint32 edi; 142 uint32 esi; 143 uint32 ebp; 144 uint32 esp; 145 uint32 ebx; 146 uint32 edx; 147 uint32 ecx; 148 uint32 eax; 149 uint32 orig_eax; 150 uint32 orig_edx; 151 uint32 vector; 152 uint32 error_code; 153 uint32 eip; 154 uint32 cs; 155 uint32 flags; 156 uint32 user_esp; 157 uint32 user_ss; 158 }; 159 160 // features 161 enum x86_feature_type { 162 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 163 FEATURE_EXT, // cpuid eax=1, edx register 164 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 165 166 FEATURE_NUM 167 }; 168 169 enum x86_vendors { 170 VENDOR_INTEL = 0, 171 VENDOR_AMD, 172 VENDOR_CYRIX, 173 VENDOR_UMC, 174 VENDOR_NEXGEN, 175 VENDOR_CENTAUR, 176 VENDOR_RISE, 177 VENDOR_TRANSMETA, 178 VENDOR_NSC, 179 180 VENDOR_NUM, 181 VENDOR_UNKNOWN, 182 }; 183 184 typedef struct arch_cpu_info { 185 // saved cpu info 186 enum x86_vendors vendor; 187 enum x86_feature_type feature[FEATURE_NUM]; 188 char model_name[49]; 189 const char *vendor_name; 190 int type; 191 int family; 192 int stepping; 193 int model; 194 char feature_string[256]; 195 196 // local TSS for this cpu 197 struct tss tss; 198 struct tss double_fault_tss; 199 } arch_cpu_info; 200 201 #ifdef __cplusplus 202 extern "C" { 203 #endif 204 205 #define nop() __asm__ ("nop"::) 206 207 struct arch_thread; 208 209 void __x86_setup_system_time(uint32 cv_factor); 210 void i386_context_switch(struct arch_thread *old_state, struct arch_thread *new_state, addr_t new_pgdir); 211 void x86_userspace_thread_exit(void); 212 void x86_end_userspace_thread_exit(void); 213 void x86_enter_userspace(addr_t entry, addr_t stackTop); 214 void i386_set_tss_and_kstack(addr_t kstack); 215 void i386_switch_stack_and_call(addr_t stack, void (*func)(void *), void *arg); 216 void i386_swap_pgdir(addr_t new_pgdir); 217 void i386_fnsave(void *fpu_state); 218 void i386_fxsave(void *fpu_state); 219 void i386_frstor(const void *fpu_state); 220 void i386_fxrstor(const void *fpu_state); 221 void i386_fnsave_swap(void *old_fpu_state, const void *new_fpu_state); 222 void i386_fxsave_swap(void *old_fpu_state, const void *new_fpu_state); 223 uint32 x86_read_ebp(); 224 uint32 x86_read_cr0(); 225 void x86_write_cr0(uint32 value); 226 uint32 x86_read_cr4(); 227 void x86_write_cr4(uint32 value); 228 uint64 x86_read_msr(uint32 registerNumber); 229 void x86_write_msr(uint32 registerNumber, uint64 value); 230 void x86_set_task_gate(int32 n, int32 segment); 231 uint32 x86_count_mtrrs(void); 232 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 233 status_t x86_get_mtrr(uint32 index, uint64 *_base, uint64 *_length, uint8 *_type); 234 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 235 236 237 #define read_cr3(value) \ 238 __asm__("movl %%cr3,%0" : "=r" (value)) 239 240 #define write_cr3(value) \ 241 __asm__("movl %0,%%cr3" : : "r" (value)) 242 243 #define read_dr3(value) \ 244 __asm__("movl %%dr3,%0" : "=r" (value)) 245 246 #define write_dr3(value) \ 247 __asm__("movl %0,%%dr3" : : "r" (value)) 248 249 #define invalidate_TLB(va) \ 250 __asm__("invlpg (%0)" : : "r" (va)) 251 252 #define wbinvd() \ 253 __asm__("wbinvd") 254 255 #define out8(value,port) \ 256 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 257 258 #define out16(value,port) \ 259 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 260 261 #define out32(value,port) \ 262 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 263 264 #define in8(port) ({ \ 265 uint8 _v; \ 266 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 267 _v; \ 268 }) 269 270 #define in16(port) ({ \ 271 uint16 _v; \ 272 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 273 _v; \ 274 }) 275 276 #define in32(port) ({ \ 277 uint32 _v; \ 278 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 279 _v; \ 280 }) 281 282 #define out8_p(value,port) \ 283 __asm__ ("outb %%al,%%dx\n" \ 284 "\tjmp 1f\n" \ 285 "1:\tjmp 1f\n" \ 286 "1:" : : "a" (value), "d" (port)) 287 288 #define in8_p(port) ({ \ 289 uint8 _v; \ 290 __asm__ volatile ("inb %%dx,%%al\n" \ 291 "\tjmp 1f\n" \ 292 "1:\tjmp 1f\n" \ 293 "1:" : "=a" (_v) : "d" (port)); \ 294 _v; \ 295 }) 296 297 extern segment_descriptor *gGDT; 298 299 300 #ifdef __cplusplus 301 } // extern "C" { 302 #endif 303 304 #endif // !_ASSEMBLER 305 306 #endif /* _KERNEL_ARCH_x86_CPU_H */ 307