1 /* 2 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 3 * Distributed under the terms of the MIT License. 4 * 5 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 6 * Distributed under the terms of the NewOS License. 7 */ 8 #ifndef _KERNEL_ARCH_x86_CPU_H 9 #define _KERNEL_ARCH_x86_CPU_H 10 11 12 #ifndef _ASSEMBLER 13 14 #include <module.h> 15 #include <arch/x86/descriptors.h> 16 17 #endif // !_ASSEMBLER 18 19 20 #undef PAUSE 21 #define PAUSE() asm volatile ("pause;") 22 23 24 // MSR registers (possibly Intel specific) 25 #define IA32_MSR_TSC 0x10 26 #define IA32_MSR_APIC_BASE 0x1b 27 28 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 29 #define IA32_MSR_SYSENTER_CS 0x174 30 #define IA32_MSR_SYSENTER_ESP 0x175 31 #define IA32_MSR_SYSENTER_EIP 0x176 32 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 33 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 34 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 35 36 // x86 features from cpuid eax 1, edx register 37 #define IA32_FEATURE_FPU 0x00000001 // x87 fpu 38 #define IA32_FEATURE_VME 0x00000002 // virtual 8086 39 #define IA32_FEATURE_DE 0x00000004 // debugging extensions 40 #define IA32_FEATURE_PSE 0x00000008 // page size extensions 41 #define IA32_FEATURE_TSC 0x00000010 // rdtsc instruction 42 #define IA32_FEATURE_MSR 0x00000020 // rdmsr/wrmsr instruction 43 #define IA32_FEATURE_PAE 0x00000040 // extended 3 level page table addressing 44 #define IA32_FEATURE_MCE 0x00000080 // machine check exception 45 #define IA32_FEATURE_CX8 0x00000100 // cmpxchg8b instruction 46 #define IA32_FEATURE_APIC 0x00000200 // local apic on chip 47 #define IA32_FEATURE_SEP 0x00000800 // SYSENTER/SYSEXIT 48 #define IA32_FEATURE_MTRR 0x00001000 // MTRR 49 #define IA32_FEATURE_PGE 0x00002000 // paging global bit 50 #define IA32_FEATURE_MCA 0x00004000 // machine check architecture 51 #define IA32_FEATURE_CMOV 0x00008000 // cmov instruction 52 #define IA32_FEATURE_PAT 0x00010000 // page attribute table 53 #define IA32_FEATURE_PSE36 0x00020000 // page size extensions with 4MB pages 54 #define IA32_FEATURE_PSN 0x00040000 // processor serial number 55 #define IA32_FEATURE_CLFSH 0x00080000 // cflush instruction 56 #define IA32_FEATURE_DS 0x00200000 // debug store 57 #define IA32_FEATURE_ACPI 0x00400000 // thermal monitor and clock ctrl 58 #define IA32_FEATURE_MMX 0x00800000 // mmx instructions 59 #define IA32_FEATURE_FXSR 0x01000000 // FXSAVE/FXRSTOR instruction 60 #define IA32_FEATURE_SSE 0x02000000 // SSE 61 #define IA32_FEATURE_SSE2 0x04000000 // SSE2 62 #define IA32_FEATURE_SS 0x08000000 // self snoop 63 #define IA32_FEATURE_HTT 0x10000000 // hyperthreading 64 #define IA32_FEATURE_TM 0x20000000 // thermal monitor 65 #define IA32_FEATURE_PBE 0x80000000 // pending break enable 66 67 // x86 features from cpuid eax 1, ecx register 68 #define IA32_FEATURE_EXT_SSE3 0x00000001 // SSE3 69 #define IA32_FEATURE_EXT_MONITOR 0x00000008 // MONITOR/MWAIT 70 #define IA32_FEATURE_EXT_DSCPL 0x00000010 // CPL qualified debug store 71 #define IA32_FEATURE_EXT_EST 0x00000080 // speedstep 72 #define IA32_FEATURE_EXT_TM2 0x00000100 // thermal monitor 2 73 #define IA32_FEATURE_EXT_CNXTID 0x00000400 // L1 context ID 74 75 // x86 features from cpuid eax 0x80000001, edx register (AMD) 76 // only care about the ones that are unique to this register 77 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 78 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 79 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 80 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 81 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 82 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 83 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 84 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 85 86 // cr4 flags 87 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 88 89 // Memory type ranges 90 #define IA32_MTR_UNCACHED 0 91 #define IA32_MTR_WRITE_COMBINING 1 92 #define IA32_MTR_WRITE_THROUGH 4 93 #define IA32_MTR_WRITE_PROTECTED 5 94 #define IA32_MTR_WRITE_BACK 6 95 96 97 // iframe types 98 #define IFRAME_TYPE_SYSCALL 0x1 99 #define IFRAME_TYPE_OTHER 0x2 100 #define IFRAME_TYPE_MASK 0xf 101 102 103 #ifndef _ASSEMBLER 104 105 typedef struct x86_mtrr_info { 106 uint64 base; 107 uint64 size; 108 uint8 type; 109 } x86_mtrr_info; 110 111 typedef struct x86_optimized_functions { 112 void (*memcpy)(void* dest, const void* source, size_t count); 113 void* memcpy_end; 114 void (*memset)(void* dest, int value, size_t count); 115 void* memset_end; 116 } x86_optimized_functions; 117 118 typedef struct x86_cpu_module_info { 119 module_info info; 120 uint32 (*count_mtrrs)(void); 121 void (*init_mtrrs)(void); 122 123 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 124 uint8 type); 125 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 126 uint8* _type); 127 void (*set_mtrrs)(const x86_mtrr_info* infos, uint32 count); 128 129 void (*get_optimized_functions)(x86_optimized_functions* functions); 130 } x86_cpu_module_info; 131 132 133 struct tss { 134 uint16 prev_task; 135 uint16 unused0; 136 uint32 sp0; 137 uint32 ss0; 138 uint32 sp1; 139 uint32 ss1; 140 uint32 sp2; 141 uint32 ss2; 142 uint32 cr3; 143 uint32 eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi; 144 uint32 es, cs, ss, ds, fs, gs; 145 uint32 ldt_seg_selector; 146 uint16 unused1; 147 uint16 io_map_base; 148 }; 149 150 struct iframe { 151 uint32 type; // iframe type 152 uint32 gs; 153 uint32 fs; 154 uint32 es; 155 uint32 ds; 156 uint32 edi; 157 uint32 esi; 158 uint32 ebp; 159 uint32 esp; 160 uint32 ebx; 161 uint32 edx; 162 uint32 ecx; 163 uint32 eax; 164 uint32 orig_eax; 165 uint32 orig_edx; 166 uint32 vector; 167 uint32 error_code; 168 uint32 eip; 169 uint32 cs; 170 uint32 flags; 171 172 // user_esp and user_ss are only present when the iframe is a userland 173 // iframe (IFRAME_IS_USER()). A kernel iframe is shorter. 174 uint32 user_esp; 175 uint32 user_ss; 176 }; 177 178 struct vm86_iframe { 179 uint32 type; // iframe type 180 uint32 __null_gs; 181 uint32 __null_fs; 182 uint32 __null_es; 183 uint32 __null_ds; 184 uint32 edi; 185 uint32 esi; 186 uint32 ebp; 187 uint32 __kern_esp; 188 uint32 ebx; 189 uint32 edx; 190 uint32 ecx; 191 uint32 eax; 192 uint32 orig_eax; 193 uint32 orig_edx; 194 uint32 vector; 195 uint32 error_code; 196 uint32 eip; 197 uint16 cs, __csh; 198 uint32 flags; 199 uint32 esp; 200 uint16 ss, __ssh; 201 202 /* vm86 mode specific part */ 203 uint16 es, __esh; 204 uint16 ds, __dsh; 205 uint16 fs, __fsh; 206 uint16 gs, __gsh; 207 }; 208 209 #define IFRAME_IS_USER(f) ((f)->cs == USER_CODE_SEG \ 210 || ((f)->flags & 0x20000) != 0) 211 #define IFRAME_IS_VM86(f) (((f)->flags & 0x20000) != 0) 212 213 // features 214 enum x86_feature_type { 215 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 216 FEATURE_EXT, // cpuid eax=1, edx register 217 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 218 219 FEATURE_NUM 220 }; 221 222 enum x86_vendors { 223 VENDOR_INTEL = 0, 224 VENDOR_AMD, 225 VENDOR_CYRIX, 226 VENDOR_UMC, 227 VENDOR_NEXGEN, 228 VENDOR_CENTAUR, 229 VENDOR_RISE, 230 VENDOR_TRANSMETA, 231 VENDOR_NSC, 232 233 VENDOR_NUM, 234 VENDOR_UNKNOWN, 235 }; 236 237 typedef struct arch_cpu_info { 238 // saved cpu info 239 enum x86_vendors vendor; 240 uint32 feature[FEATURE_NUM]; 241 char model_name[49]; 242 const char* vendor_name; 243 int type; 244 int family; 245 int extended_family; 246 int stepping; 247 int model; 248 int extended_model; 249 250 struct vm_translation_map_arch_info* active_translation_map; 251 252 // local TSS for this cpu 253 struct tss tss; 254 struct tss double_fault_tss; 255 } arch_cpu_info; 256 257 #ifdef __cplusplus 258 extern "C" { 259 #endif 260 261 #define nop() __asm__ ("nop"::) 262 263 struct arch_thread; 264 265 void __x86_setup_system_time(uint32 conversionFactor, 266 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 267 void i386_context_switch(struct arch_thread* oldState, 268 struct arch_thread* newState, addr_t newPageDir); 269 void x86_userspace_thread_exit(void); 270 void x86_end_userspace_thread_exit(void); 271 void x86_enter_userspace(addr_t entry, addr_t stackTop); 272 void i386_set_tss_and_kstack(addr_t kstack); 273 void i386_swap_pgdir(addr_t newPageDir); 274 void i386_fnsave(void* fpuState); 275 void i386_fxsave(void* fpuState); 276 void i386_frstor(const void* fpuState); 277 void i386_fxrstor(const void* fpuState); 278 void i386_fnsave_swap(void* oldFpuState, const void* newFpuState); 279 void i386_fxsave_swap(void* oldFpuState, const void* newFpuState); 280 uint32 x86_read_ebp(); 281 uint32 x86_read_cr0(); 282 void x86_write_cr0(uint32 value); 283 uint32 x86_read_cr4(); 284 void x86_write_cr4(uint32 value); 285 uint64 x86_read_msr(uint32 registerNumber); 286 void x86_write_msr(uint32 registerNumber, uint64 value); 287 void x86_set_task_gate(int32 cpu, int32 n, int32 segment); 288 void* x86_get_idt(int32 cpu); 289 uint32 x86_count_mtrrs(void); 290 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 291 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 292 uint8* _type); 293 void x86_set_mtrrs(const x86_mtrr_info* infos, uint32 count); 294 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 295 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 296 int32 x86_double_fault_get_cpu(void); 297 void x86_double_fault_exception(struct iframe* frame); 298 void x86_page_fault_exception_double_fault(struct iframe* frame); 299 300 301 #define read_cr3(value) \ 302 __asm__("movl %%cr3,%0" : "=r" (value)) 303 304 #define write_cr3(value) \ 305 __asm__("movl %0,%%cr3" : : "r" (value)) 306 307 #define read_dr3(value) \ 308 __asm__("movl %%dr3,%0" : "=r" (value)) 309 310 #define write_dr3(value) \ 311 __asm__("movl %0,%%dr3" : : "r" (value)) 312 313 #define invalidate_TLB(va) \ 314 __asm__("invlpg (%0)" : : "r" (va)) 315 316 #define wbinvd() \ 317 __asm__("wbinvd") 318 319 #define out8(value,port) \ 320 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 321 322 #define out16(value,port) \ 323 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 324 325 #define out32(value,port) \ 326 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 327 328 #define in8(port) ({ \ 329 uint8 _v; \ 330 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 331 _v; \ 332 }) 333 334 #define in16(port) ({ \ 335 uint16 _v; \ 336 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 337 _v; \ 338 }) 339 340 #define in32(port) ({ \ 341 uint32 _v; \ 342 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 343 _v; \ 344 }) 345 346 #define out8_p(value,port) \ 347 __asm__ ("outb %%al,%%dx\n" \ 348 "\tjmp 1f\n" \ 349 "1:\tjmp 1f\n" \ 350 "1:" : : "a" (value), "d" (port)) 351 352 #define in8_p(port) ({ \ 353 uint8 _v; \ 354 __asm__ volatile ("inb %%dx,%%al\n" \ 355 "\tjmp 1f\n" \ 356 "1:\tjmp 1f\n" \ 357 "1:" : "=a" (_v) : "d" (port)); \ 358 _v; \ 359 }) 360 361 extern segment_descriptor* gGDT; 362 363 364 #ifdef __cplusplus 365 } // extern "C" { 366 #endif 367 368 #endif // !_ASSEMBLER 369 370 #endif /* _KERNEL_ARCH_x86_CPU_H */ 371