1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 5 * Distributed under the terms of the MIT License. 6 * 7 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 8 * Distributed under the terms of the NewOS License. 9 */ 10 #ifndef _KERNEL_ARCH_x86_CPU_H 11 #define _KERNEL_ARCH_x86_CPU_H 12 13 14 #ifndef _ASSEMBLER 15 16 #include <module.h> 17 18 #include <arch_thread_types.h> 19 20 #include <arch/x86/arch_altcodepatch.h> 21 #include <arch/x86/arch_cpuasm.h> 22 #include <arch/x86/descriptors.h> 23 24 #ifdef __x86_64__ 25 # include <arch/x86/64/cpu.h> 26 #endif 27 28 #endif // !_ASSEMBLER 29 30 31 #define CPU_MAX_CACHE_LEVEL 8 32 33 #define CACHE_LINE_SIZE 64 34 35 36 // MSR registers (possibly Intel specific) 37 #define IA32_MSR_TSC 0x10 38 #define IA32_MSR_PLATFORM_ID 0x17 39 #define IA32_MSR_APIC_BASE 0x1b 40 #define IA32_MSR_SPEC_CTRL 0x48 41 #define IA32_MSR_PRED_CMD 0x49 42 #define IA32_MSR_UCODE_WRITE 0x79 // IA32_BIOS_UPDT_TRIG 43 #define IA32_MSR_UCODE_REV 0x8b // IA32_BIOS_SIGN_ID 44 #define IA32_MSR_PLATFORM_INFO 0xce 45 #define IA32_MSR_MPERF 0xe7 46 #define IA32_MSR_APERF 0xe8 47 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 48 #define IA32_MSR_ARCH_CAPABILITIES 0x10a 49 #define IA32_MSR_FLUSH_CMD 0x10b 50 #define IA32_MSR_SYSENTER_CS 0x174 51 #define IA32_MSR_SYSENTER_ESP 0x175 52 #define IA32_MSR_SYSENTER_EIP 0x176 53 #define IA32_MSR_PERF_STATUS 0x198 54 #define IA32_MSR_PERF_CTL 0x199 55 #define IA32_MSR_TURBO_RATIO_LIMIT 0x1ad 56 #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 57 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 58 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 59 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 60 61 // MSR SPEC CTRL bits 62 #define IA32_MSR_SPEC_CTRL_IBRS (1 << 0) 63 #define IA32_MSR_SPEC_CTRL_STIBP (1 << 1) 64 #define IA32_MSR_SPEC_CTRL_SSBD (1 << 2) 65 66 // MSR PRED CMD bits 67 #define IA32_MSR_PRED_CMD_IBPB (1 << 0) 68 69 // MSR APIC BASE bits 70 #define IA32_MSR_APIC_BASE_BSP 0x00000100 71 #define IA32_MSR_APIC_BASE_X2APIC 0x00000400 72 #define IA32_MSR_APIC_BASE_ENABLED 0x00000800 73 #define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000 74 75 // MSR EFER bits 76 // reference 77 #define IA32_MSR_EFER_SYSCALL (1 << 0) 78 #define IA32_MSR_EFER_NX (1 << 11) 79 80 // MSR ARCH CAPABILITIES bits 81 #define IA32_MSR_ARCH_CAP_RDCL_NO (1 << 0) 82 #define IA32_MSR_ARCH_CAP_IBRS_ALL (1 << 1) 83 #define IA32_MSR_ARCH_CAP_RSBA (1 << 2) 84 #define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY (1 << 3) 85 #define IA32_MSR_ARCH_CAP_SSB_NO (1 << 4) 86 87 // MSR FLUSH CMD bits 88 #define IA32_MSR_L1D_FLUSH (1 << 1) 89 90 // X2APIC MSRs. 91 #define IA32_MSR_APIC_ID 0x00000802 92 #define IA32_MSR_APIC_VERSION 0x00000803 93 #define IA32_MSR_APIC_TASK_PRIORITY 0x00000808 94 #define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a 95 #define IA32_MSR_APIC_EOI 0x0000080b 96 #define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d 97 #define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f 98 #define IA32_MSR_APIC_ERROR_STATUS 0x00000828 99 #define IA32_MSR_APIC_INTR_COMMAND 0x00000830 100 #define IA32_MSR_APIC_LVT_TIMER 0x00000832 101 #define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833 102 #define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834 103 #define IA32_MSR_APIC_LVT_LINT0 0x00000835 104 #define IA32_MSR_APIC_LVT_LINT1 0x00000836 105 #define IA32_MSR_APIC_LVT_ERROR 0x00000837 106 #define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838 107 #define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839 108 #define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e 109 #define IA32_MSR_APIC_SELF_IPI 0x0000083f 110 #define IA32_MSR_XSS 0x00000da0 111 112 // x86_64 MSRs. 113 #define IA32_MSR_EFER 0xc0000080 114 #define IA32_MSR_STAR 0xc0000081 115 #define IA32_MSR_LSTAR 0xc0000082 116 #define IA32_MSR_CSTAR 0xc0000083 117 #define IA32_MSR_FMASK 0xc0000084 118 #define IA32_MSR_FS_BASE 0xc0000100 119 #define IA32_MSR_GS_BASE 0xc0000101 120 #define IA32_MSR_KERNEL_GS_BASE 0xc0000102 121 #define IA32_MSR_TSC_AUX 0xc0000103 122 123 // K8 MSR registers 124 #define K8_MSR_IPM 0xc0010055 125 126 // x86 features from cpuid eax 1, edx register 127 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5) 128 #define IA32_FEATURE_FPU (1 << 0) // x87 fpu 129 #define IA32_FEATURE_VME (1 << 1) // virtual 8086 130 #define IA32_FEATURE_DE (1 << 2) // debugging extensions 131 #define IA32_FEATURE_PSE (1 << 3) // page size extensions 132 #define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction 133 #define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction 134 #define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing 135 #define IA32_FEATURE_MCE (1 << 7) // machine check exception 136 #define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction 137 #define IA32_FEATURE_APIC (1 << 9) // local apic on chip 138 // (1 << 10) // Reserved 139 #define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT 140 #define IA32_FEATURE_MTRR (1 << 12) // MTRR 141 #define IA32_FEATURE_PGE (1 << 13) // paging global bit 142 #define IA32_FEATURE_MCA (1 << 14) // machine check architecture 143 #define IA32_FEATURE_CMOV (1 << 15) // cmov instruction 144 #define IA32_FEATURE_PAT (1 << 16) // page attribute table 145 #define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages 146 #define IA32_FEATURE_PSN (1 << 18) // processor serial number 147 #define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction 148 // (1 << 20) // Reserved 149 #define IA32_FEATURE_DS (1 << 21) // debug store 150 #define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl 151 #define IA32_FEATURE_MMX (1 << 23) // mmx instructions 152 #define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction 153 #define IA32_FEATURE_SSE (1 << 25) // SSE 154 #define IA32_FEATURE_SSE2 (1 << 26) // SSE2 155 #define IA32_FEATURE_SS (1 << 27) // self snoop 156 #define IA32_FEATURE_HTT (1 << 28) // hyperthreading 157 #define IA32_FEATURE_TM (1 << 29) // thermal monitor 158 #define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86 159 #define IA32_FEATURE_PBE (1 << 31) // pending break enable 160 161 // x86 features from cpuid eax 1, ecx register 162 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4) 163 #define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3 164 #define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction 165 #define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store 166 #define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT 167 #define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store 168 #define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions 169 #define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions 170 #define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep 171 #define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2 172 #define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3 173 #define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID 174 // (1 << 11) // Reserved 175 #define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add 176 #define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B 177 #define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control 178 #define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability 179 // (1 << 16) // Reserved 180 #define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers 181 #define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access 182 #define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1 183 #define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2 184 #define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support 185 #define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction 186 #define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction 187 #define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline 188 #define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions 189 #define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States 190 #define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE 191 #define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions 192 #define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion 193 #define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction 194 #define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor 195 196 // x86 features from cpuid eax 0x80000001, ecx register (AMD) 197 #define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode 198 #define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions 199 200 // x86 features from cpuid eax 0x80000001, edx register (AMD) 201 // only care about the ones that are unique to this register 202 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 203 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 204 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 205 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 206 #define IA32_FEATURE_AMD_EXT_PDPE1GB (1 << 26) // Gibibyte pages 207 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 208 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 209 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 210 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 211 212 // some of the features from cpuid eax 0x80000001, edx register (AMD) are also 213 // available on Intel processors 214 #define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \ 215 | IA32_FEATURE_AMD_EXT_NX \ 216 | IA32_FEATURE_AMD_EXT_PDPE1GB \ 217 | IA32_FEATURE_AMD_EXT_RDTSCP \ 218 | IA32_FEATURE_AMD_EXT_LONG) 219 220 // x86 defined features from cpuid eax 5, ecx register 221 #define IA32_FEATURE_POWER_MWAIT (1 << 0) 222 #define IA32_FEATURE_INTERRUPT_MWAIT (1 << 1) 223 224 // x86 defined features from cpuid eax 6, eax register 225 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 226 #define IA32_FEATURE_DTS (1 << 0) // Digital Thermal Sensor 227 #define IA32_FEATURE_ITB (1 << 1) // Intel Turbo Boost Technology 228 #define IA32_FEATURE_ARAT (1 << 2) // Always running APIC Timer 229 #define IA32_FEATURE_PLN (1 << 4) // Power Limit Notification 230 #define IA32_FEATURE_ECMD (1 << 5) // Extended Clock Modulation Duty 231 #define IA32_FEATURE_PTM (1 << 6) // Package Thermal Management 232 233 // x86 defined features from cpuid eax 6, ecx register 234 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 235 #define IA32_FEATURE_APERFMPERF (1 << 0) // IA32_APERF, IA32_MPERF 236 #define IA32_FEATURE_EPB (1 << 3) // IA32_ENERGY_PERF_BIAS 237 238 // x86 features from cpuid eax 7, ebx register 239 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 240 #define IA32_FEATURE_TSC_ADJUST (1 << 1) // IA32_TSC_ADJUST MSR supported 241 #define IA32_FEATURE_SGX (1 << 2) // Software Guard Extensions 242 #define IA32_FEATURE_BMI1 (1 << 3) // Bit Manipulation Instruction Set 1 243 #define IA32_FEATURE_HLE (1 << 4) // Hardware Lock Elision 244 #define IA32_FEATURE_AVX2 (1 << 5) // Advanced Vector Extensions 2 245 #define IA32_FEATURE_SMEP (1 << 7) // Supervisor-Mode Execution Prevention 246 #define IA32_FEATURE_BMI2 (1 << 8) // Bit Manipulation Instruction Set 2 247 #define IA32_FEATURE_ERMS (1 << 9) // Enhanced REP MOVSB/STOSB 248 #define IA32_FEATURE_INVPCID (1 << 10) // INVPCID instruction 249 #define IA32_FEATURE_RTM (1 << 11) // Transactional Synchronization Extensions 250 #define IA32_FEATURE_CQM (1 << 12) // Platform Quality of Service Monitoring 251 #define IA32_FEATURE_MPX (1 << 14) // Memory Protection Extensions 252 #define IA32_FEATURE_RDT_A (1 << 15) // Resource Director Technology Allocation 253 #define IA32_FEATURE_AVX512F (1 << 16) // AVX-512 Foundation 254 #define IA32_FEATURE_AVX512DQ (1 << 17) // AVX-512 Doubleword and Quadword Instructions 255 #define IA32_FEATURE_RDSEED (1 << 18) // RDSEED instruction 256 #define IA32_FEATURE_ADX (1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions) 257 #define IA32_FEATURE_SMAP (1 << 20) // Supervisor Mode Access Prevention 258 #define IA32_FEATURE_AVX512IFMA (1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions 259 #define IA32_FEATURE_PCOMMIT (1 << 22) // PCOMMIT instruction 260 #define IA32_FEATURE_CLFLUSHOPT (1 << 23) // CLFLUSHOPT instruction 261 #define IA32_FEATURE_CLWB (1 << 24) // CLWB instruction 262 #define IA32_FEATURE_INTEL_PT (1 << 25) // Intel Processor Trace 263 #define IA32_FEATURE_AVX512PF (1 << 26) // AVX-512 Prefetch Instructions 264 #define IA32_FEATURE_AVX512ER (1 << 27) // AVX-512 Exponential and Reciprocal Instructions 265 #define IA32_FEATURE_AVX512CD (1 << 28) // AVX-512 Conflict Detection Instructions 266 #define IA32_FEATURE_SHA_NI (1 << 29) // SHA extensions 267 #define IA32_FEATURE_AVX512BW (1 << 30) // AVX-512 Byte and Word Instructions 268 #define IA32_FEATURE_AVX512VI (1 << 31) // AVX-512 Vector Length Extensions 269 270 // x86 features from cpuid eax 7, ecx register 271 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 272 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 273 #define IA32_FEATURE_AVX512VMBI (1 << 1) // AVX-512 Vector Bit Manipulation Instructions 274 #define IA32_FEATURE_UMIP (1 << 2) // User-mode Instruction Prevention 275 #define IA32_FEATURE_PKU (1 << 3) // Memory Protection Keys for User-mode pages 276 #define IA32_FEATURE_OSPKE (1 << 4) // PKU enabled by OS 277 #define IA32_FEATURE_AVX512VMBI2 (1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2 278 #define IA32_FEATURE_GFNI (1 << 8) // Galois Field instructions 279 #define IA32_FEATURE_VAES (1 << 9) // AES instruction set (VEX-256/EVEX) 280 #define IA32_FEATURE_VPCLMULQDQ (1 << 10) // CLMUL instruction set (VEX-256/EVEX) 281 #define IA32_FEATURE_AVX512_VNNI (1 << 11) // AVX-512 Vector Neural Network Instructions 282 #define IA32_FEATURE_AVX512_BITALG (1 << 12) // AVX-512 BITALG instructions 283 #define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q 284 #define IA32_FEATURE_LA57 (1 << 16) // 5-level page tables 285 #define IA32_FEATURE_RDPID (1 << 22) // RDPID Instruction 286 #define IA32_FEATURE_SGX_LC (1 << 30) // SGX Launch Configuration 287 288 // x86 features from cpuid eax 7, edx register 289 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 290 #define IA32_FEATURE_AVX512_4VNNIW (1 << 2) // AVX-512 4-register Neural Network Instructions 291 #define IA32_FEATURE_AVX512_4FMAPS (1 << 3) // AVX-512 4-register Multiply Accumulation Single precision 292 #define IA32_FEATURE_IBRS (1 << 26) // IBRS / IBPB Speculation Control 293 #define IA32_FEATURE_STIBP (1 << 27) // STIBP Speculation Control 294 #define IA32_FEATURE_L1D_FLUSH (1 << 28) // L1D_FLUSH supported 295 #define IA32_FEATURE_ARCH_CAPABILITIES (1 << 29) // IA32_ARCH_CAPABILITIES MSR 296 #define IA32_FEATURE_SSBD (1 << 31) // Speculative Store Bypass Disable 297 298 // x86 features from cpuid eax 0xd, ecx 1, eax register 299 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 300 #define IA32_FEATURE_XSAVEOPT (1 << 0) // XSAVEOPT Instruction 301 #define IA32_FEATURE_XSAVEC (1 << 1) // XSAVEC and compacted XRSTOR 302 #define IA32_FEATURE_XGETBV1 (1 << 2) // XGETBV with ECX=1 Instruction 303 #define IA32_FEATURE_XSAVES (1 << 3) // XSAVES and XRSTORS Instruction 304 305 // x86 defined features from cpuid eax 0x80000007, edx register 306 #define IA32_FEATURE_INVARIANT_TSC (1 << 8) 307 308 // x86 defined features from cpuid eax 0x80000008, ebx register 309 #define IA32_FEATURE_CLZERO (1 << 0) // CLZERO instruction 310 #define IA32_FEATURE_IBPB (1 << 12) // IBPB Support only (no IBRS) 311 #define IA32_FEATURE_AMD_SSBD (1 << 24) // Speculative Store Bypass Disable 312 #define IA32_FEATURE_VIRT_SSBD (1 << 25) // Virtualized Speculative Store Bypass Disable 313 #define IA32_FEATURE_AMD_SSB_NO (1 << 26) // Speculative Store Bypass is fixed in hardware 314 315 316 // Memory type ranges 317 #define IA32_MTR_UNCACHED 0 318 #define IA32_MTR_WRITE_COMBINING 1 319 #define IA32_MTR_WRITE_THROUGH 4 320 #define IA32_MTR_WRITE_PROTECTED 5 321 #define IA32_MTR_WRITE_BACK 6 322 323 // EFLAGS register 324 #define X86_EFLAGS_CARRY 0x00000001 325 #define X86_EFLAGS_RESERVED1 0x00000002 326 #define X86_EFLAGS_PARITY 0x00000004 327 #define X86_EFLAGS_AUXILIARY_CARRY 0x00000010 328 #define X86_EFLAGS_ZERO 0x00000040 329 #define X86_EFLAGS_SIGN 0x00000080 330 #define X86_EFLAGS_TRAP 0x00000100 331 #define X86_EFLAGS_INTERRUPT 0x00000200 332 #define X86_EFLAGS_DIRECTION 0x00000400 333 #define X86_EFLAGS_OVERFLOW 0x00000800 334 #define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000 335 #define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12 336 #define X86_EFLAGS_NESTED_TASK 0x00004000 337 #define X86_EFLAGS_RESUME 0x00010000 338 #define X86_EFLAGS_V86_MODE 0x00020000 339 #define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000 // also SMAP status 340 #define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000 341 #define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000 342 #define X86_EFLAGS_ID 0x00200000 343 344 #define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \ 345 | X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \ 346 | X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW) 347 348 #define CR0_CACHE_DISABLE (1UL << 30) 349 #define CR0_NOT_WRITE_THROUGH (1UL << 29) 350 #define CR0_FPU_EMULATION (1UL << 2) 351 #define CR0_MONITOR_FPU (1UL << 1) 352 353 // cr4 flags 354 #define IA32_CR4_PAE (1UL << 5) 355 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 356 #define CR4_OS_FXSR (1UL << 9) 357 #define CR4_OS_XMM_EXCEPTION (1UL << 10) 358 #define IA32_CR4_OSXSAVE (1UL << 18) 359 #define IA32_CR4_SMEP (1UL << 20) 360 #define IA32_CR4_SMAP (1UL << 21) 361 362 // Extended Control Register XCR0 flags 363 #define IA32_XCR0_X87 (1UL << 0) 364 #define IA32_XCR0_SSE (1UL << 1) 365 #define IA32_XCR0_AVX (1UL << 2) 366 367 // page fault error codes (http://wiki.osdev.org/Page_Fault) 368 #define PGFAULT_P 0x01 // Protection violation 369 #define PGFAULT_W 0x02 // Write 370 #define PGFAULT_U 0x04 // Usermode 371 #define PGFAULT_RSVD 0x08 // Reserved bits 372 #define PGFAULT_I 0x10 // Instruction fetch 373 374 // iframe types 375 #define IFRAME_TYPE_SYSCALL 0x1 376 #define IFRAME_TYPE_OTHER 0x2 377 #define IFRAME_TYPE_MASK 0xf 378 379 380 #ifndef _ASSEMBLER 381 382 383 struct X86PagingStructures; 384 385 386 typedef struct x86_mtrr_info { 387 uint64 base; 388 uint64 size; 389 uint8 type; 390 } x86_mtrr_info; 391 392 typedef struct x86_cpu_module_info { 393 module_info info; 394 uint32 (*count_mtrrs)(void); 395 void (*init_mtrrs)(void); 396 397 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 398 uint8 type); 399 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 400 uint8* _type); 401 void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos, 402 uint32 count); 403 } x86_cpu_module_info; 404 405 // features 406 enum x86_feature_type { 407 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 408 FEATURE_EXT, // cpuid eax=1, edx register 409 FEATURE_EXT_AMD_ECX, // cpuid eax=0x80000001, ecx register (AMD) 410 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 411 FEATURE_5_ECX, // cpuid eax=5, ecx register 412 FEATURE_6_EAX, // cpuid eax=6, eax registers 413 FEATURE_6_ECX, // cpuid eax=6, ecx registers 414 FEATURE_7_EBX, // cpuid eax=7, ebx registers 415 FEATURE_7_ECX, // cpuid eax=7, ecx registers 416 FEATURE_7_EDX, // cpuid eax=7, edx registers 417 FEATURE_EXT_7_EDX, // cpuid eax=0x80000007, edx register 418 FEATURE_EXT_8_EBX, // cpuid eax=0x80000008, ebx register 419 FEATURE_D_1_EAX, // cpuid eax=0xd, ecx=1, eax register 420 421 FEATURE_NUM 422 }; 423 424 enum x86_vendors { 425 VENDOR_INTEL = 0, 426 VENDOR_AMD, 427 VENDOR_CYRIX, 428 VENDOR_UMC, 429 VENDOR_NEXGEN, 430 VENDOR_CENTAUR, 431 VENDOR_RISE, 432 VENDOR_TRANSMETA, 433 VENDOR_NSC, 434 435 VENDOR_NUM, 436 VENDOR_UNKNOWN, 437 }; 438 439 440 typedef struct arch_cpu_info { 441 // saved cpu info 442 enum x86_vendors vendor; 443 uint32 feature[FEATURE_NUM]; 444 char model_name[49]; 445 const char* vendor_name; 446 int type; 447 int family; 448 int extended_family; 449 int stepping; 450 int model; 451 int extended_model; 452 uint32 patch_level; 453 454 uint32 logical_apic_id; 455 456 struct X86PagingStructures* active_paging_structures; 457 458 size_t dr6; // temporary storage for debug registers (cf. 459 size_t dr7; // x86_exit_user_debug_at_kernel_entry()) 460 461 // local TSS for this cpu 462 struct tss tss; 463 #ifndef __x86_64__ 464 struct tss double_fault_tss; 465 void* kernel_tls; 466 #endif 467 } arch_cpu_info; 468 469 470 // Reference Intel SDM Volume 3 9.11 "Microcode Update Facilities" 471 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 472 // 9.11.1 Table 9-7. Microcode Update Field Definitions 473 struct intel_microcode_header { 474 uint32 header_version; 475 uint32 update_revision; 476 uint32 date; 477 uint32 processor_signature; 478 uint32 checksum; 479 uint32 loader_revision; 480 uint32 processor_flags; 481 uint32 data_size; 482 uint32 total_size; 483 uint32 reserved[3]; 484 }; 485 486 487 struct intel_microcode_extended_signature_header { 488 uint32 extended_signature_count; 489 uint32 extended_checksum; 490 uint32 reserved[3]; 491 }; 492 493 494 struct intel_microcode_extended_signature { 495 uint32 processor_signature; 496 uint32 processor_flags; 497 uint32 checksum; 498 }; 499 500 501 extern void (*gCpuIdleFunc)(void); 502 503 504 #ifdef __cplusplus 505 extern "C" { 506 #endif 507 508 struct arch_thread; 509 510 #ifdef __x86_64__ 511 void __x86_setup_system_time(uint64 conversionFactor, 512 uint64 conversionFactorNsecs); 513 #else 514 void __x86_setup_system_time(uint32 conversionFactor, 515 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 516 #endif 517 518 status_t __x86_patch_errata_percpu(int cpu); 519 520 void x86_userspace_thread_exit(void); 521 void x86_end_userspace_thread_exit(void); 522 523 addr_t x86_get_stack_frame(); 524 uint32 x86_count_mtrrs(void); 525 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 526 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 527 uint8* _type); 528 void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, 529 uint32 count); 530 void x86_init_fpu(); 531 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 532 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 533 int32 x86_double_fault_get_cpu(void); 534 535 void x86_invalid_exception(iframe* frame); 536 void x86_fatal_exception(iframe* frame); 537 void x86_unexpected_exception(iframe* frame); 538 void x86_hardware_interrupt(iframe* frame); 539 void x86_page_fault_exception(iframe* iframe); 540 541 #ifndef __x86_64__ 542 543 void x86_swap_pgdir(addr_t newPageDir); 544 545 uint64 x86_read_msr(uint32 registerNumber); 546 void x86_write_msr(uint32 registerNumber, uint64 value); 547 548 void x86_context_switch(struct arch_thread* oldState, 549 struct arch_thread* newState); 550 551 void x86_fnsave(void* fpuState); 552 void x86_frstor(const void* fpuState); 553 554 void x86_fxsave(void* fpuState); 555 void x86_fxrstor(const void* fpuState); 556 557 void x86_noop_swap(void* oldFpuState, const void* newFpuState); 558 void x86_fnsave_swap(void* oldFpuState, const void* newFpuState); 559 void x86_fxsave_swap(void* oldFpuState, const void* newFpuState); 560 561 #endif 562 563 564 static inline void 565 arch_cpu_idle(void) 566 { 567 gCpuIdleFunc(); 568 } 569 570 571 static inline void 572 arch_cpu_pause(void) 573 { 574 asm volatile("pause" : : : "memory"); 575 } 576 577 578 #ifdef __cplusplus 579 } // extern "C" { 580 #endif 581 582 #endif // !_ASSEMBLER 583 584 #endif /* _KERNEL_ARCH_x86_CPU_H */ 585