1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 5 * Distributed under the terms of the MIT License. 6 * 7 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 8 * Distributed under the terms of the NewOS License. 9 */ 10 #ifndef _KERNEL_ARCH_x86_CPU_H 11 #define _KERNEL_ARCH_x86_CPU_H 12 13 14 #ifndef _ASSEMBLER 15 16 #include <module.h> 17 18 #include <arch_thread_types.h> 19 20 #include <arch/x86/arch_altcodepatch.h> 21 #include <arch/x86/arch_cpuasm.h> 22 #include <arch/x86/descriptors.h> 23 24 #ifdef __x86_64__ 25 # include <arch/x86/64/cpu.h> 26 #endif 27 28 #endif // !_ASSEMBLER 29 30 31 #define CPU_MAX_CACHE_LEVEL 8 32 33 #define CACHE_LINE_SIZE 64 34 35 36 // MSR registers (possibly Intel specific) 37 #define IA32_MSR_TSC 0x10 38 #define IA32_MSR_PLATFORM_ID 0x17 39 #define IA32_MSR_APIC_BASE 0x1b 40 #define IA32_MSR_SPEC_CTRL 0x48 41 #define IA32_MSR_PRED_CMD 0x49 42 #define IA32_MSR_UCODE_WRITE 0x79 // IA32_BIOS_UPDT_TRIG 43 #define IA32_MSR_UCODE_REV 0x8b // IA32_BIOS_SIGN_ID 44 #define IA32_MSR_PLATFORM_INFO 0xce 45 #define IA32_MSR_MPERF 0xe7 46 #define IA32_MSR_APERF 0xe8 47 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 48 #define IA32_MSR_ARCH_CAPABILITIES 0x10a 49 #define IA32_MSR_FLUSH_CMD 0x10b 50 #define IA32_MSR_SYSENTER_CS 0x174 51 #define IA32_MSR_SYSENTER_ESP 0x175 52 #define IA32_MSR_SYSENTER_EIP 0x176 53 #define IA32_MSR_PERF_STATUS 0x198 54 #define IA32_MSR_PERF_CTL 0x199 55 #define IA32_MSR_TURBO_RATIO_LIMIT 0x1ad 56 #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 57 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 58 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 59 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 60 61 // MSR SPEC CTRL bits 62 #define IA32_MSR_SPEC_CTRL_IBRS (1 << 0) 63 #define IA32_MSR_SPEC_CTRL_STIBP (1 << 1) 64 #define IA32_MSR_SPEC_CTRL_SSBD (1 << 2) 65 66 // MSR PRED CMD bits 67 #define IA32_MSR_PRED_CMD_IBPB (1 << 0) 68 69 // MSR APIC BASE bits 70 #define IA32_MSR_APIC_BASE_BSP 0x00000100 71 #define IA32_MSR_APIC_BASE_X2APIC 0x00000400 72 #define IA32_MSR_APIC_BASE_ENABLED 0x00000800 73 #define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000 74 75 // MSR EFER bits 76 // reference 77 #define IA32_MSR_EFER_SYSCALL (1 << 0) 78 #define IA32_MSR_EFER_NX (1 << 11) 79 80 // MSR ARCH CAPABILITIES bits 81 #define IA32_MSR_ARCH_CAP_RDCL_NO (1 << 0) 82 #define IA32_MSR_ARCH_CAP_IBRS_ALL (1 << 1) 83 #define IA32_MSR_ARCH_CAP_RSBA (1 << 2) 84 #define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY (1 << 3) 85 #define IA32_MSR_ARCH_CAP_SSB_NO (1 << 4) 86 87 // MSR FLUSH CMD bits 88 #define IA32_MSR_L1D_FLUSH (1 << 1) 89 90 // X2APIC MSRs. 91 #define IA32_MSR_APIC_ID 0x00000802 92 #define IA32_MSR_APIC_VERSION 0x00000803 93 #define IA32_MSR_APIC_TASK_PRIORITY 0x00000808 94 #define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a 95 #define IA32_MSR_APIC_EOI 0x0000080b 96 #define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d 97 #define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f 98 #define IA32_MSR_APIC_ERROR_STATUS 0x00000828 99 #define IA32_MSR_APIC_INTR_COMMAND 0x00000830 100 #define IA32_MSR_APIC_LVT_TIMER 0x00000832 101 #define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833 102 #define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834 103 #define IA32_MSR_APIC_LVT_LINT0 0x00000835 104 #define IA32_MSR_APIC_LVT_LINT1 0x00000836 105 #define IA32_MSR_APIC_LVT_ERROR 0x00000837 106 #define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838 107 #define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839 108 #define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e 109 #define IA32_MSR_APIC_SELF_IPI 0x0000083f 110 #define IA32_MSR_XSS 0x00000da0 111 112 // x86_64 MSRs. 113 #define IA32_MSR_EFER 0xc0000080 114 #define IA32_MSR_STAR 0xc0000081 115 #define IA32_MSR_LSTAR 0xc0000082 116 #define IA32_MSR_CSTAR 0xc0000083 117 #define IA32_MSR_FMASK 0xc0000084 118 #define IA32_MSR_FS_BASE 0xc0000100 119 #define IA32_MSR_GS_BASE 0xc0000101 120 #define IA32_MSR_KERNEL_GS_BASE 0xc0000102 121 #define IA32_MSR_TSC_AUX 0xc0000103 122 123 // K8 MSR registers 124 #define K8_MSR_IPM 0xc0010055 125 #define MSR_F10H_DE_CFG 0xc0011029 126 #define DE_CFG_SERIALIZE_LFENCE (1 << 1) 127 128 129 // Hardware P-States MSR registers §14.4.1 130 // reference https://software.intel.com/content/dam/develop/public/us/en/documents/253669-sdm-vol-3b.pdf 131 #define IA32_MSR_PM_ENABLE 0x00000770 132 #define IA32_MSR_HWP_CAPABILITIES 0x00000771 133 #define IA32_MSR_HWP_REQUEST_PKG 0x00000772 134 #define IA32_MSR_HWP_INTERRUPT 0x00000773 135 #define IA32_MSR_HWP_REQUEST 0x00000774 136 #define IA32_MSR_HWP_STATUS 0x00000777 137 138 // IA32_MSR_HWP_CAPABILITIES bits §14.4.3 139 #define IA32_HWP_CAPS_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 140 #define IA32_HWP_CAPS_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 141 #define IA32_HWP_CAPS_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 142 #define IA32_HWP_CAPS_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 143 144 // IA32_MSR_HWP_REQUEST bits §14.4.4.1 145 #define IA32_HWP_REQUEST_MINIMUM_PERFORMANCE (0xffULL << 0) 146 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 147 #define IA32_HWP_REQUEST_DESIRED_PERFORMANCE (0xffULL << 16) 148 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 149 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW (0x3ffULL << 32) 150 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 151 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 152 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 153 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 154 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 155 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 156 157 // x86 features from cpuid eax 1, edx register 158 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5) 159 #define IA32_FEATURE_FPU (1 << 0) // x87 fpu 160 #define IA32_FEATURE_VME (1 << 1) // virtual 8086 161 #define IA32_FEATURE_DE (1 << 2) // debugging extensions 162 #define IA32_FEATURE_PSE (1 << 3) // page size extensions 163 #define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction 164 #define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction 165 #define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing 166 #define IA32_FEATURE_MCE (1 << 7) // machine check exception 167 #define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction 168 #define IA32_FEATURE_APIC (1 << 9) // local apic on chip 169 // (1 << 10) // Reserved 170 #define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT 171 #define IA32_FEATURE_MTRR (1 << 12) // MTRR 172 #define IA32_FEATURE_PGE (1 << 13) // paging global bit 173 #define IA32_FEATURE_MCA (1 << 14) // machine check architecture 174 #define IA32_FEATURE_CMOV (1 << 15) // cmov instruction 175 #define IA32_FEATURE_PAT (1 << 16) // page attribute table 176 #define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages 177 #define IA32_FEATURE_PSN (1 << 18) // processor serial number 178 #define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction 179 // (1 << 20) // Reserved 180 #define IA32_FEATURE_DS (1 << 21) // debug store 181 #define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl 182 #define IA32_FEATURE_MMX (1 << 23) // mmx instructions 183 #define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction 184 #define IA32_FEATURE_SSE (1 << 25) // SSE 185 #define IA32_FEATURE_SSE2 (1 << 26) // SSE2 186 #define IA32_FEATURE_SS (1 << 27) // self snoop 187 #define IA32_FEATURE_HTT (1 << 28) // hyperthreading 188 #define IA32_FEATURE_TM (1 << 29) // thermal monitor 189 #define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86 190 #define IA32_FEATURE_PBE (1 << 31) // pending break enable 191 192 // x86 features from cpuid eax 1, ecx register 193 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4) 194 #define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3 195 #define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction 196 #define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store 197 #define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT 198 #define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store 199 #define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions 200 #define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions 201 #define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep 202 #define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2 203 #define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3 204 #define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID 205 // (1 << 11) // Reserved 206 #define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add 207 #define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B 208 #define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control 209 #define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability 210 // (1 << 16) // Reserved 211 #define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers 212 #define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access 213 #define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1 214 #define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2 215 #define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support 216 #define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction 217 #define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction 218 #define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline 219 #define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions 220 #define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States 221 #define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE 222 #define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions 223 #define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion 224 #define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction 225 #define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor 226 227 // x86 features from cpuid eax 0x80000001, ecx register (AMD) 228 #define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode 229 #define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions 230 231 // x86 features from cpuid eax 0x80000001, edx register (AMD) 232 // only care about the ones that are unique to this register 233 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 234 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 235 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 236 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 237 #define IA32_FEATURE_AMD_EXT_PDPE1GB (1 << 26) // Gibibyte pages 238 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 239 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 240 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 241 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 242 243 // some of the features from cpuid eax 0x80000001, edx register (AMD) are also 244 // available on Intel processors 245 #define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \ 246 | IA32_FEATURE_AMD_EXT_NX \ 247 | IA32_FEATURE_AMD_EXT_PDPE1GB \ 248 | IA32_FEATURE_AMD_EXT_RDTSCP \ 249 | IA32_FEATURE_AMD_EXT_LONG) 250 251 // x86 defined features from cpuid eax 5, ecx register 252 #define IA32_FEATURE_POWER_MWAIT (1 << 0) 253 #define IA32_FEATURE_INTERRUPT_MWAIT (1 << 1) 254 255 // x86 defined features from cpuid eax 6, eax register 256 // reference https://software.intel.com/content/dam/develop/public/us/en/documents/253666-sdm-vol-2a.pdf (Table 3-8) 257 #define IA32_FEATURE_DTS (1 << 0) // Digital Thermal Sensor 258 #define IA32_FEATURE_ITB (1 << 1) // Intel Turbo Boost Technology 259 #define IA32_FEATURE_ARAT (1 << 2) // Always running APIC Timer 260 #define IA32_FEATURE_PLN (1 << 4) // Power Limit Notification 261 #define IA32_FEATURE_ECMD (1 << 5) // Extended Clock Modulation Duty 262 #define IA32_FEATURE_PTM (1 << 6) // Package Thermal Management 263 #define IA32_FEATURE_HWP (1 << 7) // Hardware P-states 264 #define IA32_FEATURE_HWP_NOTIFY (1 << 8) // HWP Notification 265 #define IA32_FEATURE_HWP_ACTWIN (1 << 9) // HWP Activity Window 266 #define IA32_FEATURE_HWP_EPP (1 << 10) // HWP Energy Performance Preference 267 #define IA32_FEATURE_HWP_PLR (1 << 11) // HWP Package Level Request 268 #define IA32_FEATURE_HDC (1 << 13) // Hardware Duty Cycling 269 #define IA32_FEATURE_TBMT3 (1 << 14) // Turbo Boost Max Technology 3.0 270 #define IA32_FEATURE_HWP_CAP (1 << 15) // HWP Capabilities 271 #define IA32_FEATURE_HWP_PECI (1 << 16) // HWP PECI override 272 #define IA32_FEATURE_HWP_FLEX (1 << 17) // Flexible HWP 273 #define IA32_FEATURE_HWP_FAST (1 << 18) // Fast access for HWP_REQUEST MSR 274 #define IA32_FEATURE_HW_FEEDBACK (1 << 19) // HW_FEEDBACK*, PACKAGE_THERM* 275 #define IA32_FEATURE_HWP_IGNIDL (1 << 20) // Ignore Idle Logical Processor HWP 276 277 // x86 defined features from cpuid eax 6, ecx register 278 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 279 #define IA32_FEATURE_APERFMPERF (1 << 0) // IA32_APERF, IA32_MPERF 280 #define IA32_FEATURE_EPB (1 << 3) // IA32_ENERGY_PERF_BIAS 281 282 // x86 features from cpuid eax 7, ebx register 283 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 284 #define IA32_FEATURE_TSC_ADJUST (1 << 1) // IA32_TSC_ADJUST MSR supported 285 #define IA32_FEATURE_SGX (1 << 2) // Software Guard Extensions 286 #define IA32_FEATURE_BMI1 (1 << 3) // Bit Manipulation Instruction Set 1 287 #define IA32_FEATURE_HLE (1 << 4) // Hardware Lock Elision 288 #define IA32_FEATURE_AVX2 (1 << 5) // Advanced Vector Extensions 2 289 #define IA32_FEATURE_SMEP (1 << 7) // Supervisor-Mode Execution Prevention 290 #define IA32_FEATURE_BMI2 (1 << 8) // Bit Manipulation Instruction Set 2 291 #define IA32_FEATURE_ERMS (1 << 9) // Enhanced REP MOVSB/STOSB 292 #define IA32_FEATURE_INVPCID (1 << 10) // INVPCID instruction 293 #define IA32_FEATURE_RTM (1 << 11) // Transactional Synchronization Extensions 294 #define IA32_FEATURE_CQM (1 << 12) // Platform Quality of Service Monitoring 295 #define IA32_FEATURE_MPX (1 << 14) // Memory Protection Extensions 296 #define IA32_FEATURE_RDT_A (1 << 15) // Resource Director Technology Allocation 297 #define IA32_FEATURE_AVX512F (1 << 16) // AVX-512 Foundation 298 #define IA32_FEATURE_AVX512DQ (1 << 17) // AVX-512 Doubleword and Quadword Instructions 299 #define IA32_FEATURE_RDSEED (1 << 18) // RDSEED instruction 300 #define IA32_FEATURE_ADX (1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions) 301 #define IA32_FEATURE_SMAP (1 << 20) // Supervisor Mode Access Prevention 302 #define IA32_FEATURE_AVX512IFMA (1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions 303 #define IA32_FEATURE_PCOMMIT (1 << 22) // PCOMMIT instruction 304 #define IA32_FEATURE_CLFLUSHOPT (1 << 23) // CLFLUSHOPT instruction 305 #define IA32_FEATURE_CLWB (1 << 24) // CLWB instruction 306 #define IA32_FEATURE_INTEL_PT (1 << 25) // Intel Processor Trace 307 #define IA32_FEATURE_AVX512PF (1 << 26) // AVX-512 Prefetch Instructions 308 #define IA32_FEATURE_AVX512ER (1 << 27) // AVX-512 Exponential and Reciprocal Instructions 309 #define IA32_FEATURE_AVX512CD (1 << 28) // AVX-512 Conflict Detection Instructions 310 #define IA32_FEATURE_SHA_NI (1 << 29) // SHA extensions 311 #define IA32_FEATURE_AVX512BW (1 << 30) // AVX-512 Byte and Word Instructions 312 #define IA32_FEATURE_AVX512VI (1 << 31) // AVX-512 Vector Length Extensions 313 314 // x86 features from cpuid eax 7, ecx register 315 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 316 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 317 #define IA32_FEATURE_AVX512VMBI (1 << 1) // AVX-512 Vector Bit Manipulation Instructions 318 #define IA32_FEATURE_UMIP (1 << 2) // User-mode Instruction Prevention 319 #define IA32_FEATURE_PKU (1 << 3) // Memory Protection Keys for User-mode pages 320 #define IA32_FEATURE_OSPKE (1 << 4) // PKU enabled by OS 321 #define IA32_FEATURE_AVX512VMBI2 (1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2 322 #define IA32_FEATURE_GFNI (1 << 8) // Galois Field instructions 323 #define IA32_FEATURE_VAES (1 << 9) // AES instruction set (VEX-256/EVEX) 324 #define IA32_FEATURE_VPCLMULQDQ (1 << 10) // CLMUL instruction set (VEX-256/EVEX) 325 #define IA32_FEATURE_AVX512_VNNI (1 << 11) // AVX-512 Vector Neural Network Instructions 326 #define IA32_FEATURE_AVX512_BITALG (1 << 12) // AVX-512 BITALG instructions 327 #define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q 328 #define IA32_FEATURE_LA57 (1 << 16) // 5-level page tables 329 #define IA32_FEATURE_RDPID (1 << 22) // RDPID Instruction 330 #define IA32_FEATURE_SGX_LC (1 << 30) // SGX Launch Configuration 331 332 // x86 features from cpuid eax 7, edx register 333 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 334 #define IA32_FEATURE_AVX512_4VNNIW (1 << 2) // AVX-512 4-register Neural Network Instructions 335 #define IA32_FEATURE_AVX512_4FMAPS (1 << 3) // AVX-512 4-register Multiply Accumulation Single precision 336 #define IA32_FEATURE_IBRS (1 << 26) // IBRS / IBPB Speculation Control 337 #define IA32_FEATURE_STIBP (1 << 27) // STIBP Speculation Control 338 #define IA32_FEATURE_L1D_FLUSH (1 << 28) // L1D_FLUSH supported 339 #define IA32_FEATURE_ARCH_CAPABILITIES (1 << 29) // IA32_ARCH_CAPABILITIES MSR 340 #define IA32_FEATURE_SSBD (1 << 31) // Speculative Store Bypass Disable 341 342 // x86 features from cpuid eax 0xd, ecx 1, eax register 343 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 344 #define IA32_FEATURE_XSAVEOPT (1 << 0) // XSAVEOPT Instruction 345 #define IA32_FEATURE_XSAVEC (1 << 1) // XSAVEC and compacted XRSTOR 346 #define IA32_FEATURE_XGETBV1 (1 << 2) // XGETBV with ECX=1 Instruction 347 #define IA32_FEATURE_XSAVES (1 << 3) // XSAVES and XRSTORS Instruction 348 349 // x86 defined features from cpuid eax 0x80000007, edx register 350 #define IA32_FEATURE_INVARIANT_TSC (1 << 8) 351 352 // x86 defined features from cpuid eax 0x80000008, ebx register 353 #define IA32_FEATURE_CLZERO (1 << 0) // CLZERO instruction 354 #define IA32_FEATURE_IBPB (1 << 12) // IBPB Support only (no IBRS) 355 #define IA32_FEATURE_AMD_SSBD (1 << 24) // Speculative Store Bypass Disable 356 #define IA32_FEATURE_VIRT_SSBD (1 << 25) // Virtualized Speculative Store Bypass Disable 357 #define IA32_FEATURE_AMD_SSB_NO (1 << 26) // Speculative Store Bypass is fixed in hardware 358 359 360 // Memory type ranges 361 #define IA32_MTR_UNCACHED 0 362 #define IA32_MTR_WRITE_COMBINING 1 363 #define IA32_MTR_WRITE_THROUGH 4 364 #define IA32_MTR_WRITE_PROTECTED 5 365 #define IA32_MTR_WRITE_BACK 6 366 367 // EFLAGS register 368 #define X86_EFLAGS_CARRY 0x00000001 369 #define X86_EFLAGS_RESERVED1 0x00000002 370 #define X86_EFLAGS_PARITY 0x00000004 371 #define X86_EFLAGS_AUXILIARY_CARRY 0x00000010 372 #define X86_EFLAGS_ZERO 0x00000040 373 #define X86_EFLAGS_SIGN 0x00000080 374 #define X86_EFLAGS_TRAP 0x00000100 375 #define X86_EFLAGS_INTERRUPT 0x00000200 376 #define X86_EFLAGS_DIRECTION 0x00000400 377 #define X86_EFLAGS_OVERFLOW 0x00000800 378 #define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000 379 #define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12 380 #define X86_EFLAGS_NESTED_TASK 0x00004000 381 #define X86_EFLAGS_RESUME 0x00010000 382 #define X86_EFLAGS_V86_MODE 0x00020000 383 #define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000 // also SMAP status 384 #define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000 385 #define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000 386 #define X86_EFLAGS_ID 0x00200000 387 388 #define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \ 389 | X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \ 390 | X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW) 391 392 #define CR0_CACHE_DISABLE (1UL << 30) 393 #define CR0_NOT_WRITE_THROUGH (1UL << 29) 394 #define CR0_FPU_EMULATION (1UL << 2) 395 #define CR0_MONITOR_FPU (1UL << 1) 396 397 // Control Register CR4 flags §2.5 398 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 399 #define IA32_CR4_VME (1UL << 0) 400 #define IA32_CR4_PVI (1UL << 1) 401 #define IA32_CR4_TSD (1UL << 2) 402 #define IA32_CR4_DE (1UL << 3) 403 #define IA32_CR4_PSE (1UL << 4) 404 #define IA32_CR4_PAE (1UL << 5) 405 #define IA32_CR4_MCE (1UL << 6) 406 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 407 #define IA32_CR4_PCE (1UL << 8) 408 #define CR4_OS_FXSR (1UL << 9) 409 #define CR4_OS_XMM_EXCEPTION (1UL << 10) 410 #define IA32_CR4_UMIP (1UL << 11) 411 #define IA32_CR4_LA57 (1UL << 12) 412 #define IA32_CR4_VMXE (1UL << 13) 413 #define IA32_CR4_SMXE (1UL << 14) 414 #define IA32_CR4_FSGSBASE (1UL << 16) 415 #define IA32_CR4_PCIDE (1UL << 17) 416 #define IA32_CR4_OSXSAVE (1UL << 18) 417 #define IA32_CR4_SMEP (1UL << 20) 418 #define IA32_CR4_SMAP (1UL << 21) 419 #define IA32_CR4_PKE (1UL << 22) 420 421 // Extended Control Register XCR0 flags §13.3 422 // https://software.intel.com/content/dam/develop/public/us/en/documents/253665-sdm-vol-1.pdf 423 #define IA32_XCR0_X87 (1UL << 0) 424 #define IA32_XCR0_SSE (1UL << 1) 425 #define IA32_XCR0_AVX (1UL << 2) 426 #define IA32_XCR0_BNDREG (1UL << 3) 427 #define IA32_XCR0_BNDCSR (1UL << 4) 428 #define IA32_XCR0_OPMASK (1UL << 5) 429 #define IA32_XCR0_ZMM_HI256 (1UL << 6) 430 #define IA32_XCR0_HI16_ZMM (1UL << 7) 431 #define IA32_XCR0_PT (1UL << 8) 432 #define IA32_XCR0_PKRU (1UL << 9) 433 434 // page fault error codes (http://wiki.osdev.org/Page_Fault) 435 #define PGFAULT_P 0x01 // Protection violation 436 #define PGFAULT_W 0x02 // Write 437 #define PGFAULT_U 0x04 // Usermode 438 #define PGFAULT_RSVD 0x08 // Reserved bits 439 #define PGFAULT_I 0x10 // Instruction fetch 440 441 // iframe types 442 #define IFRAME_TYPE_SYSCALL 0x1 443 #define IFRAME_TYPE_OTHER 0x2 444 #define IFRAME_TYPE_MASK 0xf 445 446 447 #ifndef _ASSEMBLER 448 449 450 struct X86PagingStructures; 451 452 453 typedef struct x86_mtrr_info { 454 uint64 base; 455 uint64 size; 456 uint8 type; 457 } x86_mtrr_info; 458 459 typedef struct x86_cpu_module_info { 460 module_info info; 461 uint32 (*count_mtrrs)(void); 462 void (*init_mtrrs)(void); 463 464 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 465 uint8 type); 466 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 467 uint8* _type); 468 void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos, 469 uint32 count); 470 } x86_cpu_module_info; 471 472 // features 473 enum x86_feature_type { 474 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 475 FEATURE_EXT, // cpuid eax=1, edx register 476 FEATURE_EXT_AMD_ECX, // cpuid eax=0x80000001, ecx register (AMD) 477 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 478 FEATURE_5_ECX, // cpuid eax=5, ecx register 479 FEATURE_6_EAX, // cpuid eax=6, eax registers 480 FEATURE_6_ECX, // cpuid eax=6, ecx registers 481 FEATURE_7_EBX, // cpuid eax=7, ebx registers 482 FEATURE_7_ECX, // cpuid eax=7, ecx registers 483 FEATURE_7_EDX, // cpuid eax=7, edx registers 484 FEATURE_EXT_7_EDX, // cpuid eax=0x80000007, edx register 485 FEATURE_EXT_8_EBX, // cpuid eax=0x80000008, ebx register 486 FEATURE_D_1_EAX, // cpuid eax=0xd, ecx=1, eax register 487 488 FEATURE_NUM 489 }; 490 491 enum x86_vendors { 492 VENDOR_INTEL = 0, 493 VENDOR_AMD, 494 VENDOR_CYRIX, 495 VENDOR_UMC, 496 VENDOR_NEXGEN, 497 VENDOR_CENTAUR, 498 VENDOR_RISE, 499 VENDOR_TRANSMETA, 500 VENDOR_NSC, 501 VENDOR_HYGON, 502 503 VENDOR_NUM, 504 VENDOR_UNKNOWN, 505 }; 506 507 508 typedef struct arch_cpu_info { 509 // saved cpu info 510 enum x86_vendors vendor; 511 uint32 feature[FEATURE_NUM]; 512 char model_name[49]; 513 const char* vendor_name; 514 int type; 515 int family; 516 int extended_family; 517 int stepping; 518 int model; 519 int extended_model; 520 uint32 patch_level; 521 522 uint32 logical_apic_id; 523 524 uint64 mperf_prev; 525 uint64 aperf_prev; 526 bigtime_t perf_timestamp; 527 uint64 frequency; 528 529 struct X86PagingStructures* active_paging_structures; 530 531 size_t dr6; // temporary storage for debug registers (cf. 532 size_t dr7; // x86_exit_user_debug_at_kernel_entry()) 533 534 // local TSS for this cpu 535 struct tss tss; 536 #ifndef __x86_64__ 537 struct tss double_fault_tss; 538 void* kernel_tls; 539 #endif 540 } arch_cpu_info; 541 542 543 // Reference Intel SDM Volume 3 9.11 "Microcode Update Facilities" 544 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 545 // 9.11.1 Table 9-7. Microcode Update Field Definitions 546 struct intel_microcode_header { 547 uint32 header_version; 548 uint32 update_revision; 549 uint32 date; 550 uint32 processor_signature; 551 uint32 checksum; 552 uint32 loader_revision; 553 uint32 processor_flags; 554 uint32 data_size; 555 uint32 total_size; 556 uint32 reserved[3]; 557 }; 558 559 560 struct intel_microcode_extended_signature_header { 561 uint32 extended_signature_count; 562 uint32 extended_checksum; 563 uint32 reserved[3]; 564 }; 565 566 567 struct intel_microcode_extended_signature { 568 uint32 processor_signature; 569 uint32 processor_flags; 570 uint32 checksum; 571 }; 572 573 574 extern void (*gCpuIdleFunc)(void); 575 576 577 #ifdef __cplusplus 578 extern "C" { 579 #endif 580 581 struct arch_thread; 582 583 #ifdef __x86_64__ 584 void __x86_setup_system_time(uint64 conversionFactor, 585 uint64 conversionFactorNsecs); 586 #else 587 void __x86_setup_system_time(uint32 conversionFactor, 588 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 589 #endif 590 591 status_t __x86_patch_errata_percpu(int cpu); 592 593 void x86_userspace_thread_exit(void); 594 void x86_end_userspace_thread_exit(void); 595 596 addr_t x86_get_stack_frame(); 597 uint32 x86_count_mtrrs(void); 598 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 599 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 600 uint8* _type); 601 void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, 602 uint32 count); 603 void x86_init_fpu(); 604 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 605 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 606 int32 x86_double_fault_get_cpu(void); 607 608 void x86_invalid_exception(iframe* frame); 609 void x86_fatal_exception(iframe* frame); 610 void x86_unexpected_exception(iframe* frame); 611 void x86_hardware_interrupt(iframe* frame); 612 void x86_page_fault_exception(iframe* iframe); 613 614 #ifndef __x86_64__ 615 616 void x86_swap_pgdir(addr_t newPageDir); 617 618 uint64 x86_read_msr(uint32 registerNumber); 619 void x86_write_msr(uint32 registerNumber, uint64 value); 620 621 void x86_context_switch(struct arch_thread* oldState, 622 struct arch_thread* newState); 623 624 void x86_fnsave(void* fpuState); 625 void x86_frstor(const void* fpuState); 626 627 void x86_fxsave(void* fpuState); 628 void x86_fxrstor(const void* fpuState); 629 630 void x86_noop_swap(void* oldFpuState, const void* newFpuState); 631 void x86_fnsave_swap(void* oldFpuState, const void* newFpuState); 632 void x86_fxsave_swap(void* oldFpuState, const void* newFpuState); 633 634 #endif 635 636 637 static inline void 638 arch_cpu_idle(void) 639 { 640 gCpuIdleFunc(); 641 } 642 643 644 static inline void 645 arch_cpu_pause(void) 646 { 647 asm volatile("pause" : : : "memory"); 648 } 649 650 651 #ifdef __cplusplus 652 } // extern "C" { 653 #endif 654 655 #endif // !_ASSEMBLER 656 657 #endif /* _KERNEL_ARCH_x86_CPU_H */ 658