1 /* 2 * Copyright 2018, Jérôme Duval, jerome.duval@gmail.com. 3 * Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de. 4 * Copyright 2012, Alex Smith, alex@alex-smith.me.uk. 5 * Distributed under the terms of the MIT License. 6 * 7 * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved. 8 * Distributed under the terms of the NewOS License. 9 */ 10 #ifndef _KERNEL_ARCH_x86_CPU_H 11 #define _KERNEL_ARCH_x86_CPU_H 12 13 14 #ifndef _ASSEMBLER 15 16 #include <module.h> 17 18 #include <arch_thread_types.h> 19 20 #include <arch/x86/arch_altcodepatch.h> 21 #include <arch/x86/descriptors.h> 22 23 #ifdef __x86_64__ 24 # include <arch/x86/64/cpu.h> 25 #endif 26 27 #endif // !_ASSEMBLER 28 29 30 #define CPU_MAX_CACHE_LEVEL 8 31 32 #define CACHE_LINE_SIZE 64 33 34 35 // MSR registers (possibly Intel specific) 36 #define IA32_MSR_TSC 0x10 37 #define IA32_MSR_PLATFORM_ID 0x17 38 #define IA32_MSR_APIC_BASE 0x1b 39 #define IA32_MSR_SPEC_CTRL 0x48 40 #define IA32_MSR_PRED_CMD 0x49 41 #define IA32_MSR_UCODE_WRITE 0x79 // IA32_BIOS_UPDT_TRIG 42 #define IA32_MSR_UCODE_REV 0x8b // IA32_BIOS_SIGN_ID 43 #define IA32_MSR_PLATFORM_INFO 0xce 44 #define IA32_MSR_MPERF 0xe7 45 #define IA32_MSR_APERF 0xe8 46 #define IA32_MSR_MTRR_CAPABILITIES 0xfe 47 #define IA32_MSR_ARCH_CAPABILITIES 0x10a 48 #define IA32_MSR_FLUSH_CMD 0x10b 49 #define IA32_MSR_SYSENTER_CS 0x174 50 #define IA32_MSR_SYSENTER_ESP 0x175 51 #define IA32_MSR_SYSENTER_EIP 0x176 52 #define IA32_MSR_PERF_STATUS 0x198 53 #define IA32_MSR_PERF_CTL 0x199 54 #define IA32_MSR_TURBO_RATIO_LIMIT 0x1ad 55 #define IA32_MSR_ENERGY_PERF_BIAS 0x1b0 56 #define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff 57 #define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200 58 #define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201 59 60 // MSR SPEC CTRL bits 61 #define IA32_MSR_SPEC_CTRL_IBRS (1 << 0) 62 #define IA32_MSR_SPEC_CTRL_STIBP (1 << 1) 63 #define IA32_MSR_SPEC_CTRL_SSBD (1 << 2) 64 65 // MSR PRED CMD bits 66 #define IA32_MSR_PRED_CMD_IBPB (1 << 0) 67 68 // MSR APIC BASE bits 69 #define IA32_MSR_APIC_BASE_BSP 0x00000100 70 #define IA32_MSR_APIC_BASE_X2APIC 0x00000400 71 #define IA32_MSR_APIC_BASE_ENABLED 0x00000800 72 #define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000 73 74 // MSR EFER bits 75 // reference 76 #define IA32_MSR_EFER_SYSCALL (1 << 0) 77 #define IA32_MSR_EFER_NX (1 << 11) 78 79 // MSR ARCH CAPABILITIES bits 80 #define IA32_MSR_ARCH_CAP_RDCL_NO (1 << 0) 81 #define IA32_MSR_ARCH_CAP_IBRS_ALL (1 << 1) 82 #define IA32_MSR_ARCH_CAP_RSBA (1 << 2) 83 #define IA32_MSR_ARCH_CAP_SKIP_L1D_VMENTRY (1 << 3) 84 #define IA32_MSR_ARCH_CAP_SSB_NO (1 << 4) 85 86 // MSR FLUSH CMD bits 87 #define IA32_MSR_L1D_FLUSH (1 << 1) 88 89 // X2APIC MSRs. 90 #define IA32_MSR_APIC_ID 0x00000802 91 #define IA32_MSR_APIC_VERSION 0x00000803 92 #define IA32_MSR_APIC_TASK_PRIORITY 0x00000808 93 #define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a 94 #define IA32_MSR_APIC_EOI 0x0000080b 95 #define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d 96 #define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f 97 #define IA32_MSR_APIC_ERROR_STATUS 0x00000828 98 #define IA32_MSR_APIC_INTR_COMMAND 0x00000830 99 #define IA32_MSR_APIC_LVT_TIMER 0x00000832 100 #define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833 101 #define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834 102 #define IA32_MSR_APIC_LVT_LINT0 0x00000835 103 #define IA32_MSR_APIC_LVT_LINT1 0x00000836 104 #define IA32_MSR_APIC_LVT_ERROR 0x00000837 105 #define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838 106 #define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839 107 #define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e 108 #define IA32_MSR_APIC_SELF_IPI 0x0000083f 109 #define IA32_MSR_XSS 0x00000da0 110 111 // x86_64 MSRs. 112 #define IA32_MSR_EFER 0xc0000080 113 #define IA32_MSR_STAR 0xc0000081 114 #define IA32_MSR_LSTAR 0xc0000082 115 #define IA32_MSR_CSTAR 0xc0000083 116 #define IA32_MSR_FMASK 0xc0000084 117 #define IA32_MSR_FS_BASE 0xc0000100 118 #define IA32_MSR_GS_BASE 0xc0000101 119 #define IA32_MSR_KERNEL_GS_BASE 0xc0000102 120 #define IA32_MSR_TSC_AUX 0xc0000103 121 122 // K8 MSR registers 123 #define K8_MSR_IPM 0xc0010055 124 125 // x86 features from cpuid eax 1, edx register 126 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5) 127 #define IA32_FEATURE_FPU (1 << 0) // x87 fpu 128 #define IA32_FEATURE_VME (1 << 1) // virtual 8086 129 #define IA32_FEATURE_DE (1 << 2) // debugging extensions 130 #define IA32_FEATURE_PSE (1 << 3) // page size extensions 131 #define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction 132 #define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction 133 #define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing 134 #define IA32_FEATURE_MCE (1 << 7) // machine check exception 135 #define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction 136 #define IA32_FEATURE_APIC (1 << 9) // local apic on chip 137 // (1 << 10) // Reserved 138 #define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT 139 #define IA32_FEATURE_MTRR (1 << 12) // MTRR 140 #define IA32_FEATURE_PGE (1 << 13) // paging global bit 141 #define IA32_FEATURE_MCA (1 << 14) // machine check architecture 142 #define IA32_FEATURE_CMOV (1 << 15) // cmov instruction 143 #define IA32_FEATURE_PAT (1 << 16) // page attribute table 144 #define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages 145 #define IA32_FEATURE_PSN (1 << 18) // processor serial number 146 #define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction 147 // (1 << 20) // Reserved 148 #define IA32_FEATURE_DS (1 << 21) // debug store 149 #define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl 150 #define IA32_FEATURE_MMX (1 << 23) // mmx instructions 151 #define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction 152 #define IA32_FEATURE_SSE (1 << 25) // SSE 153 #define IA32_FEATURE_SSE2 (1 << 26) // SSE2 154 #define IA32_FEATURE_SS (1 << 27) // self snoop 155 #define IA32_FEATURE_HTT (1 << 28) // hyperthreading 156 #define IA32_FEATURE_TM (1 << 29) // thermal monitor 157 #define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86 158 #define IA32_FEATURE_PBE (1 << 31) // pending break enable 159 160 // x86 features from cpuid eax 1, ecx register 161 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4) 162 #define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3 163 #define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction 164 #define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store 165 #define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT 166 #define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store 167 #define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions 168 #define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions 169 #define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep 170 #define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2 171 #define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3 172 #define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID 173 // (1 << 11) // Reserved 174 #define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add 175 #define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B 176 #define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control 177 #define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability 178 // (1 << 16) // Reserved 179 #define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers 180 #define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access 181 #define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1 182 #define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2 183 #define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support 184 #define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction 185 #define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction 186 #define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline 187 #define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions 188 #define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States 189 #define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE 190 #define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions 191 #define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion 192 #define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction 193 #define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor 194 195 // x86 features from cpuid eax 0x80000001, ecx register (AMD) 196 #define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode 197 #define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions 198 199 // x86 features from cpuid eax 0x80000001, edx register (AMD) 200 // only care about the ones that are unique to this register 201 #define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET 202 #define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit 203 #define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions 204 #define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR 205 #define IA32_FEATURE_AMD_EXT_PDPE1GB (1 << 26) // Gibibyte pages 206 #define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction 207 #define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode 208 #define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions 209 #define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow! 210 211 // some of the features from cpuid eax 0x80000001, edx register (AMD) are also 212 // available on Intel processors 213 #define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \ 214 | IA32_FEATURE_AMD_EXT_NX \ 215 | IA32_FEATURE_AMD_EXT_PDPE1GB \ 216 | IA32_FEATURE_AMD_EXT_RDTSCP \ 217 | IA32_FEATURE_AMD_EXT_LONG) 218 219 // x86 defined features from cpuid eax 5, ecx register 220 #define IA32_FEATURE_POWER_MWAIT (1 << 0) 221 #define IA32_FEATURE_INTERRUPT_MWAIT (1 << 1) 222 223 // x86 defined features from cpuid eax 6, eax register 224 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 225 #define IA32_FEATURE_DTS (1 << 0) // Digital Thermal Sensor 226 #define IA32_FEATURE_ITB (1 << 1) // Intel Turbo Boost Technology 227 #define IA32_FEATURE_ARAT (1 << 2) // Always running APIC Timer 228 #define IA32_FEATURE_PLN (1 << 4) // Power Limit Notification 229 #define IA32_FEATURE_ECMD (1 << 5) // Extended Clock Modulation Duty 230 #define IA32_FEATURE_PTM (1 << 6) // Package Thermal Management 231 232 // x86 defined features from cpuid eax 6, ecx register 233 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11) 234 #define IA32_FEATURE_APERFMPERF (1 << 0) // IA32_APERF, IA32_MPERF 235 #define IA32_FEATURE_EPB (1 << 3) // IA32_ENERGY_PERF_BIAS 236 237 // x86 features from cpuid eax 7, ebx register 238 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 239 #define IA32_FEATURE_TSC_ADJUST (1 << 1) // IA32_TSC_ADJUST MSR supported 240 #define IA32_FEATURE_SGX (1 << 2) // Software Guard Extensions 241 #define IA32_FEATURE_BMI1 (1 << 3) // Bit Manipulation Instruction Set 1 242 #define IA32_FEATURE_HLE (1 << 4) // Hardware Lock Elision 243 #define IA32_FEATURE_AVX2 (1 << 5) // Advanced Vector Extensions 2 244 #define IA32_FEATURE_SMEP (1 << 7) // Supervisor-Mode Execution Prevention 245 #define IA32_FEATURE_BMI2 (1 << 8) // Bit Manipulation Instruction Set 2 246 #define IA32_FEATURE_ERMS (1 << 9) // Enhanced REP MOVSB/STOSB 247 #define IA32_FEATURE_INVPCID (1 << 10) // INVPCID instruction 248 #define IA32_FEATURE_RTM (1 << 11) // Transactional Synchronization Extensions 249 #define IA32_FEATURE_CQM (1 << 12) // Platform Quality of Service Monitoring 250 #define IA32_FEATURE_MPX (1 << 14) // Memory Protection Extensions 251 #define IA32_FEATURE_RDT_A (1 << 15) // Resource Director Technology Allocation 252 #define IA32_FEATURE_AVX512F (1 << 16) // AVX-512 Foundation 253 #define IA32_FEATURE_AVX512DQ (1 << 17) // AVX-512 Doubleword and Quadword Instructions 254 #define IA32_FEATURE_RDSEED (1 << 18) // RDSEED instruction 255 #define IA32_FEATURE_ADX (1 << 19) // ADX (Multi-Precision Add-Carry Instruction Extensions) 256 #define IA32_FEATURE_SMAP (1 << 20) // Supervisor Mode Access Prevention 257 #define IA32_FEATURE_AVX512IFMA (1 << 21) // AVX-512 Integer Fused Multiply-Add Instructions 258 #define IA32_FEATURE_PCOMMIT (1 << 22) // PCOMMIT instruction 259 #define IA32_FEATURE_CLFLUSHOPT (1 << 23) // CLFLUSHOPT instruction 260 #define IA32_FEATURE_CLWB (1 << 24) // CLWB instruction 261 #define IA32_FEATURE_INTEL_PT (1 << 25) // Intel Processor Trace 262 #define IA32_FEATURE_AVX512PF (1 << 26) // AVX-512 Prefetch Instructions 263 #define IA32_FEATURE_AVX512ER (1 << 27) // AVX-512 Exponential and Reciprocal Instructions 264 #define IA32_FEATURE_AVX512CD (1 << 28) // AVX-512 Conflict Detection Instructions 265 #define IA32_FEATURE_SHA_NI (1 << 29) // SHA extensions 266 #define IA32_FEATURE_AVX512BW (1 << 30) // AVX-512 Byte and Word Instructions 267 #define IA32_FEATURE_AVX512VI (1 << 31) // AVX-512 Vector Length Extensions 268 269 // x86 features from cpuid eax 7, ecx register 270 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 271 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 272 #define IA32_FEATURE_AVX512VMBI (1 << 1) // AVX-512 Vector Bit Manipulation Instructions 273 #define IA32_FEATURE_UMIP (1 << 2) // User-mode Instruction Prevention 274 #define IA32_FEATURE_PKU (1 << 3) // Memory Protection Keys for User-mode pages 275 #define IA32_FEATURE_OSPKE (1 << 4) // PKU enabled by OS 276 #define IA32_FEATURE_AVX512VMBI2 (1 << 6) // AVX-512 Vector Bit Manipulation Instructions 2 277 #define IA32_FEATURE_GFNI (1 << 8) // Galois Field instructions 278 #define IA32_FEATURE_VAES (1 << 9) // AES instruction set (VEX-256/EVEX) 279 #define IA32_FEATURE_VPCLMULQDQ (1 << 10) // CLMUL instruction set (VEX-256/EVEX) 280 #define IA32_FEATURE_AVX512_VNNI (1 << 11) // AVX-512 Vector Neural Network Instructions 281 #define IA32_FEATURE_AVX512_BITALG (1 << 12) // AVX-512 BITALG instructions 282 #define IA32_FEATURE_AVX512_VPOPCNTDQ (1 << 14) // AVX-512 Vector Population Count D/Q 283 #define IA32_FEATURE_LA57 (1 << 16) // 5-level page tables 284 #define IA32_FEATURE_RDPID (1 << 22) // RDPID Instruction 285 #define IA32_FEATURE_SGX_LC (1 << 30) // SGX Launch Configuration 286 287 // x86 features from cpuid eax 7, edx register 288 // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features 289 #define IA32_FEATURE_AVX512_4VNNIW (1 << 2) // AVX-512 4-register Neural Network Instructions 290 #define IA32_FEATURE_AVX512_4FMAPS (1 << 3) // AVX-512 4-register Multiply Accumulation Single precision 291 #define IA32_FEATURE_IBRS (1 << 26) // IBRS / IBPB Speculation Control 292 #define IA32_FEATURE_STIBP (1 << 27) // STIBP Speculation Control 293 #define IA32_FEATURE_L1D_FLUSH (1 << 28) // L1D_FLUSH supported 294 #define IA32_FEATURE_ARCH_CAPABILITIES (1 << 29) // IA32_ARCH_CAPABILITIES MSR 295 #define IA32_FEATURE_SSBD (1 << 31) // Speculative Store Bypass Disable 296 297 // x86 features from cpuid eax 0xd, ecx 1, eax register 298 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 3-8) 299 #define IA32_FEATURE_XSAVEOPT (1 << 0) // XSAVEOPT Instruction 300 #define IA32_FEATURE_XSAVEC (1 << 1) // XSAVEC and compacted XRSTOR 301 #define IA32_FEATURE_XGETBV1 (1 << 2) // XGETBV with ECX=1 Instruction 302 #define IA32_FEATURE_XSAVES (1 << 3) // XSAVES and XRSTORS Instruction 303 304 // x86 defined features from cpuid eax 0x80000007, edx register 305 #define IA32_FEATURE_INVARIANT_TSC (1 << 8) 306 307 // x86 defined features from cpuid eax 0x80000008, ebx register 308 #define IA32_FEATURE_CLZERO (1 << 0) // CLZERO instruction 309 #define IA32_FEATURE_IBPB (1 << 12) // IBPB Support only (no IBRS) 310 #define IA32_FEATURE_AMD_SSBD (1 << 24) // Speculative Store Bypass Disable 311 #define IA32_FEATURE_VIRT_SSBD (1 << 25) // Virtualized Speculative Store Bypass Disable 312 #define IA32_FEATURE_AMD_SSB_NO (1 << 26) // Speculative Store Bypass is fixed in hardware 313 314 315 // Memory type ranges 316 #define IA32_MTR_UNCACHED 0 317 #define IA32_MTR_WRITE_COMBINING 1 318 #define IA32_MTR_WRITE_THROUGH 4 319 #define IA32_MTR_WRITE_PROTECTED 5 320 #define IA32_MTR_WRITE_BACK 6 321 322 // EFLAGS register 323 #define X86_EFLAGS_CARRY 0x00000001 324 #define X86_EFLAGS_RESERVED1 0x00000002 325 #define X86_EFLAGS_PARITY 0x00000004 326 #define X86_EFLAGS_AUXILIARY_CARRY 0x00000010 327 #define X86_EFLAGS_ZERO 0x00000040 328 #define X86_EFLAGS_SIGN 0x00000080 329 #define X86_EFLAGS_TRAP 0x00000100 330 #define X86_EFLAGS_INTERRUPT 0x00000200 331 #define X86_EFLAGS_DIRECTION 0x00000400 332 #define X86_EFLAGS_OVERFLOW 0x00000800 333 #define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000 334 #define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12 335 #define X86_EFLAGS_NESTED_TASK 0x00004000 336 #define X86_EFLAGS_RESUME 0x00010000 337 #define X86_EFLAGS_V86_MODE 0x00020000 338 #define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000 // also SMAP status 339 #define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000 340 #define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000 341 #define X86_EFLAGS_ID 0x00200000 342 343 #define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \ 344 | X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \ 345 | X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW) 346 347 #define CR0_CACHE_DISABLE (1UL << 30) 348 #define CR0_NOT_WRITE_THROUGH (1UL << 29) 349 #define CR0_FPU_EMULATION (1UL << 2) 350 #define CR0_MONITOR_FPU (1UL << 1) 351 352 // cr4 flags 353 #define IA32_CR4_PAE (1UL << 5) 354 #define IA32_CR4_GLOBAL_PAGES (1UL << 7) 355 #define CR4_OS_FXSR (1UL << 9) 356 #define CR4_OS_XMM_EXCEPTION (1UL << 10) 357 #define IA32_CR4_OSXSAVE (1UL << 18) 358 #define IA32_CR4_SMEP (1UL << 20) 359 #define IA32_CR4_SMAP (1UL << 21) 360 361 // Extended Control Register XCR0 flags 362 #define IA32_XCR0_X87 (1UL << 0) 363 #define IA32_XCR0_SSE (1UL << 1) 364 #define IA32_XCR0_AVX (1UL << 2) 365 366 // page fault error codes (http://wiki.osdev.org/Page_Fault) 367 #define PGFAULT_P 0x01 // Protection violation 368 #define PGFAULT_W 0x02 // Write 369 #define PGFAULT_U 0x04 // Usermode 370 #define PGFAULT_RSVD 0x08 // Reserved bits 371 #define PGFAULT_I 0x10 // Instruction fetch 372 373 // iframe types 374 #define IFRAME_TYPE_SYSCALL 0x1 375 #define IFRAME_TYPE_OTHER 0x2 376 #define IFRAME_TYPE_MASK 0xf 377 378 379 #ifndef _ASSEMBLER 380 381 382 struct X86PagingStructures; 383 384 385 typedef struct x86_mtrr_info { 386 uint64 base; 387 uint64 size; 388 uint8 type; 389 } x86_mtrr_info; 390 391 typedef struct x86_cpu_module_info { 392 module_info info; 393 uint32 (*count_mtrrs)(void); 394 void (*init_mtrrs)(void); 395 396 void (*set_mtrr)(uint32 index, uint64 base, uint64 length, 397 uint8 type); 398 status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length, 399 uint8* _type); 400 void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos, 401 uint32 count); 402 } x86_cpu_module_info; 403 404 // features 405 enum x86_feature_type { 406 FEATURE_COMMON = 0, // cpuid eax=1, ecx register 407 FEATURE_EXT, // cpuid eax=1, edx register 408 FEATURE_EXT_AMD_ECX, // cpuid eax=0x80000001, ecx register (AMD) 409 FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD) 410 FEATURE_5_ECX, // cpuid eax=5, ecx register 411 FEATURE_6_EAX, // cpuid eax=6, eax registers 412 FEATURE_6_ECX, // cpuid eax=6, ecx registers 413 FEATURE_7_EBX, // cpuid eax=7, ebx registers 414 FEATURE_7_ECX, // cpuid eax=7, ecx registers 415 FEATURE_7_EDX, // cpuid eax=7, edx registers 416 FEATURE_EXT_7_EDX, // cpuid eax=0x80000007, edx register 417 FEATURE_EXT_8_EBX, // cpuid eax=0x80000008, ebx register 418 FEATURE_D_1_EAX, // cpuid eax=0xd, ecx=1, eax register 419 420 FEATURE_NUM 421 }; 422 423 enum x86_vendors { 424 VENDOR_INTEL = 0, 425 VENDOR_AMD, 426 VENDOR_CYRIX, 427 VENDOR_UMC, 428 VENDOR_NEXGEN, 429 VENDOR_CENTAUR, 430 VENDOR_RISE, 431 VENDOR_TRANSMETA, 432 VENDOR_NSC, 433 434 VENDOR_NUM, 435 VENDOR_UNKNOWN, 436 }; 437 438 439 typedef struct arch_cpu_info { 440 // saved cpu info 441 enum x86_vendors vendor; 442 uint32 feature[FEATURE_NUM]; 443 char model_name[49]; 444 const char* vendor_name; 445 int type; 446 int family; 447 int extended_family; 448 int stepping; 449 int model; 450 int extended_model; 451 uint32 patch_level; 452 453 uint32 logical_apic_id; 454 455 struct X86PagingStructures* active_paging_structures; 456 457 size_t dr6; // temporary storage for debug registers (cf. 458 size_t dr7; // x86_exit_user_debug_at_kernel_entry()) 459 460 // local TSS for this cpu 461 struct tss tss; 462 #ifndef __x86_64__ 463 struct tss double_fault_tss; 464 void* kernel_tls; 465 #endif 466 } arch_cpu_info; 467 468 469 // Reference Intel SDM Volume 3 9.11 "Microcode Update Facilities" 470 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 471 // 9.11.1 Table 9-7. Microcode Update Field Definitions 472 struct intel_microcode_header { 473 uint32 header_version; 474 uint32 update_revision; 475 uint32 date; 476 uint32 processor_signature; 477 uint32 checksum; 478 uint32 loader_revision; 479 uint32 processor_flags; 480 uint32 data_size; 481 uint32 total_size; 482 uint32 reserved[3]; 483 }; 484 485 486 struct intel_microcode_extended_signature_header { 487 uint32 extended_signature_count; 488 uint32 extended_checksum; 489 uint32 reserved[3]; 490 }; 491 492 493 struct intel_microcode_extended_signature { 494 uint32 processor_signature; 495 uint32 processor_flags; 496 uint32 checksum; 497 }; 498 499 500 #define nop() __asm__ ("nop"::) 501 502 #define x86_read_cr0() ({ \ 503 size_t _v; \ 504 __asm__("mov %%cr0,%0" : "=r" (_v)); \ 505 _v; \ 506 }) 507 508 #define x86_write_cr0(value) \ 509 __asm__("mov %0,%%cr0" : : "r" (value)) 510 511 #define x86_read_cr2() ({ \ 512 size_t _v; \ 513 __asm__("mov %%cr2,%0" : "=r" (_v)); \ 514 _v; \ 515 }) 516 517 #define x86_read_cr3() ({ \ 518 size_t _v; \ 519 __asm__("mov %%cr3,%0" : "=r" (_v)); \ 520 _v; \ 521 }) 522 523 #define x86_write_cr3(value) \ 524 __asm__("mov %0,%%cr3" : : "r" (value)) 525 526 #define x86_read_cr4() ({ \ 527 size_t _v; \ 528 __asm__("mov %%cr4,%0" : "=r" (_v)); \ 529 _v; \ 530 }) 531 532 #define x86_write_cr4(value) \ 533 __asm__("mov %0,%%cr4" : : "r" (value)) 534 535 #define x86_read_dr3() ({ \ 536 size_t _v; \ 537 __asm__("mov %%dr3,%0" : "=r" (_v)); \ 538 _v; \ 539 }) 540 541 #define x86_write_dr3(value) \ 542 __asm__("mov %0,%%dr3" : : "r" (value)) 543 544 #define invalidate_TLB(va) \ 545 __asm__("invlpg (%0)" : : "r" (va)) 546 547 #define wbinvd() \ 548 __asm__ volatile ("wbinvd" : : : "memory") 549 550 #define set_ac() \ 551 __asm__ volatile (ASM_STAC : : : "memory") 552 553 #define clear_ac() \ 554 __asm__ volatile (ASM_CLAC : : : "memory") 555 556 #define xgetbv(reg) ({ \ 557 uint32 low, high; \ 558 __asm__ volatile ("xgetbv" : "=a" (low), "=d" (high), "c" (reg)); \ 559 (low | (uint64)high << 32); \ 560 }) 561 562 #define xsetbv(reg, value) { \ 563 uint32 low = value; uint32 high = value >> 32; \ 564 __asm__ volatile ("xsetbv" : : "a" (low), "d" (high), "c" (reg)); } 565 566 #define out8(value,port) \ 567 __asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port)) 568 569 #define out16(value,port) \ 570 __asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port)) 571 572 #define out32(value,port) \ 573 __asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port)) 574 575 #define in8(port) ({ \ 576 uint8 _v; \ 577 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \ 578 _v; \ 579 }) 580 581 #define in16(port) ({ \ 582 uint16 _v; \ 583 __asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \ 584 _v; \ 585 }) 586 587 #define in32(port) ({ \ 588 uint32 _v; \ 589 __asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \ 590 _v; \ 591 }) 592 593 #define out8_p(value,port) \ 594 __asm__ ("outb %%al,%%dx\n" \ 595 "\tjmp 1f\n" \ 596 "1:\tjmp 1f\n" \ 597 "1:" : : "a" (value), "d" (port)) 598 599 #define in8_p(port) ({ \ 600 uint8 _v; \ 601 __asm__ volatile ("inb %%dx,%%al\n" \ 602 "\tjmp 1f\n" \ 603 "1:\tjmp 1f\n" \ 604 "1:" : "=a" (_v) : "d" (port)); \ 605 _v; \ 606 }) 607 608 609 extern void (*gCpuIdleFunc)(void); 610 611 612 #ifdef __cplusplus 613 extern "C" { 614 #endif 615 616 struct arch_thread; 617 618 #ifdef __x86_64__ 619 void __x86_setup_system_time(uint64 conversionFactor, 620 uint64 conversionFactorNsecs); 621 #else 622 void __x86_setup_system_time(uint32 conversionFactor, 623 uint32 conversionFactorNsecs, bool conversionFactorNsecsShift); 624 #endif 625 626 status_t __x86_patch_errata_percpu(int cpu); 627 628 void x86_userspace_thread_exit(void); 629 void x86_end_userspace_thread_exit(void); 630 631 addr_t x86_get_stack_frame(); 632 uint32 x86_count_mtrrs(void); 633 void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type); 634 status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length, 635 uint8* _type); 636 void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos, 637 uint32 count); 638 void x86_init_fpu(); 639 bool x86_check_feature(uint32 feature, enum x86_feature_type type); 640 void* x86_get_double_fault_stack(int32 cpu, size_t* _size); 641 int32 x86_double_fault_get_cpu(void); 642 643 void x86_invalid_exception(iframe* frame); 644 void x86_fatal_exception(iframe* frame); 645 void x86_unexpected_exception(iframe* frame); 646 void x86_hardware_interrupt(iframe* frame); 647 void x86_page_fault_exception(iframe* iframe); 648 649 #ifndef __x86_64__ 650 651 void x86_swap_pgdir(addr_t newPageDir); 652 653 uint64 x86_read_msr(uint32 registerNumber); 654 void x86_write_msr(uint32 registerNumber, uint64 value); 655 656 void x86_context_switch(struct arch_thread* oldState, 657 struct arch_thread* newState); 658 659 void x86_fnsave(void* fpuState); 660 void x86_frstor(const void* fpuState); 661 662 void x86_fxsave(void* fpuState); 663 void x86_fxrstor(const void* fpuState); 664 665 void x86_noop_swap(void* oldFpuState, const void* newFpuState); 666 void x86_fnsave_swap(void* oldFpuState, const void* newFpuState); 667 void x86_fxsave_swap(void* oldFpuState, const void* newFpuState); 668 669 #endif 670 671 672 static inline void 673 arch_cpu_idle(void) 674 { 675 gCpuIdleFunc(); 676 } 677 678 679 static inline void 680 arch_cpu_pause(void) 681 { 682 asm volatile("pause" : : : "memory"); 683 } 684 685 686 #ifdef __cplusplus 687 } // extern "C" { 688 #endif 689 690 #endif // !_ASSEMBLER 691 692 #endif /* _KERNEL_ARCH_x86_CPU_H */ 693