1 /* 2 * Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. 3 * Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_PPC_CPU_H 6 #define _KERNEL_ARCH_PPC_CPU_H 7 8 9 #include <arch/ppc/arch_thread_types.h> 10 #include <kernel.h> 11 12 13 struct iframe { 14 uint32 vector; 15 uint32 srr0; 16 uint32 srr1; 17 uint32 dar; 18 uint32 dsisr; 19 uint32 lr; 20 uint32 cr; 21 uint32 xer; 22 uint32 ctr; 23 uint32 fpscr; 24 uint32 r31; 25 uint32 r30; 26 uint32 r29; 27 uint32 r28; 28 uint32 r27; 29 uint32 r26; 30 uint32 r25; 31 uint32 r24; 32 uint32 r23; 33 uint32 r22; 34 uint32 r21; 35 uint32 r20; 36 uint32 r19; 37 uint32 r18; 38 uint32 r17; 39 uint32 r16; 40 uint32 r15; 41 uint32 r14; 42 uint32 r13; 43 uint32 r12; 44 uint32 r11; 45 uint32 r10; 46 uint32 r9; 47 uint32 r8; 48 uint32 r7; 49 uint32 r6; 50 uint32 r5; 51 uint32 r4; 52 uint32 r3; 53 uint32 r2; 54 uint32 r1; 55 uint32 r0; 56 double f31; 57 double f30; 58 double f29; 59 double f28; 60 double f27; 61 double f26; 62 double f25; 63 double f24; 64 double f23; 65 double f22; 66 double f21; 67 double f20; 68 double f19; 69 double f18; 70 double f17; 71 double f16; 72 double f15; 73 double f14; 74 double f13; 75 double f12; 76 double f11; 77 double f10; 78 double f9; 79 double f8; 80 double f7; 81 double f6; 82 double f5; 83 double f4; 84 double f3; 85 double f2; 86 double f1; 87 double f0; 88 }; 89 90 enum machine_state { 91 MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE 92 MSR_PRIVILEGE_LEVEL = 1L << 14, // PR 93 MSR_FP_AVAILABLE = 1L << 13, // FP 94 MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME 95 MSR_EXCEPTION_PREFIX = 1L << 6, // IP 96 MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR 97 MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR 98 }; 99 100 struct block_address_translation; 101 102 typedef struct arch_cpu_info { 103 int null; 104 } arch_cpu_info; 105 106 107 #ifdef __cplusplus 108 extern "C" { 109 #endif 110 111 extern uint32 get_sdr1(void); 112 extern void set_sdr1(uint32 value); 113 extern uint32 get_sr(void *virtualAddress); 114 extern void set_sr(void *virtualAddress, uint32 value); 115 extern uint32 get_msr(void); 116 extern uint32 set_msr(uint32 value); 117 extern uint32 get_pvr(void); 118 119 extern void set_ibat0(struct block_address_translation *bat); 120 extern void set_ibat1(struct block_address_translation *bat); 121 extern void set_ibat2(struct block_address_translation *bat); 122 extern void set_ibat3(struct block_address_translation *bat); 123 extern void set_dbat0(struct block_address_translation *bat); 124 extern void set_dbat1(struct block_address_translation *bat); 125 extern void set_dbat2(struct block_address_translation *bat); 126 extern void set_dbat3(struct block_address_translation *bat); 127 128 extern void get_ibat0(struct block_address_translation *bat); 129 extern void get_ibat1(struct block_address_translation *bat); 130 extern void get_ibat2(struct block_address_translation *bat); 131 extern void get_ibat3(struct block_address_translation *bat); 132 extern void get_dbat0(struct block_address_translation *bat); 133 extern void get_dbat1(struct block_address_translation *bat); 134 extern void get_dbat2(struct block_address_translation *bat); 135 extern void get_dbat3(struct block_address_translation *bat); 136 137 extern void reset_ibats(void); 138 extern void reset_dbats(void); 139 140 //extern void sethid0(unsigned int val); 141 //extern unsigned int getl2cr(void); 142 //extern void setl2cr(unsigned int val); 143 extern long long get_time_base(void); 144 145 void __ppc_setup_system_time(vint32 *cvFactor); 146 // defined in libroot: os/arch/system_time.c 147 int64 __ppc_get_time_base(void); 148 // defined in libroot: os/arch/system_time_asm.S 149 150 extern void ppc_context_switch(void **_oldStackPointer, void *newStackPointer); 151 152 extern bool ppc_set_fault_handler(addr_t *handlerLocation, addr_t handler) 153 __attribute__((noinline)); 154 155 #ifdef __cplusplus 156 } 157 #endif 158 159 #define eieio() asm volatile("eieio") 160 #define isync() asm volatile("isync") 161 #define tlbsync() asm volatile("tlbsync") 162 #define ppc_sync() asm volatile("sync") 163 #define tlbia() asm volatile("tlbia") 164 #define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr)) 165 166 167 // PowerPC processor version (the upper 16 bits of the PVR). 168 enum ppc_processor_version { 169 MPC601 = 0x0001, 170 MPC603 = 0x0003, 171 MPC604 = 0x0004, 172 MPC602 = 0x0005, 173 MPC603e = 0x0006, 174 MPC603ev = 0x0007, 175 MPC750 = 0x0008, 176 MPC604ev = 0x0009, 177 MPC7400 = 0x000c, 178 MPC620 = 0x0014, 179 IBM403 = 0x0020, 180 IBM401A1 = 0x0021, 181 IBM401B2 = 0x0022, 182 IBM401C2 = 0x0023, 183 IBM401D2 = 0x0024, 184 IBM401E2 = 0x0025, 185 IBM401F2 = 0x0026, 186 IBM401G2 = 0x0027, 187 IBMPOWER3 = 0x0041, 188 MPC860 = 0x0050, 189 MPC8240 = 0x0081, 190 AMCC460EX = 0x1302, 191 IBM405GP = 0x4011, 192 IBM405L = 0x4161, 193 AMCC440EP = 0x4222, 194 IBM750FX = 0x7000, 195 MPC7450 = 0x8000, 196 MPC7455 = 0x8001, 197 MPC7457 = 0x8002, 198 MPC7447A = 0x8003, 199 MPC7448 = 0x8004, 200 MPC7410 = 0x800c, 201 MPC8245 = 0x8081, 202 }; 203 204 205 /* 206 Use of (some) special purpose registers. 207 208 SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context 209 structure 210 SPRG1: scratch 211 SPRG2: current Thread* 212 SPRG3: TLS base pointer (only for userland threads) 213 */ 214 215 #endif /* _KERNEL_ARCH_PPC_CPU_H */ 216