1 /* 2 * Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. 3 * Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_PPC_CPU_H 6 #define _KERNEL_ARCH_PPC_CPU_H 7 8 9 #include <arch/ppc/arch_thread_types.h> 10 #include <arch/ppc/cpu.h> 11 #include <kernel.h> 12 13 14 #define CPU_MAX_CACHE_LEVEL 8 15 #define CACHE_LINE_SIZE 128 16 // 128 Byte lines on PPC970 17 18 19 struct iframe { 20 uint32 vector; 21 uint32 srr0; 22 uint32 srr1; 23 uint32 dar; 24 uint32 dsisr; 25 uint32 lr; 26 uint32 cr; 27 uint32 xer; 28 uint32 ctr; 29 uint32 fpscr; 30 uint32 r31; 31 uint32 r30; 32 uint32 r29; 33 uint32 r28; 34 uint32 r27; 35 uint32 r26; 36 uint32 r25; 37 uint32 r24; 38 uint32 r23; 39 uint32 r22; 40 uint32 r21; 41 uint32 r20; 42 uint32 r19; 43 uint32 r18; 44 uint32 r17; 45 uint32 r16; 46 uint32 r15; 47 uint32 r14; 48 uint32 r13; 49 uint32 r12; 50 uint32 r11; 51 uint32 r10; 52 uint32 r9; 53 uint32 r8; 54 uint32 r7; 55 uint32 r6; 56 uint32 r5; 57 uint32 r4; 58 uint32 r3; 59 uint32 r2; 60 uint32 r1; 61 uint32 r0; 62 double f31; 63 double f30; 64 double f29; 65 double f28; 66 double f27; 67 double f26; 68 double f25; 69 double f24; 70 double f23; 71 double f22; 72 double f21; 73 double f20; 74 double f19; 75 double f18; 76 double f17; 77 double f16; 78 double f15; 79 double f14; 80 double f13; 81 double f12; 82 double f11; 83 double f10; 84 double f9; 85 double f8; 86 double f7; 87 double f6; 88 double f5; 89 double f4; 90 double f3; 91 double f2; 92 double f1; 93 double f0; 94 }; 95 96 enum machine_state { 97 MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE 98 MSR_PRIVILEGE_LEVEL = 1L << 14, // PR 99 MSR_FP_AVAILABLE = 1L << 13, // FP 100 MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME 101 MSR_EXCEPTION_PREFIX = 1L << 6, // IP 102 MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR 103 MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR 104 }; 105 106 struct block_address_translation; 107 108 typedef struct arch_cpu_info { 109 int null; 110 } arch_cpu_info; 111 112 113 #define eieio() asm volatile("eieio") 114 #define isync() asm volatile("isync") 115 #define tlbsync() asm volatile("tlbsync") 116 #define ppc_sync() asm volatile("sync") 117 #define tlbia() asm volatile("tlbia") 118 #define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr)) 119 120 // adjust thread priority on PowerPC (Shared resource hints) 121 #define SRH_very_low() asm volatile("or 31,31,31") 122 #define SRH_low() asm volatile("or 1,1,1") 123 #define SRH_medium_low() asm volatile("or 6,6,6") 124 #define SRH_medium() asm volatile("or 2,2,2") 125 #define SRH_medium_high() asm volatile("or 5,5,5") 126 #define SRH_high() asm volatile("or 3,3,3") 127 128 129 #ifdef __cplusplus 130 extern "C" { 131 #endif 132 133 extern uint32 get_sdr1(void); 134 extern void set_sdr1(uint32 value); 135 extern uint32 get_sr(void *virtualAddress); 136 extern void set_sr(void *virtualAddress, uint32 value); 137 extern uint32 get_msr(void); 138 extern uint32 set_msr(uint32 value); 139 extern uint32 get_pvr(void); 140 141 extern void set_ibat0(struct block_address_translation *bat); 142 extern void set_ibat1(struct block_address_translation *bat); 143 extern void set_ibat2(struct block_address_translation *bat); 144 extern void set_ibat3(struct block_address_translation *bat); 145 extern void set_dbat0(struct block_address_translation *bat); 146 extern void set_dbat1(struct block_address_translation *bat); 147 extern void set_dbat2(struct block_address_translation *bat); 148 extern void set_dbat3(struct block_address_translation *bat); 149 150 extern void get_ibat0(struct block_address_translation *bat); 151 extern void get_ibat1(struct block_address_translation *bat); 152 extern void get_ibat2(struct block_address_translation *bat); 153 extern void get_ibat3(struct block_address_translation *bat); 154 extern void get_dbat0(struct block_address_translation *bat); 155 extern void get_dbat1(struct block_address_translation *bat); 156 extern void get_dbat2(struct block_address_translation *bat); 157 extern void get_dbat3(struct block_address_translation *bat); 158 159 extern void reset_ibats(void); 160 extern void reset_dbats(void); 161 162 //extern void sethid0(unsigned int val); 163 //extern unsigned int getl2cr(void); 164 //extern void setl2cr(unsigned int val); 165 extern long long get_time_base(void); 166 167 void __ppc_setup_system_time(vint32 *cvFactor); 168 // defined in libroot: os/arch/system_time.c 169 int64 __ppc_get_time_base(void); 170 // defined in libroot: os/arch/system_time_asm.S 171 172 extern void ppc_context_switch(void **_oldStackPointer, void *newStackPointer); 173 174 extern bool ppc_set_fault_handler(addr_t *handlerLocation, addr_t handler) 175 __attribute__((noinline)); 176 177 178 static inline void 179 arch_cpu_pause(void) 180 { 181 // TODO: PowerPC review logic of setting very low for pause 182 SRH_very_low(); 183 } 184 185 186 static inline void 187 arch_cpu_idle(void) 188 { 189 // TODO: PowerPC CPU idle call 190 } 191 192 193 #ifdef __cplusplus 194 } 195 #endif 196 197 // PowerPC processor version (the upper 16 bits of the PVR). 198 enum ppc_processor_version { 199 MPC601 = 0x0001, 200 MPC603 = 0x0003, 201 MPC604 = 0x0004, 202 MPC602 = 0x0005, 203 MPC603e = 0x0006, 204 MPC603ev = 0x0007, 205 MPC750 = 0x0008, 206 MPC604ev = 0x0009, 207 MPC7400 = 0x000c, 208 MPC620 = 0x0014, 209 IBM403 = 0x0020, 210 IBM401A1 = 0x0021, 211 IBM401B2 = 0x0022, 212 IBM401C2 = 0x0023, 213 IBM401D2 = 0x0024, 214 IBM401E2 = 0x0025, 215 IBM401F2 = 0x0026, 216 IBM401G2 = 0x0027, 217 IBMPOWER3 = 0x0041, 218 MPC860 = 0x0050, 219 MPC8240 = 0x0081, 220 AMCC460EX = 0x1302, 221 IBM405GP = 0x4011, 222 IBM405L = 0x4161, 223 AMCC440EP = 0x4222, 224 IBM750FX = 0x7000, 225 MPC7450 = 0x8000, 226 MPC7455 = 0x8001, 227 MPC7457 = 0x8002, 228 MPC7447A = 0x8003, 229 MPC7448 = 0x8004, 230 MPC7410 = 0x800c, 231 MPC8245 = 0x8081, 232 }; 233 234 235 /* 236 Use of (some) special purpose registers. 237 238 SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context 239 structure 240 SPRG1: scratch 241 SPRG2: current Thread* 242 SPRG3: TLS base pointer (only for userland threads) 243 */ 244 245 #endif /* _KERNEL_ARCH_PPC_CPU_H */ 246