1 /* 2 * Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. 3 * Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_PPC_CPU_H 6 #define _KERNEL_ARCH_PPC_CPU_H 7 8 9 #include <arch/ppc/arch_thread_types.h> 10 #include <kernel.h> 11 12 13 #define CPU_MAX_CACHE_LEVEL 8 14 #define CACHE_LINE_SIZE 128 15 // 128 Byte lines on PPC970 16 17 18 struct iframe { 19 uint32 vector; 20 uint32 srr0; 21 uint32 srr1; 22 uint32 dar; 23 uint32 dsisr; 24 uint32 lr; 25 uint32 cr; 26 uint32 xer; 27 uint32 ctr; 28 uint32 fpscr; 29 uint32 r31; 30 uint32 r30; 31 uint32 r29; 32 uint32 r28; 33 uint32 r27; 34 uint32 r26; 35 uint32 r25; 36 uint32 r24; 37 uint32 r23; 38 uint32 r22; 39 uint32 r21; 40 uint32 r20; 41 uint32 r19; 42 uint32 r18; 43 uint32 r17; 44 uint32 r16; 45 uint32 r15; 46 uint32 r14; 47 uint32 r13; 48 uint32 r12; 49 uint32 r11; 50 uint32 r10; 51 uint32 r9; 52 uint32 r8; 53 uint32 r7; 54 uint32 r6; 55 uint32 r5; 56 uint32 r4; 57 uint32 r3; 58 uint32 r2; 59 uint32 r1; 60 uint32 r0; 61 double f31; 62 double f30; 63 double f29; 64 double f28; 65 double f27; 66 double f26; 67 double f25; 68 double f24; 69 double f23; 70 double f22; 71 double f21; 72 double f20; 73 double f19; 74 double f18; 75 double f17; 76 double f16; 77 double f15; 78 double f14; 79 double f13; 80 double f12; 81 double f11; 82 double f10; 83 double f9; 84 double f8; 85 double f7; 86 double f6; 87 double f5; 88 double f4; 89 double f3; 90 double f2; 91 double f1; 92 double f0; 93 }; 94 95 enum machine_state { 96 MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE 97 MSR_PRIVILEGE_LEVEL = 1L << 14, // PR 98 MSR_FP_AVAILABLE = 1L << 13, // FP 99 MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME 100 MSR_EXCEPTION_PREFIX = 1L << 6, // IP 101 MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR 102 MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR 103 }; 104 105 struct block_address_translation; 106 107 typedef struct arch_cpu_info { 108 int null; 109 } arch_cpu_info; 110 111 112 #define eieio() asm volatile("eieio") 113 #define isync() asm volatile("isync") 114 #define tlbsync() asm volatile("tlbsync") 115 #define ppc_sync() asm volatile("sync") 116 #define tlbia() asm volatile("tlbia") 117 #define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr)) 118 119 // adjust thread priority on PowerPC (Shared resource hints) 120 #define SRH_very_low() asm volatile("or 31,31,31") 121 #define SRH_low() asm volatile("or 1,1,1") 122 #define SRH_medium_low() asm volatile("or 6,6,6") 123 #define SRH_medium() asm volatile("or 2,2,2") 124 #define SRH_medium_high() asm volatile("or 5,5,5") 125 #define SRH_high() asm volatile("or 3,3,3") 126 127 128 #ifdef __cplusplus 129 extern "C" { 130 #endif 131 132 extern uint32 get_sdr1(void); 133 extern void set_sdr1(uint32 value); 134 extern uint32 get_sr(void *virtualAddress); 135 extern void set_sr(void *virtualAddress, uint32 value); 136 extern uint32 get_msr(void); 137 extern uint32 set_msr(uint32 value); 138 extern uint32 get_pvr(void); 139 140 extern void set_ibat0(struct block_address_translation *bat); 141 extern void set_ibat1(struct block_address_translation *bat); 142 extern void set_ibat2(struct block_address_translation *bat); 143 extern void set_ibat3(struct block_address_translation *bat); 144 extern void set_dbat0(struct block_address_translation *bat); 145 extern void set_dbat1(struct block_address_translation *bat); 146 extern void set_dbat2(struct block_address_translation *bat); 147 extern void set_dbat3(struct block_address_translation *bat); 148 149 extern void get_ibat0(struct block_address_translation *bat); 150 extern void get_ibat1(struct block_address_translation *bat); 151 extern void get_ibat2(struct block_address_translation *bat); 152 extern void get_ibat3(struct block_address_translation *bat); 153 extern void get_dbat0(struct block_address_translation *bat); 154 extern void get_dbat1(struct block_address_translation *bat); 155 extern void get_dbat2(struct block_address_translation *bat); 156 extern void get_dbat3(struct block_address_translation *bat); 157 158 extern void reset_ibats(void); 159 extern void reset_dbats(void); 160 161 //extern void sethid0(unsigned int val); 162 //extern unsigned int getl2cr(void); 163 //extern void setl2cr(unsigned int val); 164 extern long long get_time_base(void); 165 166 void __ppc_setup_system_time(vint32 *cvFactor); 167 // defined in libroot: os/arch/system_time.c 168 int64 __ppc_get_time_base(void); 169 // defined in libroot: os/arch/system_time_asm.S 170 171 extern void ppc_context_switch(void **_oldStackPointer, void *newStackPointer); 172 173 extern bool ppc_set_fault_handler(addr_t *handlerLocation, addr_t handler) 174 __attribute__((noinline)); 175 176 177 static inline void 178 arch_cpu_pause(void) 179 { 180 // TODO: PowerPC review logic of setting very low for pause 181 SRH_very_low(); 182 } 183 184 185 static inline void 186 arch_cpu_idle(void) 187 { 188 // TODO: PowerPC CPU idle call 189 } 190 191 192 #ifdef __cplusplus 193 } 194 #endif 195 196 // PowerPC processor version (the upper 16 bits of the PVR). 197 enum ppc_processor_version { 198 MPC601 = 0x0001, 199 MPC603 = 0x0003, 200 MPC604 = 0x0004, 201 MPC602 = 0x0005, 202 MPC603e = 0x0006, 203 MPC603ev = 0x0007, 204 MPC750 = 0x0008, 205 MPC604ev = 0x0009, 206 MPC7400 = 0x000c, 207 MPC620 = 0x0014, 208 IBM403 = 0x0020, 209 IBM401A1 = 0x0021, 210 IBM401B2 = 0x0022, 211 IBM401C2 = 0x0023, 212 IBM401D2 = 0x0024, 213 IBM401E2 = 0x0025, 214 IBM401F2 = 0x0026, 215 IBM401G2 = 0x0027, 216 IBMPOWER3 = 0x0041, 217 MPC860 = 0x0050, 218 MPC8240 = 0x0081, 219 AMCC460EX = 0x1302, 220 IBM405GP = 0x4011, 221 IBM405L = 0x4161, 222 AMCC440EP = 0x4222, 223 IBM750FX = 0x7000, 224 MPC7450 = 0x8000, 225 MPC7455 = 0x8001, 226 MPC7457 = 0x8002, 227 MPC7447A = 0x8003, 228 MPC7448 = 0x8004, 229 MPC7410 = 0x800c, 230 MPC8245 = 0x8081, 231 }; 232 233 234 /* 235 Use of (some) special purpose registers. 236 237 SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context 238 structure 239 SPRG1: scratch 240 SPRG2: current Thread* 241 SPRG3: TLS base pointer (only for userland threads) 242 */ 243 244 #endif /* _KERNEL_ARCH_PPC_CPU_H */ 245