1 /* 2 ** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 ** Distributed under the terms of the Haiku License. 4 */ 5 #ifndef _KERNEL_ARCH_M68K_CPU_H 6 #define _KERNEL_ARCH_M68K_CPU_H 7 8 9 #include <arch/m68k/arch_thread_types.h> 10 #include <kernel.h> 11 12 13 #define PAGE_SIZE 4096 14 15 /* 68k has many different possible stack frames, differentiated by a 4 bit number, 16 * but they also depend on the cpu type. 17 * cf. mint/sys/arch/check_exc.h 18 */ 19 20 /* definitions for special status word */ 21 22 // 020 as well 23 struct mc68030_ssw { 24 uint16 fc:1; 25 uint16 fb:1; 26 uint16 rc:1; 27 uint16 rb:1; 28 uint16 :3; 29 uint16 df:1; 30 uint16 rm:1; 31 uint16 rw:1; 32 uint16 size:2; 33 uint16 :1; 34 uint16 as:3; 35 } _PACKED; 36 37 struct mc68040_ssw { 38 uint16 cp:1; 39 uint16 cu:1; 40 uint16 ct:1; 41 uint16 cm:1; 42 uint16 ma:1; 43 uint16 atc:1; 44 uint16 lk:1; 45 uint16 rw:1; 46 uint16 :1; 47 uint16 size:2; 48 uint16 tt:2; 49 uint16 tm:3; 50 } _PACKED; 51 52 struct mc68060_fslw { 53 uint32 :4; 54 uint32 ma:1; 55 uint32 :1; 56 uint32 lk:1; 57 uint32 rw:2; //XXX ?? 58 uint32 size:2; 59 uint32 tt:2; 60 uint32 tm:2; 61 uint32 io:1; 62 uint32 pbe:1; 63 uint32 sbe:1; 64 uint32 pta:1; 65 uint32 ptb:1; 66 uint32 il:1; 67 uint32 pf:1; 68 uint32 sb:1; 69 uint32 wp:1; 70 uint32 twe:1; 71 uint32 re:1; 72 uint32 we:1; 73 uint32 ttr:1; 74 uint32 bpe:1; 75 uint32 :1; 76 uint32 see:1; 77 } _PACKED; 78 79 /* raw exception frames */ 80 81 struct mc680x0_type_0_frame { 82 uint16 sr; 83 addr_t pc; 84 uint16 type:4; 85 uint16 vector:12; 86 }; 87 88 struct mc680x0_type_1_frame { 89 uint16 sr; 90 addr_t pc; 91 uint16 type:4; 92 uint16 vector:12; 93 }; 94 95 struct mc680x0_type_2_frame { 96 uint16 sr; 97 addr_t pc; 98 uint16 type:4; 99 uint16 vector:12; 100 addr_t instruction_address; 101 }; 102 103 struct mc680x0_type_3_frame { 104 uint16 sr; 105 addr_t pc; 106 uint16 type:4; 107 uint16 vector:12; 108 addr_t effective_address; 109 }; 110 111 struct mc68040_type_7_frame { 112 uint16 sr; 113 addr_t pc; 114 uint16 type:4; 115 uint16 vector:12; 116 addr_t effective_address; 117 struct mc68040_ssw ssw; 118 // write-back status 119 uint16 wb3s; 120 uint16 wb2s; 121 uint16 wb1s; 122 addr_t fault_address; 123 addr_t wb3a; 124 uint32 wb3d; 125 addr_t wb2a; 126 uint32 wb2d; 127 addr_t wb1a; 128 uint32 wb1d; // also pd0 129 uint32 pd1; 130 uint32 pd2; 131 uint32 pd3; 132 }; 133 134 struct mc680x0_type_9_frame { 135 uint16 sr; 136 addr_t pc; 137 uint16 type:4; 138 uint16 vector:12; 139 addr_t instruction_address; 140 uint16 intregs[4]; 141 }; 142 143 struct mc68030_type_a_frame { 144 uint16 sr; 145 addr_t pc; 146 uint16 type:4; 147 uint16 vector:12; 148 uint16 intreg1; 149 struct mc68030_ssw ssw; 150 uint16 instpipe_c; 151 uint16 instpipe_b; 152 addr_t fault_address; 153 uint16 intregs2[2]; 154 uint32 dataout; 155 uint16 intregs3[2]; 156 }; 157 158 struct mc68030_type_b_frame { 159 uint16 sr; 160 addr_t pc; 161 uint16 type:4; 162 uint16 vector:12; 163 uint16 intreg1; 164 struct mc68030_ssw ssw; 165 uint16 instpipe_c; 166 uint16 instpipe_b; 167 addr_t fault_address; 168 uint16 intregs2[2]; 169 uint32 dataout; 170 uint16 intregs3[4]; 171 uint32 stbaddr; 172 uint16 intregs4[2]; 173 uint32 datain; 174 uint16 intregs5[3]; 175 uint16 intinfo; 176 uint16 intregs6[18]; 177 }; 178 179 //XXX: add 060 frames 180 181 struct mc680x0_frame { 182 union { 183 struct { 184 uint16 sr; 185 addr_t pc; 186 uint16 type:4; 187 uint16 vector:12; 188 }; 189 struct mc680x0_type_0_frame type_0; 190 struct mc680x0_type_1_frame type_1; 191 struct mc680x0_type_2_frame type_2; 192 struct mc68040_type_7_frame type_7; 193 struct mc680x0_type_9_frame type_9; 194 struct mc68030_type_a_frame type_a; 195 struct mc68030_type_b_frame type_b; 196 // XXX: add 060 frames 197 }; 198 }; 199 200 #warning M68K: check for missing regs/movem 201 struct iframe { 202 // XXX: fp_frame ? 203 /* data and address registers */ 204 // XXX: order depends on movem 205 uint32 d[8]; 206 uint32 a[7]; 207 /* cpu exception frame, including sr, pc, format and vector */ 208 struct mc680x0_frame cpu; 209 210 /* uint32 vector; 211 uint32 srr0; 212 uint32 srr1; 213 uint32 dar; 214 uint32 dsisr; 215 uint32 lr; 216 uint32 cr; 217 uint32 xer; 218 uint32 ctr; 219 uint32 fpscr; 220 uint32 r31; 221 uint32 r30; 222 uint32 r29; 223 uint32 r28; 224 uint32 r27; 225 uint32 r26; 226 uint32 r25; 227 uint32 r24; 228 uint32 r23; 229 uint32 r22; 230 uint32 r21; 231 uint32 r20; 232 uint32 r19; 233 uint32 r18; 234 uint32 r17; 235 uint32 r16; 236 uint32 r15; 237 uint32 r14; 238 uint32 r13; 239 uint32 r12; 240 uint32 r11; 241 uint32 r10; 242 uint32 r9; 243 uint32 r8; 244 uint32 r7; 245 uint32 r6; 246 uint32 r5; 247 uint32 r4; 248 uint32 r3; 249 uint32 r2; 250 uint32 r1; 251 uint32 r0; 252 double f31; 253 double f30; 254 double f29; 255 double f28; 256 double f27; 257 double f26; 258 double f25; 259 double f24; 260 double f23; 261 double f22; 262 double f21; 263 double f20; 264 double f19; 265 double f18; 266 double f17; 267 double f16; 268 double f15; 269 double f14; 270 double f13; 271 double f12; 272 double f11; 273 double f10; 274 double f9; 275 double f8; 276 double f7; 277 double f6; 278 double f5; 279 double f4; 280 double f3; 281 double f2; 282 double f1; 283 double f0;*/ 284 } _PACKED; 285 286 enum machine_state { 287 MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE 288 MSR_PRIVILEGE_LEVEL = 1L << 14, // PR 289 MSR_FP_AVAILABLE = 1L << 13, // FP 290 MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME 291 MSR_EXCEPTION_PREFIX = 1L << 6, // IP 292 MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR 293 MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR 294 }; 295 296 //struct block_address_translation; 297 298 typedef struct arch_cpu_info { 299 int null; 300 } arch_cpu_info; 301 302 303 #ifdef __cplusplus 304 extern "C" { 305 #endif 306 307 #if 0 308 //PPC stuff 309 extern uint32 get_sdr1(void); 310 extern void set_sdr1(uint32 value); 311 extern uint32 get_sr(void *virtualAddress); 312 extern void set_sr(void *virtualAddress, uint32 value); 313 extern uint32 get_msr(void); 314 extern uint32 set_msr(uint32 value); 315 extern uint32 get_pvr(void); 316 317 extern void set_ibat0(struct block_address_translation *bat); 318 extern void set_ibat1(struct block_address_translation *bat); 319 extern void set_ibat2(struct block_address_translation *bat); 320 extern void set_ibat3(struct block_address_translation *bat); 321 extern void set_dbat0(struct block_address_translation *bat); 322 extern void set_dbat1(struct block_address_translation *bat); 323 extern void set_dbat2(struct block_address_translation *bat); 324 extern void set_dbat3(struct block_address_translation *bat); 325 326 extern void get_ibat0(struct block_address_translation *bat); 327 extern void get_ibat1(struct block_address_translation *bat); 328 extern void get_ibat2(struct block_address_translation *bat); 329 extern void get_ibat3(struct block_address_translation *bat); 330 extern void get_dbat0(struct block_address_translation *bat); 331 extern void get_dbat1(struct block_address_translation *bat); 332 extern void get_dbat2(struct block_address_translation *bat); 333 extern void get_dbat3(struct block_address_translation *bat); 334 335 extern void reset_ibats(void); 336 extern void reset_dbats(void); 337 #endif 338 339 //extern void sethid0(unsigned int val); 340 //extern unsigned int getl2cr(void); 341 //extern void setl2cr(unsigned int val); 342 extern long long get_time_base(void); 343 344 void __m68k_setup_system_time(vint32 *cvFactor); 345 // defined in libroot: os/arch/system_time.c 346 int64 __m68k_get_time_base(void); 347 // defined in libroot: os/arch/system_time_asm.S 348 349 extern void m68k_context_switch(void **_oldStackPointer, void *newStackPointer); 350 351 extern bool m68k_set_fault_handler(addr_t *handlerLocation, addr_t handler) 352 __attribute__((noinline)); 353 354 #ifdef __cplusplus 355 } 356 #endif 357 358 struct m68k_cpu_ops { 359 void (*flush_insn_pipeline)(void); 360 void (*flush_atc_all)(void); 361 void (*flush_atc_user)(void); 362 void (*flush_atc_addr)(void *addr); 363 void (*flush_dcache)(void *address, size_t len); 364 void (*flush_icache)(void *address, size_t len); 365 void (*idle)(void); 366 }; 367 368 extern struct m68k_cpu_ops cpu_ops; 369 370 //#define 371 372 #if 0 373 #define eieio() asm volatile("eieio") 374 #define isync() asm volatile("isync") 375 #define tlbsync() asm volatile("tlbsync") 376 #define ppc_sync() asm volatile("sync") 377 #define tlbia() asm volatile("tlbia") 378 #define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr)) 379 #endif 380 381 // m68k processor version. 382 enum m68k_processor_version { 383 /* those two we don't support */ 384 CPU_68000 = 0x0000, 385 CPU_68010 = 0x0001, 386 /* maybe with a pmmu and fpu */ 387 CPU_68020 = 0x0002, 388 /* should work */ 389 CPU_68030 = 0x0003, 390 CPU_68040 = 0x0004, 391 CPU_68060 = 0x0006, 392 /* mask */ 393 CPU_MASK = 0x000F 394 }; 395 396 enum m68k_fpu_version { 397 /* we don't support */ 398 FPU_NONE = 0x0000, 399 FPU_68881 = 0x0010, 400 FPU_68882 = 0x0020, 401 FPU_030 = 0x0030, 402 FPU_040 = 0x0040, 403 FPU_060 = 0x0060, 404 FPU_MASK = 0x00F0 405 }; 406 407 enum m68k_mmu_version { 408 MMU_NONE = 0x0000, 409 MMU_68551 = 0x0100, 410 MMU_68030 = 0x0300, 411 MMU_68040 = 0x0400, 412 MMU_68060 = 0x0600, 413 MMU_MASK = 0x0F00 414 }; 415 416 extern int arch_cpu_type; 417 extern int arch_fpu_type; 418 extern int arch_mmu_type; 419 extern int arch_platform; 420 421 /* 422 Use of (some) special purpose registers. 423 XXX: those regs aren't implemented/accessed the same way on different cpus... 424 425 SRP[63-32]: current struct thread* 426 SRP[31-0] : 427 CAAR : can we use it ?? 428 MSP : 429 430 PPC: 431 SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context 432 structure 433 SPRG1: scratch 434 SPRG2: current struct thread* 435 SPRG3: TLS base pointer (only for userland threads) 436 */ 437 438 #endif /* _KERNEL_ARCH_PPC_CPU_H */ 439