1 /* 2 * Copyright (c) 2008 Travis Geiselbrecht 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __PLATFORM_OMAP3_H 24 #define __PLATFORM_OMAP3_H 25 26 #define SDRAM_BASE 0x80000000 27 28 #define VECT_BASE 0x00000000 29 #define VECT_SIZE 0x1000 30 31 #define DEVICE_BASE 0x48000000 32 #define DEVICE_SIZE 0x2000000 33 34 /* framebuffer */ 35 #define FB_BASE 0x88000000 36 #define FB_SIZE 0x200000 37 38 #define L4_BASE 0x48000000 39 #define L4_WKUP_BASE 0x48300000 40 #define L4_PER_BASE 0x49000000 41 #define L4_EMU_BASE 0x54000000 42 #define GFX_BASE 0x50000000 43 #define L3_BASE 0x68000000 44 #define SMS_BASE 0x6C000000 45 #define SDRC_BASE 0x6D000000 46 #define GPMC_BASE 0x6E000000 47 #define SCM_BASE 0x48002000 48 49 /* clocks */ 50 #define CM_CLKSEL_PER (L4_BASE + 0x5040) 51 52 /* PRCM */ 53 #define CM_FCLKEN_IVA2 (L4_BASE + 0x4000) 54 #define CM_CLKEN_PLL_IVA2 (L4_BASE + 0x4004) 55 #define CM_IDLEST_PLL_IVA2 (L4_BASE + 0x4024) 56 #define CM_CLKSEL1_PLL_IVA2 (L4_BASE + 0x4040) 57 #define CM_CLKSEL2_PLL_IVA2 (L4_BASE + 0x4044) 58 #define CM_CLKEN_PLL_MPU (L4_BASE + 0x4904) 59 #define CM_IDLEST_PLL_MPU (L4_BASE + 0x4924) 60 #define CM_CLKSEL1_PLL_MPU (L4_BASE + 0x4940) 61 #define CM_CLKSEL2_PLL_MPU (L4_BASE + 0x4944) 62 #define CM_FCLKEN1_CORE (L4_BASE + 0x4a00) 63 #define CM_ICLKEN1_CORE (L4_BASE + 0x4a10) 64 #define CM_ICLKEN2_CORE (L4_BASE + 0x4a14) 65 #define CM_CLKSEL_CORE (L4_BASE + 0x4a40) 66 #define CM_FCLKEN_GFX (L4_BASE + 0x4b00) 67 #define CM_ICLKEN_GFX (L4_BASE + 0x4b10) 68 #define CM_CLKSEL_GFX (L4_BASE + 0x4b40) 69 #define CM_FCLKEN_WKUP (L4_BASE + 0x4c00) 70 #define CM_ICLKEN_WKUP (L4_BASE + 0x4c10) 71 #define CM_CLKSEL_WKUP (L4_BASE + 0x4c40) 72 #define CM_IDLEST_WKUP (L4_BASE + 0x4c20) 73 #define CM_CLKEN_PLL (L4_BASE + 0x4d00) 74 #define CM_IDLEST_CKGEN (L4_BASE + 0x4d20) 75 #define CM_CLKSEL1_PLL (L4_BASE + 0x4d40) 76 #define CM_CLKSEL2_PLL (L4_BASE + 0x4d44) 77 #define CM_CLKSEL3_PLL (L4_BASE + 0x4d48) 78 #define CM_FCLKEN_DSS (L4_BASE + 0x4e00) 79 #define CM_ICLKEN_DSS (L4_BASE + 0x4e10) 80 #define CM_CLKSEL_DSS (L4_BASE + 0x4e40) 81 #define CM_FCLKEN_CAM (L4_BASE + 0x4f00) 82 #define CM_ICLKEN_CAM (L4_BASE + 0x4f10) 83 #define CM_CLKSEL_CAM (L4_BASE + 0x4F40) 84 #define CM_FCLKEN_PER (L4_BASE + 0x5000) 85 #define CM_ICLKEN_PER (L4_BASE + 0x5010) 86 #define CM_CLKSEL_PER (L4_BASE + 0x5040) 87 #define CM_CLKSEL1_EMU (L4_BASE + 0x5140) 88 89 #define PRM_CLKSEL (L4_BASE + 0x306d40) 90 #define PRM_RSTCTRL (L4_BASE + 0x307250) 91 #define PRM_CLKSRC_CTRL (L4_BASE + 0x307270) 92 93 /* General Purpose Timers */ 94 #define OMAP34XX_GPT1 (L4_BASE + 0x318000) 95 #define OMAP34XX_GPT2 (L4_BASE + 0x1032000) 96 #define OMAP34XX_GPT3 (L4_BASE + 0x1034000) 97 #define OMAP34XX_GPT4 (L4_BASE + 0x1036000) 98 #define OMAP34XX_GPT5 (L4_BASE + 0x1038000) 99 #define OMAP34XX_GPT6 (L4_BASE + 0x103A000) 100 #define OMAP34XX_GPT7 (L4_BASE + 0x103C000) 101 #define OMAP34XX_GPT8 (L4_BASE + 0x103E000) 102 #define OMAP34XX_GPT9 (L4_BASE + 0x1040000) 103 #define OMAP34XX_GPT10 (L4_BASE + 0x86000) 104 #define OMAP34XX_GPT11 (L4_BASE + 0x88000) 105 #define OMAP34XX_GPT12 (L4_BASE + 0x304000) 106 107 #define TIDR 0x00 108 #define TIOCP_CFG 0x10 109 #define TISTAT 0x14 110 #define TISR 0x18 111 #define TIER 0x1C 112 #define TWER 0x20 113 #define TCLR 0x24 114 #define TCRR 0x28 115 #define TLDR 0x2C 116 #define TTGR 0x30 117 #define TWPS 0x34 118 #define TMAR 0x38 119 #define TCAR1 0x3C 120 #define TSICR 0x40 121 #define TCAR2 0x44 122 #define TPIR 0x48 123 #define TNIR 0x4C 124 #define TCVR 0x50 125 #define TOCR 0x54 126 #define TOWR 0x58 127 128 /* WatchDog Timers (1 secure, 3 GP) */ 129 #define WD1_BASE (0x4830C000) 130 #define WD2_BASE (0x48314000) 131 #define WD3_BASE (0x49030000) 132 133 #define WIDR 0x00 134 #define WD_SYSCONFIG 0x10 135 #define WD_SYSSTATUS 0x14 136 #define WISR 0x18 137 #define WIER 0x1C 138 #define WCLR 0x24 139 #define WCRR 0x28 140 #define WLDR 0x2C 141 #define WTGR 0x30 142 #define WWPS 0x34 143 #define WSPR 0x48 144 145 #define W_PEND_WCLR (1<<0) 146 #define W_PEND_WCRR (1<<1) 147 #define W_PEND_WLDR (1<<2) 148 #define W_PEND_WTGR (1<<3) 149 #define W_PEND_WSPR (1<<4) 150 151 #define WD_UNLOCK1 0xAAAA 152 #define WD_UNLOCK2 0x5555 153 154 /* 32KTIMER */ 155 #define TIMER32K_BASE (L4_BASE + 0x320000) 156 #define TIMER32K_REV (TIMER32K_BASE + 0x00) 157 #define TIMER32K_CR (TIMER32K_BASE + 0x10) 158 159 /* UART */ 160 #define OMAP_UART1_BASE (L4_BASE + 0x6a000) 161 #define OMAP_UART2_BASE (L4_BASE + 0x6c000) 162 #define OMAP_UART3_BASE (L4_BASE + 0x01020000) 163 164 #define UART_RHR 0 165 #define UART_THR 0 166 #define UART_DLL 0 167 #define UART_IER 1 168 #define UART_DLH 1 169 #define UART_IIR 2 170 #define UART_FCR 2 171 #define UART_EFR 2 172 #define UART_LCR 3 173 #define UART_MCR 4 174 #define UART_LSR 5 175 #define UART_MSR 6 176 #define UART_TCR 6 177 #define UART_SPR 7 178 #define UART_TLR 7 179 #define UART_MDR1 8 180 #define UART_MDR2 9 181 #define UART_SFLSR 10 182 #define UART_RESUME 11 183 #define UART_TXFLL 10 184 #define UART_TXFLH 11 185 #define UART_SFREGL 12 186 #define UART_SFREGH 13 187 #define UART_RXFLL 12 188 #define UART_RXFLH 13 189 #define UART_BLR 14 190 #define UART_UASR 14 191 #define UART_ACREG 15 192 #define UART_SCR 16 193 #define UART_SSR 17 194 #define UART_EBLR 18 195 #define UART_MVR 19 196 #define UART_SYSC 20 197 198 /* MPU INTC */ 199 #define INTC_BASE (L4_BASE + 0x200000) 200 #define INTC_REVISION (INTC_BASE + 0x000) 201 #define INTC_SYSCONFIG (INTC_BASE + 0x010) 202 #define INTC_SYSSTATUS (INTC_BASE + 0x014) 203 #define INTC_SIR_IRQ (INTC_BASE + 0x040) 204 #define INTC_SIR_FIQ (INTC_BASE + 0x044) 205 #define INTC_CONTROL (INTC_BASE + 0x048) 206 #define INTC_PROTECTION (INTC_BASE + 0x04C) 207 #define INTC_IDLE (INTC_BASE + 0x050) 208 #define INTC_IRQ_PRIORITY (INTC_BASE + 0x060) 209 #define INTC_FIQ_PRIORITY (INTC_BASE + 0x064) 210 #define INTC_THRESHOLD (INTC_BASE + 0x068) 211 #define INTC_ITR(n) (INTC_BASE + 0x080 + (n) * 0x20) 212 #define INTC_MIR(n) (INTC_BASE + 0x084 + (n) * 0x20) 213 #define INTC_MIR_CLEAR(n) (INTC_BASE + 0x088 + (n) * 0x20) 214 #define INTC_MIR_SET(n) (INTC_BASE + 0x08C + (n) * 0x20) 215 #define INTC_ISR_SET(n) (INTC_BASE + 0x090 + (n) * 0x20) 216 #define INTC_ISR_CLEAR(n) (INTC_BASE + 0x094 + (n) * 0x20) 217 #define INTC_PENDING_IRQ(n) (INTC_BASE + 0x098 + (n) * 0x20) 218 #define INTC_PENDING_FIQ(n) (INTC_BASE + 0x09C + (n) * 0x20) 219 #define INTC_ILR(n) (INTC_BASE + 0x100 + (n) * 4) 220 221 /* interrupts */ 222 #define INT_VECTORS 96 223 #define GPT2_IRQ 38 224 225 /* HS USB */ 226 #define USB_HS_BASE (L4_BASE + 0xab000) 227 228 /* USB OTG */ 229 #define OTG_BASE (L4_BASE + 0xab400) 230 231 #define OTG_REVISION (OTG_BASE + 0x00) 232 #define OTG_SYSCONFIG (OTG_BASE + 0x04) 233 #define OTG_SYSSTATUS (OTG_BASE + 0x08) 234 #define OTG_INTERFSEL (OTG_BASE + 0x0C) 235 #define OTG_SIMENABLE (OTG_BASE + 0x10) 236 #define OTG_FORCESTDBY (OTG_BASE + 0x14) 237 238 /* I2C */ 239 #define I2C1_BASE (L4_BASE + 0x70000) 240 #define I2C2_BASE (L4_BASE + 0x72000) 241 #define I2C3_BASE (L4_BASE + 0x60000) 242 243 #define I2C_REV (0x00) 244 #define I2C_IE (0x04) 245 #define I2C_STAT (0x08) 246 #define I2C_WE (0x0C) 247 #define I2C_SYSS (0x10) 248 #define I2C_BUF (0x14) 249 #define I2C_CNT (0x18) 250 #define I2C_DATA (0x1C) 251 #define I2C_SYSC (0x20) 252 #define I2C_CON (0x24) 253 #define I2C_OA0 (0x28) 254 #define I2C_SA (0x2C) 255 #define I2C_PSC (0x30) 256 #define I2C_SCLL (0x34) 257 #define I2C_SCLH (0x38) 258 #define I2C_SYSTEST (0x3C) 259 #define I2C_BUFSTAT (0x40) 260 #define I2C_OA1 (0x44) 261 #define I2C_OA2 (0x48) 262 #define I2C_OA3 (0x4C) 263 #define I2C_ACTOA (0x50) 264 #define I2C_SBLOCK (0x54) 265 266 /* GPIO */ 267 #define GPIO1_BASE 0x48310000 268 #define GPIO2_BASE 0x49050000 269 #define GPIO3_BASE 0x49052000 270 #define GPIO4_BASE 0x49054000 271 #define GPIO5_BASE 0x49056000 272 #define GPIO6_BASE 0x49058000 273 274 /* (incomplete) */ 275 #define GPIO_OE 0x034 276 #define GPIO_DATAIN 0x038 277 #define GPIO_DATAOUT 0x03C 278 #define GPIO_SETDATAOUT 0x094 279 280 #endif 281 282