1 /* 2 * Copyright (c) 2012-2015 Haiku, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Alexander von Gluck, kallisti5@unixzen.com 25 */ 26 #ifndef __PLATFORM_BCM283X_H 27 #define __PLATFORM_BCM283X_H 28 29 30 #include <board_config.h> 31 32 33 #define SIZE_4K 0x00001000 34 35 /* 36 * Found in: 37 * Broadcom BCM2835 ARM Peripherals 38 * - BCM2835-ARM-Peripherals.pdf 39 */ 40 41 // Section 1.2.2 42 // These board bases should go away when we start using FDT's 43 // (all loader drivers compiled in, drivers chosen based on FDT) 44 // 45 #define BCM283X_SDRAM_BASE 0x00000000 46 #if defined(BOARD_CPU_BCM2835) 47 #define BCM283X_PERIPHERAL_BASE 0x20000000 48 #elif defined(BOARD_CPU_BCM2836) 49 #define BCM283X_PERIPHERAL_BASE 0x3f000000 50 #else 51 // This will always trigger on non-BCM arm boards 52 // Leave in until we use FDT to pick needed board drivers at runtime. 53 // We can get peripheral base from the DTB long-term 54 #define BCM283X_PERIPHERAL_BASE 0x0 55 #warning Unknown BCM283X chipset! 56 #endif 57 58 59 // Added to physical addresses to select the different cache behaviours 60 #define BCM283X_VIDEO_CORE_L1_L2_CACHED (0 << 30) 61 #define BCM283X_VIDEO_CORE_L2_COHERENT (1 << 30) 62 #define BCM283X_VIDEO_CORE_L2_CACHED (2 << 30) 63 #define BCM283X_VIDEO_CORE_UNCACHED (3 << 30) 64 65 // The highest two bits are used to select aliases to the physical memory 66 // with different cache semantic. Clearing them converts the address to 67 // physical memory as seen by ARM. 68 #define BCM283X_BUS_TO_PHYSICAL(x) (x & ~BCM283X_VIDEO_CORE_UNCACHED) 69 70 71 #define ST_BASE 0x3000 72 // System Timer, sec 12.0, page 172 73 #define DMA_BASE 0x7000 74 // DMA Controller, sec 4.2, page 39 75 #define ARM_BASE 0xB000 76 // BCM283X ARM Control Block, sec 7.5, page 112 77 #define PM_BASE 0x100000 78 // Power Management, Reset controller and Watchdog registers 79 #define GPIO_BASE 0x200000 80 // GPIO, sec 6.1, page 90 81 #define UART0_BASE 0x201000 82 // UART 0, sec 13.4, page 177 83 #define MMCI0_BASE 0x202000 84 // MMC 85 #define UART1_BASE 0x215000 86 // UART 1, sec 2.1, page 65 87 #define EMMC_BASE 0x300000 88 // eMMC interface, sec 5, page 66 89 #define SMI_BASE 0x600000 90 // SMI Base 91 #define USB_BASE 0x980000 92 // USB Controller, 15.2, page 202 93 // FB_BASE will depend on memory split 94 95 96 // 7.5, page 112 97 #define ARM_CTRL_BASE (ARM_BASE + 0x000) 98 #define ARM_CTRL_IC_BASa (ARM_BASE + 0x200) 99 // Interrupt controller 100 #define ARM_CTRL_TIMER0_1_BASE (ARM_BASE + 0x400) 101 // Timer 0 and 1 102 #define ARM_CTRL_0_SBM_BASE (ARM_BASE + 0x800) 103 // ARM Semaphores, Doorbells, and Mailboxes 104 105 #define VECT_BASE 0xFFFF0000 106 #define VECT_SIZE SIZE_4K 107 108 #define DEVICE_BASE BCM283X_PERIPHERAL_BASE 109 #define DEVICE_SIZE 0xFFFFFF 110 111 #define SDRAM_BASE BCM283X_SDRAM_BASE 112 #define SDRAM_SIZE 0x4000000 113 // 64Mb 114 115 116 /* UART */ 117 // TODO: Check these UART defines! 118 #define UART_RHR 0 119 #define UART_THR 0 120 #define UART_DLL 0 121 #define UART_IER 1 122 #define UART_DLH 1 123 #define UART_IIR 2 124 #define UART_FCR 2 125 #define UART_EFR 2 126 #define UART_LCR 3 127 #define UART_MCR 4 128 #define UART_LSR 5 129 #define UART_MSR 6 130 #define UART_TCR 6 131 #define UART_SPR 7 132 #define UART_TLR 7 133 #define UART_MDR1 8 134 #define UART_MDR2 9 135 #define UART_SFLSR 10 136 #define UART_RESUME 11 137 #define UART_TXFLL 10 138 #define UART_TXFLH 11 139 #define UART_SFREGL 12 140 #define UART_SFREGH 13 141 #define UART_RXFLL 12 142 #define UART_RXFLH 13 143 #define UART_BLR 14 144 #define UART_UASR 14 145 #define UART_ACREG 15 146 #define UART_SCR 16 147 #define UART_SSR 17 148 #define UART_EBLR 18 149 #define UART_MVR 19 150 #define UART_SYSC 20 151 152 153 /* Mailbox */ 154 #define ARM_CTRL_0_MAILBOX_BASE (ARM_CTRL_0_SBM_BASE + 0x80) 155 156 #define ARM_MAILBOX_READ 0x00 157 #define ARM_MAILBOX_STATUS 0x18 158 #define ARM_MAILBOX_WRITE 0x20 159 160 #define ARM_MAILBOX_FULL (1 << 31) 161 #define ARM_MAILBOX_EMPTY (1 << 30) 162 163 #define ARM_MAILBOX_DATA_MASK 0xfffffff0 164 #define ARM_MAILBOX_CHANNEL_MASK 0x0000000f 165 166 #define ARM_MAILBOX_CHANNEL_FRAMEBUFFER 1 167 168 #endif /* __PLATFORM_BCM283X_H */ 169