1 #ifndef _ARCH_ARM_ARM_MMU_H 2 #define _ARCH_ARM_ARM_MMU_H 3 4 /* 5 * generic arm mmu definitions 6 */ 7 8 9 /* 10 * defines for the page directory (aka Master/Section Table) 11 */ 12 13 #define MMU_L1_TYPE_COARSEPAGETABLE 0x1 14 //only type used in Haiku by now (4k pages) 15 16 // coarse pagetable entry : 17 // 18 // 31 10 9 8 5 432 10 19 // | page table address |?| domain |000|01 20 // 21 // the domain is not used so and the ? is implementation specified... have not 22 // found it in the cortex A8 reference... so I set t to 0 23 // page table must obviously be on multiple of 1KB 24 25 #define MMU_L1_TYPE_SECTION 0x2 26 //map 1MB directly instead of using a page table (not used) 27 #define MMU_L1_TYPE_FINEEPAGETABLE 0x3 28 //map 1kb pages (not used and not supported on newer ARMs) 29 30 /* 31 * L2-Page descriptors... now things get really complicated... 32 * there are three different types of pages large pages (64KB) and small(4KB) 33 * and "small extended". 34 * only small extende is used by now.... 35 * and there is a new and a old format of page table entries 36 * I will use the old format... 37 */ 38 39 #define MMU_L2_TYPE_SMALLEXT 0x3 40 // for B C and TEX see ARM arm B4-11 41 #define MMU_L2_FLAG_B 0x4 42 #define MMU_L2_FLAG_C 0x8 43 #define MMU_L2_FLAG_TEX 0 // use 0b000 as TEX 44 #define MMU_L2_FLAG_AP_RW 0x30 // allow read and write for user and system 45 // #define MMU_L2_FLAG_AP_ 46 47 48 #define MMU_L1_TABLE_SIZE (4096 * 4) 49 //4096 entries (one entry per MB) -> 16KB 50 #define MMU_L2_COARSE_TABLE_SIZE (256 * 4) 51 //256 entries (one entry per 4KB) -> 1KB 52 53 54 /* 55 * definitions for CP15 r1 56 */ 57 58 #define CR_R1_MMU 0x1 // enable MMU 59 #define CP_R1_XP 0x800000 // if XP=0 then use backwards comaptible 60 // translation tables 61 62 63 64 65 66 67 #endif /* _ARCH_ARM_ARM_MMU_H */ 68