1 /* 2 * Copyright 2010-2012 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Francois Revol 7 * Ithamar R. Adema, ithamar.adema@team-embedded.nl 8 * Alexander von Gluck, kallisti5@unixzen.com 9 */ 10 #ifndef _ARCH_ARM_ARM_MMU_H 11 #define _ARCH_ARM_ARM_MMU_H 12 13 14 /* 15 * generic arm mmu definitions 16 */ 17 18 /* 19 * L1 defines for the page directory (page table walk methods) 20 */ 21 #define ARM_MMU_L1_TYPE_FAULT 0x0 22 // MMU Fault 23 // 31 2 10 24 // | |00| 25 #define ARM_MMU_L1_TYPE_SECTION 0x2 26 // Single step table walk, 4096 entries 27 // 1024K pages, 16K consumed 28 // 31 20 19 12 11 10 9 8 5 432 10 29 // | page table address | 0? | AP |0| domain |1CB|10| 30 #define ARM_MMU_L1_TYPE_FINE 0x3 31 // Three(?) step table walk, 1024 entries 32 // 1K, 4K, 64K pages, 4K consumed 33 // 31 12 11 9 8 5 432 10 34 // | page table address | 0? | domain |100|11| 35 #define ARM_MMU_L1_TYPE_COARSE 0x1 36 // Two step table walk, 256 entries 37 // 4K(Haiku), 64K pages, 1K consumed 38 // 31 10 9 8 5 432 10 39 // | page table address |0| domain |000|01| 40 41 42 // the domain is not used so and the ? is implementation specified... have not 43 // found it in the cortex A8 reference... so I set t to 0 44 // page table must obviously be on multiple of 1KB 45 46 /* 47 * L2-Page descriptors... now things get really complicated... 48 * there are three different types of pages large pages (64KB) and small(4KB) 49 * and "small extended". 50 * only small extende is used by now.... 51 * and there is a new and a old format of page table entries 52 * I will use the old format... 53 */ 54 55 #define ARM_MMU_L2_TYPE_LARGE 0x1 56 #define ARM_MMU_L2_TYPE_SMALLEXT 0x3 57 58 /* for new format entries (cortex-a8) */ 59 #define ARM_MMU_L2_TYPE_SMALLNEW 0x2 60 61 // for B C and TEX see ARM arm B4-11 62 #define ARM_MMU_L2_FLAG_B 0x4 63 #define ARM_MMU_L2_FLAG_C 0x8 64 #define ARM_MMU_L2_FLAG_TEX 0 // use 0b000 as TEX 65 #define ARM_MMU_L2_FLAG_AP_RW 0x30 66 // allow read and write for user and system 67 68 #define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096 69 #define ARM_MMU_L1_TABLE_SIZE (ARM_MMU_L1_TABLE_ENTRY_COUNT \ 70 * sizeof(uint32)) 71 72 #define ARM_MMU_L2_COARSE_ENTRY_COUNT 256 73 #define ARM_MMU_L2_COARSE_TABLE_SIZE (ARM_MMU_L2_COARSE_ENTRY_COUNT \ 74 * sizeof(uint32)) 75 76 #define ARM_MMU_L2_FINE_ENTRY_COUNT 1024 77 #define ARM_MMU_L2_FINE_TABLE_SIZE (ARM_MMU_L2_FINE_ENTRY_COUNT \ 78 * sizeof(uint32)) 79 80 /* 81 * definitions for CP15 r1 82 */ 83 84 #define CR_R1_MMU 0x1 // enable MMU 85 #define CP_R1_XP 0x800000 86 // if XP=0 then use backwards comaptible translation tables 87 88 89 #define VADDR_TO_PDENT(va) ((va) >> 20) 90 #define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12) 91 #define VADDR_TO_PGOFF(va) ((va) & 0x0fff) 92 93 #define ARM_PDE_ADDRESS_MASK 0xfffffc00 94 #define ARM_PDE_TYPE_MASK 0x00000003 95 96 #define ARM_PTE_ADDRESS_MASK 0xfffff000 97 #define ARM_PTE_TYPE_MASK 0x00000003 98 99 #endif /* _ARCH_ARM_ARM_MMU_H */ 100