1 /* 2 ** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 ** Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_ARM_CPU_H 6 #define _KERNEL_ARCH_ARM_CPU_H 7 8 9 #define CPU_MAX_CACHE_LEVEL 8 10 #define CACHE_LINE_SIZE 64 11 // TODO: Could be 32-bits sometimes? 12 13 14 #define isb() __asm__ __volatile__("isb" : : : "memory") 15 #define dsb() __asm__ __volatile__("dsb" : : : "memory") 16 #define dmb() __asm__ __volatile__("dmb" : : : "memory") 17 18 #define set_ac() 19 #define clear_ac() 20 21 22 #ifndef _ASSEMBLER 23 24 #include <arch/arm/arch_thread_types.h> 25 #include <kernel.h> 26 27 /**! Values for arch_cpu_info.arch */ 28 enum { 29 ARCH_ARM_PRE_ARM7, 30 ARCH_ARM_v3, 31 ARCH_ARM_v4, 32 ARCH_ARM_v4T, 33 ARCH_ARM_v5, 34 ARCH_ARM_v5T, 35 ARCH_ARM_v5TE, 36 ARCH_ARM_v5TEJ, 37 ARCH_ARM_v6, 38 ARCH_ARM_v7 39 }; 40 41 typedef struct arch_cpu_info { 42 /* For a detailed interpretation of these values, 43 see "The System Control coprocessor", 44 "Main ID register" in your ARM ARM */ 45 int implementor; 46 int part_number; 47 int revision; 48 int variant; 49 int arch; 50 } arch_cpu_info; 51 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 56 extern uint32 arm_get_dfsr(void); 57 extern uint32 arm_get_ifsr(void); 58 extern addr_t arm_get_dfar(void); 59 extern addr_t arm_get_ifar(void); 60 61 extern addr_t arm_get_fp(void); 62 63 extern int mmu_read_c1(void); 64 extern int mmu_write_c1(int val); 65 66 void arch_cpu_invalidate_TLB_page(addr_t page); 67 68 static inline void 69 arch_cpu_pause(void) 70 { 71 // TODO: ARM Priority pause call 72 } 73 74 75 static inline void 76 arch_cpu_idle(void) 77 { 78 uint32 Rd = 0; 79 asm volatile("mcr p15, 0, %[c7format], c7, c0, 4" 80 : : [c7format] "r" (Rd) ); 81 } 82 83 84 #ifdef __cplusplus 85 }; 86 #endif 87 88 #endif // !_ASSEMBLER 89 90 #endif /* _KERNEL_ARCH_ARM_CPU_H */ 91