1 /* 2 ** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 ** Distributed under the terms of the Haiku License. 4 */ 5 #ifndef _KERNEL_ARCH_ARM_CPU_H 6 #define _KERNEL_ARCH_ARM_CPU_H 7 8 9 #define CPU_MAX_CACHE_LEVEL 8 10 #define CACHE_LINE_SIZE 64 11 // TODO: Could be 32-bits sometimes? 12 13 14 #ifndef _ASSEMBLER 15 16 #include <arch/arm/arch_thread_types.h> 17 #include <kernel.h> 18 19 20 /* raw exception frames */ 21 struct iframe { 22 uint32 spsr; 23 uint32 r0; 24 uint32 r1; 25 uint32 r2; 26 uint32 r3; 27 uint32 r4; 28 uint32 r5; 29 uint32 r6; 30 uint32 r7; 31 uint32 r8; 32 uint32 r9; 33 uint32 r10; 34 uint32 r11; 35 uint32 r12; 36 uint32 usr_sp; 37 uint32 usr_lr; 38 uint32 svc_sp; 39 uint32 svc_lr; 40 uint32 pc; 41 } _PACKED; 42 43 /**! Values for arch_cpu_info.arch */ 44 enum { 45 ARCH_ARM_PRE_ARM7, 46 ARCH_ARM_v3, 47 ARCH_ARM_v4, 48 ARCH_ARM_v4T, 49 ARCH_ARM_v5, 50 ARCH_ARM_v5T, 51 ARCH_ARM_v5TE, 52 ARCH_ARM_v5TEJ, 53 ARCH_ARM_v6, 54 ARCH_ARM_v7 55 }; 56 57 typedef struct arch_cpu_info { 58 /* For a detailed interpretation of these values, 59 see "The System Control coprocessor", 60 "Main ID register" in your ARM ARM */ 61 int implementor; 62 int part_number; 63 int revision; 64 int variant; 65 int arch; 66 } arch_cpu_info; 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 extern addr_t arm_get_far(void); 73 extern int32 arm_get_fsr(void); 74 extern addr_t arm_get_fp(void); 75 76 extern int mmu_read_c1(void); 77 extern int mmu_write_c1(int val); 78 79 80 static inline void 81 arch_cpu_pause(void) 82 { 83 // TODO: ARM Priority pause call 84 } 85 86 87 static inline void 88 arch_cpu_idle(void) 89 { 90 uint32 Rd = 0; 91 asm volatile("mcr p15, 0, %[c7format], c7, c0, 4" 92 : : [c7format] "r" (Rd) ); 93 } 94 95 96 #ifdef __cplusplus 97 }; 98 #endif 99 100 #endif // !_ASSEMBLER 101 102 #endif /* _KERNEL_ARCH_ARM_CPU_H */ 103