1 /* 2 ** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 ** Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_ARM_CPU_H 6 #define _KERNEL_ARCH_ARM_CPU_H 7 8 9 #define CPU_MAX_CACHE_LEVEL 8 10 #define CACHE_LINE_SIZE 64 11 // TODO: Could be 32-bits sometimes? 12 13 14 #define isb() __asm__ __volatile__("isb" : : : "memory") 15 #define dsb() __asm__ __volatile__("dsb" : : : "memory") 16 #define dmb() __asm__ __volatile__("dmb" : : : "memory") 17 18 #define set_ac() 19 #define clear_ac() 20 21 22 #ifndef _ASSEMBLER 23 24 #include <arch/arm/arch_thread_types.h> 25 #include <kernel.h> 26 27 28 /* raw exception frames */ 29 struct iframe { 30 uint32 spsr; 31 uint32 r0; 32 uint32 r1; 33 uint32 r2; 34 uint32 r3; 35 uint32 r4; 36 uint32 r5; 37 uint32 r6; 38 uint32 r7; 39 uint32 r8; 40 uint32 r9; 41 uint32 r10; 42 uint32 r11; 43 uint32 r12; 44 uint32 usr_sp; 45 uint32 usr_lr; 46 uint32 svc_sp; 47 uint32 svc_lr; 48 uint32 pc; 49 } _PACKED; 50 51 /**! Values for arch_cpu_info.arch */ 52 enum { 53 ARCH_ARM_PRE_ARM7, 54 ARCH_ARM_v3, 55 ARCH_ARM_v4, 56 ARCH_ARM_v4T, 57 ARCH_ARM_v5, 58 ARCH_ARM_v5T, 59 ARCH_ARM_v5TE, 60 ARCH_ARM_v5TEJ, 61 ARCH_ARM_v6, 62 ARCH_ARM_v7 63 }; 64 65 typedef struct arch_cpu_info { 66 /* For a detailed interpretation of these values, 67 see "The System Control coprocessor", 68 "Main ID register" in your ARM ARM */ 69 int implementor; 70 int part_number; 71 int revision; 72 int variant; 73 int arch; 74 } arch_cpu_info; 75 76 #ifdef __cplusplus 77 extern "C" { 78 #endif 79 80 extern uint32 arm_get_dfsr(void); 81 extern uint32 arm_get_ifsr(void); 82 extern addr_t arm_get_dfar(void); 83 extern addr_t arm_get_ifar(void); 84 85 extern addr_t arm_get_fp(void); 86 87 extern int mmu_read_c1(void); 88 extern int mmu_write_c1(int val); 89 90 void arch_cpu_invalidate_TLB_page(addr_t page); 91 92 static inline void 93 arch_cpu_pause(void) 94 { 95 // TODO: ARM Priority pause call 96 } 97 98 99 static inline void 100 arch_cpu_idle(void) 101 { 102 uint32 Rd = 0; 103 asm volatile("mcr p15, 0, %[c7format], c7, c0, 4" 104 : : [c7format] "r" (Rd) ); 105 } 106 107 108 #ifdef __cplusplus 109 }; 110 #endif 111 112 #endif // !_ASSEMBLER 113 114 #endif /* _KERNEL_ARCH_ARM_CPU_H */ 115