1 /* 2 ** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved. 3 ** Distributed under the terms of the MIT License. 4 */ 5 #ifndef _KERNEL_ARCH_ARM_CPU_H 6 #define _KERNEL_ARCH_ARM_CPU_H 7 8 9 #define CPU_MAX_CACHE_LEVEL 8 10 #define CACHE_LINE_SIZE 64 11 // TODO: Could be 32-bits sometimes? 12 13 14 #if __ARM_ARCH__ <= 5 15 #define isb() __asm__ __volatile__("" : : : "memory") 16 #define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ 17 : : "r" (0) : "memory") 18 #define dmb() __asm__ __volatile__("" : : : "memory") 19 #elif __ARM_ARCH__ == 6 20 #define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \ 21 : : "r" (0) : "memory") 22 #define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ 23 : : "r" (0) : "memory") 24 #define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \ 25 : : "r" (0) : "memory") 26 #else /* ARMv7+ */ 27 #define isb() __asm__ __volatile__("isb" : : : "memory") 28 #define dsb() __asm__ __volatile__("dsb" : : : "memory") 29 #define dmb() __asm__ __volatile__("dmb" : : : "memory") 30 #endif 31 32 #define set_ac() 33 #define clear_ac() 34 35 36 #ifndef _ASSEMBLER 37 38 #include <arch/arm/arch_thread_types.h> 39 #include <kernel.h> 40 41 42 /* raw exception frames */ 43 struct iframe { 44 uint32 spsr; 45 uint32 r0; 46 uint32 r1; 47 uint32 r2; 48 uint32 r3; 49 uint32 r4; 50 uint32 r5; 51 uint32 r6; 52 uint32 r7; 53 uint32 r8; 54 uint32 r9; 55 uint32 r10; 56 uint32 r11; 57 uint32 r12; 58 uint32 usr_sp; 59 uint32 usr_lr; 60 uint32 svc_sp; 61 uint32 svc_lr; 62 uint32 pc; 63 } _PACKED; 64 65 /**! Values for arch_cpu_info.arch */ 66 enum { 67 ARCH_ARM_PRE_ARM7, 68 ARCH_ARM_v3, 69 ARCH_ARM_v4, 70 ARCH_ARM_v4T, 71 ARCH_ARM_v5, 72 ARCH_ARM_v5T, 73 ARCH_ARM_v5TE, 74 ARCH_ARM_v5TEJ, 75 ARCH_ARM_v6, 76 ARCH_ARM_v7 77 }; 78 79 typedef struct arch_cpu_info { 80 /* For a detailed interpretation of these values, 81 see "The System Control coprocessor", 82 "Main ID register" in your ARM ARM */ 83 int implementor; 84 int part_number; 85 int revision; 86 int variant; 87 int arch; 88 } arch_cpu_info; 89 90 #ifdef __cplusplus 91 extern "C" { 92 #endif 93 94 extern addr_t arm_get_far(void); 95 extern int32 arm_get_fsr(void); 96 extern addr_t arm_get_fp(void); 97 98 extern int mmu_read_c1(void); 99 extern int mmu_write_c1(int val); 100 101 102 static inline void 103 arch_cpu_pause(void) 104 { 105 // TODO: ARM Priority pause call 106 } 107 108 109 static inline void 110 arch_cpu_idle(void) 111 { 112 uint32 Rd = 0; 113 asm volatile("mcr p15, 0, %[c7format], c7, c0, 4" 114 : : [c7format] "r" (Rd) ); 115 } 116 117 118 #ifdef __cplusplus 119 }; 120 #endif 121 122 #endif // !_ASSEMBLER 123 124 #endif /* _KERNEL_ARCH_ARM_CPU_H */ 125