1 /* registers definitions and macros for access to them */ 2 3 /* documentation can be found at http://unichrome.sourceforge.net/ */ 4 5 /* PCI_config_space */ 6 #define ENCFG_DEVID 0x00 7 #define ENCFG_DEVCTRL 0x04 8 #define ENCFG_CLASS 0x08 9 #define ENCFG_HEADER 0x0c 10 #define ENCFG_BASE1REGS 0x10 11 #define ENCFG_BASE2FB 0x14 12 #define ENCFG_BASE3 0x18 13 #define ENCFG_BASE4 0x1c //unknown if used 14 #define ENCFG_BASE5 0x20 //unknown if used 15 #define ENCFG_BASE6 0x24 //unknown if used 16 #define ENCFG_BASE7 0x28 //unknown if used 17 #define ENCFG_SUBSYSID1 0x2c 18 #define ENCFG_ROMBASE 0x30 19 #define ENCFG_CAPPTR 0x34 20 #define ENCFG_CFG_1 0x38 //unknown if used 21 #define ENCFG_INTERRUPT 0x3c 22 #define ENCFG_SUBSYSID2 0x40 23 #define ENCFG_AGPREF 0x44 24 #define ENCFG_AGPSTAT 0x48 25 #define ENCFG_AGPCMD 0x4c 26 #define ENCFG_ROMSHADOW 0x50 27 #define ENCFG_VGA 0x54 28 #define ENCFG_SCHRATCH 0x58 29 #define ENCFG_CFG_10 0x5c 30 #define ENCFG_CFG_11 0x60 31 #define ENCFG_CFG_12 0x64 32 #define ENCFG_CFG_13 0x68 //unknown if used 33 #define ENCFG_CFG_14 0x6c //unknown if used 34 #define ENCFG_CFG_15 0x70 //unknown if used 35 #define ENCFG_CFG_16 0x74 //unknown if used 36 #define ENCFG_CFG_17 0x78 //unknown if used 37 #define ENCFG_CFG_18 0x7c //unknown if used 38 #define ENCFG_CFG_19 0x80 //unknown if used 39 #define ENCFG_CFG_20 0x84 //unknown if used 40 #define ENCFG_CFG_21 0x88 //unknown if used 41 #define ENCFG_CFG_22 0x8c //unknown if used 42 #define ENCFG_CFG_23 0x90 //unknown if used 43 #define ENCFG_CFG_24 0x94 //unknown if used 44 #define ENCFG_CFG_25 0x98 //unknown if used 45 #define ENCFG_CFG_26 0x9c //unknown if used 46 #define ENCFG_CFG_27 0xa0 //unknown if used 47 #define ENCFG_CFG_28 0xa4 //unknown if used 48 #define ENCFG_CFG_29 0xa8 //unknown if used 49 #define ENCFG_CFG_30 0xac //unknown if used 50 #define ENCFG_CFG_31 0xb0 //unknown if used 51 #define ENCFG_CFG_32 0xb4 //unknown if used 52 #define ENCFG_CFG_33 0xb8 //unknown if used 53 #define ENCFG_CFG_34 0xbc //unknown if used 54 #define ENCFG_CFG_35 0xc0 //unknown if used 55 #define ENCFG_CFG_36 0xc4 //unknown if used 56 #define ENCFG_CFG_37 0xc8 //unknown if used 57 #define ENCFG_CFG_38 0xcc //unknown if used 58 #define ENCFG_CFG_39 0xd0 //unknown if used 59 #define ENCFG_CFG_40 0xd4 //unknown if used 60 #define ENCFG_CFG_41 0xd8 //unknown if used 61 #define ENCFG_CFG_42 0xdc //unknown if used 62 #define ENCFG_CFG_43 0xe0 //unknown if used 63 #define ENCFG_CFG_44 0xe4 //unknown if used 64 #define ENCFG_CFG_45 0xe8 //unknown if used 65 #define ENCFG_CFG_46 0xec //unknown if used 66 #define ENCFG_CFG_47 0xf0 //unknown if used 67 #define ENCFG_CFG_48 0xf4 //unknown if used 68 #define ENCFG_CFG_49 0xf8 //unknown if used 69 #define ENCFG_CFG_50 0xfc //unknown if used 70 71 /* used INT registers for vblank */ 72 #define RG32_MAIN_INTE 0x00000140 73 #define RG32_CRTC_INTS 0x00600100 74 #define RG32_CRTC_INTE 0x00600140 75 76 /* ACCeleration registers */ 77 /* engine initialisation registers */ 78 #define ENACC_FORMATS 0x00400618 79 #define ENACC_OFFSET0 0x00400640 80 #define ENACC_OFFSET1 0x00400644 81 #define ENACC_OFFSET2 0x00400648 82 #define ENACC_OFFSET3 0x0040064c 83 #define ENACC_OFFSET4 0x00400650 84 #define ENACC_OFFSET5 0x00400654 85 #define ENACC_BBASE0 0x00400658 86 #define ENACC_BBASE1 0x0040065c 87 #define ENACC_BBASE2 0x00400660 88 #define ENACC_BBASE3 0x00400664 89 #define ENACC_NV10_BBASE4 0x00400668 90 #define ENACC_NV10_BBASE5 0x0040066c 91 #define ENACC_PITCH0 0x00400670 92 #define ENACC_PITCH1 0x00400674 93 #define ENACC_PITCH2 0x00400678 94 #define ENACC_PITCH3 0x0040067c 95 #define ENACC_PITCH4 0x00400680 96 #define ENACC_BLIMIT0 0x00400684 97 #define ENACC_BLIMIT1 0x00400688 98 #define ENACC_BLIMIT2 0x0040068c 99 #define ENACC_BLIMIT3 0x00400690 100 #define ENACC_NV10_BLIMIT4 0x00400694 101 #define ENACC_NV10_BLIMIT5 0x00400698 102 #define ENACC_BPIXEL 0x00400724 103 #define ENACC_NV20_OFFSET0 0x00400820 104 #define ENACC_NV20_OFFSET1 0x00400824 105 #define ENACC_NV20_OFFSET2 0x00400828 106 #define ENACC_NV20_OFFSET3 0x0040082c 107 #define ENACC_STRD_FMT 0x00400830 108 #define ENACC_NV20_PITCH0 0x00400850 109 #define ENACC_NV20_PITCH1 0x00400854 110 #define ENACC_NV20_PITCH2 0x00400858 111 #define ENACC_NV20_PITCH3 0x0040085c 112 #define ENACC_NV20_BLIMIT6 0x00400864 113 #define ENACC_NV20_BLIMIT7 0x00400868 114 #define ENACC_NV20_BLIMIT8 0x0040086c 115 #define ENACC_NV20_BLIMIT9 0x00400870 116 #define ENACC_NV30_WHAT 0x00400890 117 118 /* specials */ 119 #define ENACC_DEBUG0 0x00400080 120 #define ENACC_DEBUG1 0x00400084 121 #define ENACC_DEBUG2 0x00400088 122 #define ENACC_DEBUG3 0x0040008c 123 #define ENACC_NV10_DEBUG4 0x00400090 124 #define ENACC_ACC_INTS 0x00400100 125 #define ENACC_ACC_INTE 0x00400140 126 #define ENACC_NV10_CTX_CTRL 0x00400144 127 #define ENACC_STATUS 0x00400700 128 #define ENACC_NV04_SURF_TYP 0x0040070c 129 #define ENACC_NV10_SURF_TYP 0x00400710 130 #define ENACC_NV04_ACC_STAT 0x00400710 131 #define ENACC_NV10_ACC_STAT 0x00400714 132 #define ENACC_FIFO_EN 0x00400720 133 #define ENACC_PAT_SHP 0x00400810 134 #define ENACC_NV10_XFMOD0 0x00400f40 135 #define ENACC_NV10_XFMOD1 0x00400f44 136 #define ENACC_NV10_PIPEADR 0x00400f50 137 #define ENACC_NV10_PIPEDAT 0x00400f54 138 /* PGRAPH cache registers */ 139 #define ENACC_CACHE1_1 0x00400160 140 #define ENACC_CACHE1_2 0x00400180 141 #define ENACC_CACHE1_3 0x004001a0 142 #define ENACC_CACHE1_4 0x004001c0 143 #define ENACC_CACHE1_5 0x004001e0 144 #define ENACC_CACHE2_1 0x00400164 145 #define ENACC_CACHE2_2 0x00400184 146 #define ENACC_CACHE2_3 0x004001a4 147 #define ENACC_CACHE2_4 0x004001c4 148 #define ENACC_CACHE2_5 0x004001e4 149 #define ENACC_CACHE3_1 0x00400168 150 #define ENACC_CACHE3_2 0x00400188 151 #define ENACC_CACHE3_3 0x004001a8 152 #define ENACC_CACHE3_4 0x004001c8 153 #define ENACC_CACHE3_5 0x004001e8 154 #define ENACC_CACHE4_1 0x0040016c 155 #define ENACC_CACHE4_2 0x0040018c 156 #define ENACC_CACHE4_3 0x004001ac 157 #define ENACC_CACHE4_4 0x004001cc 158 #define ENACC_CACHE4_5 0x004001ec 159 #define ENACC_NV10_CACHE5_1 0x00400170 160 #define ENACC_NV04_CTX_CTRL 0x00400170 161 #define ENACC_CACHE5_2 0x00400190 162 #define ENACC_CACHE5_3 0x004001b0 163 #define ENACC_CACHE5_4 0x004001d0 164 #define ENACC_CACHE5_5 0x004001f0 165 #define ENACC_NV10_CACHE6_1 0x00400174 166 #define ENACC_CACHE6_2 0x00400194 167 #define ENACC_CACHE6_3 0x004001b4 168 #define ENACC_CACHE6_4 0x004001d4 169 #define ENACC_CACHE6_5 0x004001f4 170 #define ENACC_NV10_CACHE7_1 0x00400178 171 #define ENACC_CACHE7_2 0x00400198 172 #define ENACC_CACHE7_3 0x004001b8 173 #define ENACC_CACHE7_4 0x004001d8 174 #define ENACC_CACHE7_5 0x004001f8 175 #define ENACC_NV10_CACHE8_1 0x0040017c 176 #define ENACC_CACHE8_2 0x0040019c 177 #define ENACC_CACHE8_3 0x004001bc 178 #define ENACC_CACHE8_4 0x004001dc 179 #define ENACC_CACHE8_5 0x004001fc 180 #define ENACC_NV10_CTX_SW1 0x0040014c 181 #define ENACC_NV10_CTX_SW2 0x00400150 182 #define ENACC_NV10_CTX_SW3 0x00400154 183 #define ENACC_NV10_CTX_SW4 0x00400158 184 #define ENACC_NV10_CTX_SW5 0x0040015c 185 /* engine tile registers src */ 186 #define ENACC_NV20_FBWHAT0 0x00100200 187 #define ENACC_NV20_FBWHAT1 0x00100204 188 #define ENACC_NV10_FBTIL0AD 0x00100240 189 #define ENACC_NV10_FBTIL0ED 0x00100244 190 #define ENACC_NV10_FBTIL0PT 0x00100248 191 #define ENACC_NV10_FBTIL0ST 0x0010024c 192 #define ENACC_NV10_FBTIL1AD 0x00100250 193 #define ENACC_NV10_FBTIL1ED 0x00100254 194 #define ENACC_NV10_FBTIL1PT 0x00100258 195 #define ENACC_NV10_FBTIL1ST 0x0010025c 196 #define ENACC_NV10_FBTIL2AD 0x00100260 197 #define ENACC_NV10_FBTIL2ED 0x00100264 198 #define ENACC_NV10_FBTIL2PT 0x00100268 199 #define ENACC_NV10_FBTIL2ST 0x0010026c 200 #define ENACC_NV10_FBTIL3AD 0x00100270 201 #define ENACC_NV10_FBTIL3ED 0x00100274 202 #define ENACC_NV10_FBTIL3PT 0x00100278 203 #define ENACC_NV10_FBTIL3ST 0x0010027c 204 #define ENACC_NV10_FBTIL4AD 0x00100280 205 #define ENACC_NV10_FBTIL4ED 0x00100284 206 #define ENACC_NV10_FBTIL4PT 0x00100288 207 #define ENACC_NV10_FBTIL4ST 0x0010028c 208 #define ENACC_NV10_FBTIL5AD 0x00100290 209 #define ENACC_NV10_FBTIL5ED 0x00100294 210 #define ENACC_NV10_FBTIL5PT 0x00100298 211 #define ENACC_NV10_FBTIL5ST 0x0010029c 212 #define ENACC_NV10_FBTIL6AD 0x001002a0 213 #define ENACC_NV10_FBTIL6ED 0x001002a4 214 #define ENACC_NV10_FBTIL6PT 0x001002a8 215 #define ENACC_NV10_FBTIL6ST 0x001002ac 216 #define ENACC_NV10_FBTIL7AD 0x001002b0 217 #define ENACC_NV10_FBTIL7ED 0x001002b4 218 #define ENACC_NV10_FBTIL7PT 0x001002b8 219 #define ENACC_NV10_FBTIL7ST 0x001002bc 220 /* engine tile registers dst */ 221 #define ENACC_NV20_WHAT0 0x004009a4 222 #define ENACC_NV20_WHAT1 0x004009a8 223 #define ENACC_NV10_TIL0AD 0x00400b00 224 #define ENACC_NV10_TIL0ED 0x00400b04 225 #define ENACC_NV10_TIL0PT 0x00400b08 226 #define ENACC_NV10_TIL0ST 0x00400b0c 227 #define ENACC_NV10_TIL1AD 0x00400b10 228 #define ENACC_NV10_TIL1ED 0x00400b14 229 #define ENACC_NV10_TIL1PT 0x00400b18 230 #define ENACC_NV10_TIL1ST 0x00400b1c 231 #define ENACC_NV10_TIL2AD 0x00400b20 232 #define ENACC_NV10_TIL2ED 0x00400b24 233 #define ENACC_NV10_TIL2PT 0x00400b28 234 #define ENACC_NV10_TIL2ST 0x00400b2c 235 #define ENACC_NV10_TIL3AD 0x00400b30 236 #define ENACC_NV10_TIL3ED 0x00400b34 237 #define ENACC_NV10_TIL3PT 0x00400b38 238 #define ENACC_NV10_TIL3ST 0x00400b3c 239 #define ENACC_NV10_TIL4AD 0x00400b40 240 #define ENACC_NV10_TIL4ED 0x00400b44 241 #define ENACC_NV10_TIL4PT 0x00400b48 242 #define ENACC_NV10_TIL4ST 0x00400b4c 243 #define ENACC_NV10_TIL5AD 0x00400b50 244 #define ENACC_NV10_TIL5ED 0x00400b54 245 #define ENACC_NV10_TIL5PT 0x00400b58 246 #define ENACC_NV10_TIL5ST 0x00400b5c 247 #define ENACC_NV10_TIL6AD 0x00400b60 248 #define ENACC_NV10_TIL6ED 0x00400b64 249 #define ENACC_NV10_TIL6PT 0x00400b68 250 #define ENACC_NV10_TIL6ST 0x00400b6c 251 #define ENACC_NV10_TIL7AD 0x00400b70 252 #define ENACC_NV10_TIL7ED 0x00400b74 253 #define ENACC_NV10_TIL7PT 0x00400b78 254 #define ENACC_NV10_TIL7ST 0x00400b7c 255 /* cache setup registers */ 256 #define ENACC_PF_INTSTAT 0x00002100 257 #define ENACC_PF_INTEN 0x00002140 258 #define ENACC_PF_RAMHT 0x00002210 259 #define ENACC_PF_RAMFC 0x00002214 260 #define ENACC_PF_RAMRO 0x00002218 261 #define ENACC_PF_CACHES 0x00002500 262 #define ENACC_PF_SIZE 0x0000250c 263 #define ENACC_PF_CACH0_PSH0 0x00003000 264 #define ENACC_PF_CACH0_PUL0 0x00003050 265 #define ENACC_PF_CACH0_PUL1 0x00003054 266 #define ENACC_PF_CACH1_PSH0 0x00003200 267 #define ENACC_PF_CACH1_PSH1 0x00003204 268 #define ENACC_PF_CACH1_DMAI 0x0000322c 269 #define ENACC_PF_CACH1_PUL0 0x00003250 270 #define ENACC_PF_CACH1_PUL1 0x00003254 271 #define ENACC_PF_CACH1_HASH 0x00003258 272 /* Ptimer registers */ 273 #define ENACC_PT_INTSTAT 0x00009100 274 #define ENACC_PT_INTEN 0x00009140 275 #define ENACC_PT_NUMERATOR 0x00009200 276 #define ENACC_PT_DENOMINATR 0x00009210 277 /* used PRAMIN registers */ 278 #define ENACC_PR_CTX0_R 0x00711400 279 #define ENACC_PR_CTX1_R 0x00711404 280 #define ENACC_PR_CTX2_R 0x00711408 281 #define ENACC_PR_CTX3_R 0x0071140c 282 #define ENACC_PR_CTX0_0 0x00711420 283 #define ENACC_PR_CTX1_0 0x00711424 284 #define ENACC_PR_CTX2_0 0x00711428 285 #define ENACC_PR_CTX3_0 0x0071142c 286 #define ENACC_PR_CTX0_1 0x00711430 287 #define ENACC_PR_CTX1_1 0x00711434 288 #define ENACC_PR_CTX2_1 0x00711438 289 #define ENACC_PR_CTX3_1 0x0071143c 290 #define ENACC_PR_CTX0_2 0x00711440 291 #define ENACC_PR_CTX1_2 0x00711444 292 #define ENACC_PR_CTX2_2 0x00711448 293 #define ENACC_PR_CTX3_2 0x0071144c 294 #define ENACC_PR_CTX0_3 0x00711450 295 #define ENACC_PR_CTX1_3 0x00711454 296 #define ENACC_PR_CTX2_3 0x00711458 297 #define ENACC_PR_CTX3_3 0x0071145c 298 #define ENACC_PR_CTX0_4 0x00711460 299 #define ENACC_PR_CTX1_4 0x00711464 300 #define ENACC_PR_CTX2_4 0x00711468 301 #define ENACC_PR_CTX3_4 0x0071146c 302 #define ENACC_PR_CTX0_5 0x00711470 303 #define ENACC_PR_CTX1_5 0x00711474 304 #define ENACC_PR_CTX2_5 0x00711478 305 #define ENACC_PR_CTX3_5 0x0071147c 306 #define ENACC_PR_CTX0_6 0x00711480 307 #define ENACC_PR_CTX1_6 0x00711484 308 #define ENACC_PR_CTX2_6 0x00711488 309 #define ENACC_PR_CTX3_6 0x0071148c 310 #define ENACC_PR_CTX0_7 0x00711490 311 #define ENACC_PR_CTX1_7 0x00711494 312 #define ENACC_PR_CTX2_7 0x00711498 313 #define ENACC_PR_CTX3_7 0x0071149c 314 #define ENACC_PR_CTX0_8 0x007114a0 315 #define ENACC_PR_CTX1_8 0x007114a4 316 #define ENACC_PR_CTX2_8 0x007114a8 317 #define ENACC_PR_CTX3_8 0x007114ac 318 #define ENACC_PR_CTX0_9 0x007114b0 319 #define ENACC_PR_CTX1_9 0x007114b4 320 #define ENACC_PR_CTX2_9 0x007114b8 321 #define ENACC_PR_CTX3_9 0x007114bc 322 #define ENACC_PR_CTX0_A 0x007114c0 323 #define ENACC_PR_CTX1_A 0x007114c4 /* not used */ 324 #define ENACC_PR_CTX2_A 0x007114c8 325 #define ENACC_PR_CTX3_A 0x007114cc 326 #define ENACC_PR_CTX0_B 0x007114d0 327 #define ENACC_PR_CTX1_B 0x007114d4 328 #define ENACC_PR_CTX2_B 0x007114d8 329 #define ENACC_PR_CTX3_B 0x007114dc 330 #define ENACC_PR_CTX0_C 0x007114e0 331 #define ENACC_PR_CTX1_C 0x007114e4 332 #define ENACC_PR_CTX2_C 0x007114e8 333 #define ENACC_PR_CTX3_C 0x007114ec 334 #define ENACC_PR_CTX0_D 0x007114f0 335 #define ENACC_PR_CTX1_D 0x007114f4 336 #define ENACC_PR_CTX2_D 0x007114f8 337 #define ENACC_PR_CTX3_D 0x007114fc 338 #define ENACC_PR_CTX0_E 0x00711500 339 #define ENACC_PR_CTX1_E 0x00711504 340 #define ENACC_PR_CTX2_E 0x00711508 341 #define ENACC_PR_CTX3_E 0x0071150c 342 /* used RAMHT registers (hash-table(?)) */ 343 #define ENACC_HT_HANDL_00 0x00710000 344 #define ENACC_HT_VALUE_00 0x00710004 345 #define ENACC_HT_HANDL_01 0x00710008 346 #define ENACC_HT_VALUE_01 0x0071000c 347 #define ENACC_HT_HANDL_02 0x00710010 348 #define ENACC_HT_VALUE_02 0x00710014 349 #define ENACC_HT_HANDL_03 0x00710018 350 #define ENACC_HT_VALUE_03 0x0071001c 351 #define ENACC_HT_HANDL_04 0x00710020 352 #define ENACC_HT_VALUE_04 0x00710024 353 #define ENACC_HT_HANDL_05 0x00710028 354 #define ENACC_HT_VALUE_05 0x0071002c 355 #define ENACC_HT_HANDL_06 0x00710030 356 #define ENACC_HT_VALUE_06 0x00710034 357 #define ENACC_HT_HANDL_10 0x00710080 358 #define ENACC_HT_VALUE_10 0x00710084 359 #define ENACC_HT_HANDL_11 0x00710088 360 #define ENACC_HT_VALUE_11 0x0071008c 361 #define ENACC_HT_HANDL_12 0x00710090 362 #define ENACC_HT_VALUE_12 0x00710094 363 #define ENACC_HT_HANDL_13 0x00710098 364 #define ENACC_HT_VALUE_13 0x0071009c 365 #define ENACC_HT_HANDL_14 0x007100a0 366 #define ENACC_HT_VALUE_14 0x007100a4 367 #define ENACC_HT_HANDL_15 0x007100a8 368 #define ENACC_HT_VALUE_15 0x007100ac 369 #define ENACC_HT_HANDL_16 0x007100b0 370 #define ENACC_HT_VALUE_16 0x007100b4 371 #define ENACC_HT_HANDL_17 0x007100b8 372 #define ENACC_HT_VALUE_17 0x007100bc 373 374 /* acc engine fifo setup registers (for function_register 'mappings') */ 375 #define ENACC_FIFO_00800000 0x00800000 376 #define ENACC_FIFO_00802000 0x00802000 377 #define ENACC_FIFO_00804000 0x00804000 378 #define ENACC_FIFO_00806000 0x00806000 379 #define ENACC_FIFO_00808000 0x00808000 380 #define ENACC_FIFO_0080a000 0x0080a000 381 #define ENACC_FIFO_0080c000 0x0080c000 382 #define ENACC_FIFO_0080e000 0x0080e000 383 384 /* ROP3 registers (Raster OPeration) */ 385 #define RG16_ROP_FIFOFREE 0x00800010 /* little endian */ 386 #define ENACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ 387 388 /* clip registers */ 389 #define RG16_CLP_FIFOFREE 0x00802010 /* little endian */ 390 #define ENACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ 391 #define ENACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ 392 393 /* pattern registers */ 394 #define RG16_PAT_FIFOFREE 0x00804010 /* little endian */ 395 #define ENACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ 396 #define ENACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ 397 #define ENACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ 398 #define ENACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ 399 #define ENACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ 400 401 /* blit registers */ 402 #define RG16_BLT_FIFOFREE 0x00808010 /* little endian */ 403 #define ENACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ 404 #define ENACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ 405 #define ENACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ 406 407 /* used bitmap registers */ 408 #define RG16_BMP_FIFOFREE 0x0080a010 /* little endian */ 409 #define ENACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ 410 #define ENACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ 411 #define ENACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ 412 413 /* PCI direct registers */ 414 #define RG32_PWRUPCTRL 0x00000200 415 #define RG32_DUALHEAD_CTRL 0x000010f0//verify!!! 416 #define RG8_VSE2 0x000c03c3 417 418 /* bootstrap info registers */ 419 #define RG32_NV4STRAPINFO 0x00100000 420 #define RG32_PFB_CONFIG_0 0x00100200 421 #define RG32_PFB_CONFIG_1 0x00100204 422 #define RG32_NV10STRAPINFO 0x0010020c 423 #define RG32_FB_MRS1 0x001002c0 424 #define RG32_FB_MRS2 0x001002c8 425 #define RG32_NVSTRAPINFO2 0x00101000 426 427 /* registers needed for 'coldstart' */ 428 #define RG32_PFB_DEBUG_0 0x00100080 429 #define RG32_PFB_REFCTRL 0x00100210 430 #define RG32_COREPLL 0x00680500 431 #define RG32_MEMPLL 0x00680504 432 #define RG32_PLL_CTRL 0x00680510 433 #define RG32_COREPLL2 0x00680570 /* NV31, NV36 only */ 434 #define RG32_MEMPLL2 0x00680574 /* NV31, NV36 only */ 435 #define RG32_CONFIG 0x00600804 436 437 //new via 438 /* primary head */ 439 #define RG8_ATTRINDW 0x000083c0 440 #define RG8_ATTRDATW 0x000083c0 441 #define RG8_ATTRDATR 0x000083c1 442 #define RG8_MISCW 0x000083c2 443 #define RG8_MISCR 0x000083cc 444 #define RG8_SEQIND 0x000083c4 445 #define RG16_SEQIND 0x000083c4 446 #define RG8_SEQDAT 0x000083c5 447 #define RG8_GRPHIND 0x000083ce 448 #define RG16_GRPHIND 0x000083ce 449 #define RG8_GRPHDAT 0x000083cf 450 #define RG8_CRTCIND 0x000083d4 451 #define RG16_CRTCIND 0x000083d4 452 #define RG8_CRTCDAT 0x000083d5 453 #define RG8_INSTAT1 0x000083da 454 //end via. 455 #define RG32_NV10FBSTADD32 0x00600800 456 #define RG32_RASTER 0x00600808 457 #define RG32_NV10CURADD32 0x0060080c 458 #define RG32_CURCONF 0x00600810 459 #define RG32_PANEL_PWR 0x0060081c 460 #define RG32_FUNCSEL 0x00600860 461 462 /* secondary head */ 463 #define RG8_ATTR2INDW 0x006033c0 464 #define RG8_ATTR2DATW 0x006033c0 465 #define RG8_ATTR2DATR 0x006033c1 466 #define RG8_CRTC2IND 0x006033d4 467 #define RG16_CRTC2IND 0x006033d4 468 #define RG8_CRTC2DAT 0x006033d5 469 #define RG8_2INSTAT1 0x006033da//verify!!! 470 #define RG32_NV10FB2STADD32 0x00602800 471 #define RG32_RASTER2 0x00602808 472 #define RG32_NV10CUR2ADD32 0x0060280c 473 #define RG32_2CURCONF 0x00602810 474 #define RG32_2PANEL_PWR 0x0060281c//verify!!! 475 #define RG32_2FUNCSEL 0x00602860 476 477 /* DAC direct registers (standard VGA palette RAM registers) */ 478 /* primary head */ 479 //via new: 480 #define RG8_PALMASK 0x000083c6 481 #define RG8_PALINDR 0x000083c7 482 #define RG8_PALINDW 0x000083c8 483 #define RG8_PALDATA 0x000083c9 484 //end via new. 485 /* secondary head */ 486 #define RG8_PAL2MASK 0x006833c6 487 #define RG8_PAL2INDR 0x006833c7 488 #define RG8_PAL2INDW 0x006833c8 489 #define RG8_PAL2DATA 0x006833c9 490 491 /* PCI direct DAC registers (32bit) */ 492 /* primary head */ 493 #define ENDAC_CURPOS 0x00680300 494 #define ENDAC_PIXPLLC 0x00680508 495 #define ENDAC_PLLSEL 0x0068050c 496 #define ENDAC_OUTPUT 0x0068052c 497 #define ENDAC_PIXPLLC2 0x00680578 498 #define ENDAC_GENCTRL 0x00680600 499 #define ENDAC_TSTCTRL 0x00680608 500 #define ENDAC_TSTDATA 0x00680610 501 #define ENDAC_TV_SETUP 0x00680700 502 /* (flatpanel registers: confirmed for TNT2 and up) */ 503 #define ENDAC_FP_VDISPEND 0x00680800 504 #define ENDAC_FP_VTOTAL 0x00680804 505 #define ENDAC_FP_VCRTC 0x00680808 506 #define ENDAC_FP_VSYNC_S 0x0068080c 507 #define ENDAC_FP_VSYNC_E 0x00680810 508 #define ENDAC_FP_VVALID_S 0x00680814 509 #define ENDAC_FP_VVALID_E 0x00680818 510 #define ENDAC_FP_HDISPEND 0x00680820 511 #define ENDAC_FP_HTOTAL 0x00680824 512 #define ENDAC_FP_HCRTC 0x00680828 513 #define ENDAC_FP_HSYNC_S 0x0068082c 514 #define ENDAC_FP_HSYNC_E 0x00680830 515 #define ENDAC_FP_HVALID_S 0x00680834 516 #define ENDAC_FP_HVALID_E 0x00680838 517 #define ENDAC_FP_CHKSUM 0x00680840 518 #define ENDAC_FP_TST_CTRL 0x00680844 519 #define ENDAC_FP_TG_CTRL 0x00680848 520 #define ENDAC_FP_DEBUG0 0x00680880 521 #define ENDAC_FP_DEBUG1 0x00680884 522 #define ENDAC_FP_DEBUG2 0x00680888 523 #define ENDAC_FP_DEBUG3 0x0068088c 524 /* secondary head */ 525 #define ENDAC2_CURPOS 0x00682300 526 #define ENDAC2_PIXPLLC 0x00680520 527 #define ENDAC2_OUTPUT 0x0068252c 528 #define ENDAC2_PIXPLLC2 0x0068057c 529 #define ENDAC2_GENCTRL 0x00682600 530 #define ENDAC2_TSTCTRL 0x00682608 531 #define ENDAC2_TV_SETUP 0x00682700 //verify!!! 532 /* (flatpanel registers) */ 533 #define ENDAC2_FP_VDISPEND 0x00682800 534 #define ENDAC2_FP_VTOTAL 0x00682804 535 #define ENDAC2_FP_VCRTC 0x00682808 536 #define ENDAC2_FP_VSYNC_S 0x0068280c 537 #define ENDAC2_FP_VSYNC_E 0x00682810 538 #define ENDAC2_FP_VVALID_S 0x00682814 539 #define ENDAC2_FP_VVALID_E 0x00682818 540 #define ENDAC2_FP_HDISPEND 0x00682820 541 #define ENDAC2_FP_HTOTAL 0x00682824 542 #define ENDAC2_FP_HCRTC 0x00682828 543 #define ENDAC2_FP_HSYNC_S 0x0068282c 544 #define ENDAC2_FP_HSYNC_E 0x00682830 545 #define ENDAC2_FP_HVALID_S 0x00682834 546 #define ENDAC2_FP_HVALID_E 0x00682838 547 #define ENDAC2_FP_CHKSUM 0x00682840 548 #define ENDAC2_FP_TST_CTRL 0x00682844 549 #define ENDAC2_FP_TG_CTRL 0x00682848 550 #define ENDAC2_FP_DEBUG0 0x00682880 551 #define ENDAC2_FP_DEBUG1 0x00682884 552 #define ENDAC2_FP_DEBUG2 0x00682888 553 #define ENDAC2_FP_DEBUG3 0x0068288c 554 555 //new via 556 /* VIA CRTC indexed registers */ 557 /* VGA standard registers: */ 558 #define ENCRTCX_HTOTAL 0x00 559 #define ENCRTCX_HDISPE 0x01 560 #define ENCRTCX_HBLANKS 0x02 561 #define ENCRTCX_HBLANKE 0x03 562 #define ENCRTCX_HSYNCS 0x04 563 #define ENCRTCX_HSYNCE 0x05 564 #define ENCRTCX_VTOTAL 0x06 565 #define ENCRTCX_OVERFLOW 0x07 566 #define ENCRTCX_PRROWSCN 0x08 567 #define ENCRTCX_MAXSCLIN 0x09 568 #define ENCRTCX_VGACURCTRL 0x0a 569 #define ENCRTCX_FBSTADDH 0x0c 570 #define ENCRTCX_FBSTADDL 0x0d 571 #define ENCRTCX_PITCHL 0x13 572 #define ENCRTCX_VSYNCS 0x10 573 #define ENCRTCX_VSYNCE 0x11 574 #define ENCRTCX_VDISPE 0x12 575 #define ENCRTCX_VBLANKS 0x15 576 #define ENCRTCX_VBLANKE 0x16 577 #define ENCRTCX_MODECTL 0x17 578 #define ENCRTCX_LINECOMP 0x18 579 /* VIA specific registers: */ 580 #define ENCRTCX_0x32 0x32 581 #define ENCRTCX_HTIMEXT1 0x33 582 #define ENCRTCX_FBSTADDE 0x34 583 #define ENCRTCX_VTIMEXT_PIT 0x35 584 #define ENCRTCX_HTIMEXT2 0x36 585 #define ENCRTCX_TVTYPE 0x3b //TVtype jumper: b1=1 = PAL, else NTSC 586 //end via 587 /* Nvidia specific registers: */ 588 #define ENCRTCX_REPAINT0 0x19 589 #define ENCRTCX_REPAINT1 0x1a 590 #define ENCRTCX_FIFO 0x1b 591 #define ENCRTCX_LOCK 0x1f 592 #define ENCRTCX_FIFO_LWM 0x20 593 #define ENCRTCX_BUFFER 0x21 594 #define ENCRTCX_LSR 0x25 595 #define ENCRTCX_PIXEL 0x28 596 #define ENCRTCX_HEB 0x2d 597 #define ENCRTCX_CURCTL2 0x2f 598 #define ENCRTCX_CURCTL1 0x30 599 #define ENCRTCX_CURCTL0 0x31 600 #define ENCRTCX_LCD 0x33 601 #define ENCRTCX_RMA 0x38 602 #define ENCRTCX_INTERLACE 0x39 603 #define ENCRTCX_TREG 0x3d 604 #define ENCRTCX_EXTRA 0x41 605 #define ENCRTCX_OWNER 0x44 606 #define ENCRTCX_FP_HTIMING 0x53 607 #define ENCRTCX_FP_VTIMING 0x54 608 #define ENCRTCX_0x59 0x59 609 #define ENCRTCX_0x9f 0x9f 610 611 //new via: 612 /* VIA ATTRIBUTE indexed registers */ 613 /* VGA standard registers: */ 614 #define ENATBX_MODECTL 0x10 615 #define ENATBX_OSCANCOLOR 0x11 616 #define ENATBX_COLPLANE_EN 0x12 617 #define ENATBX_HORPIXPAN 0x13 618 #define ENATBX_COLSEL 0x14 619 #define ENATBX_0x16 0x16 620 621 /* VIA SEQUENCER indexed registers */ 622 /* VGA standard registers: */ 623 #define ENSEQX_RESET 0x00 624 #define ENSEQX_CLKMODE 0x01 625 #define ENSEQX_MAPMASK 0x02 626 #define ENSEQX_MEMMODE 0x04 627 /* VIA specific registers: */ 628 #define ENSEQX_LOCK 0x10 629 #define ENSEQX_0x14 0x14 630 #define ENSEQX_COLDEPTH 0x15 631 #define ENSEQX_FIFOWM 0x16 632 #define ENSEQX_FIFODEPTH 0x17 633 #define ENSEQX_0x18 0x18 634 #define ENSEQX_0x19 0x19 635 #define ENSEQX_MMIO_EN 0x1a 636 #define ENSEQX_0x1b 0x1b 637 #define ENSEQX_FETCHCNTLO 0x1c 638 #define ENSEQX_FETCHCNTHI 0x1d 639 #define ENSEQX_0x1e 0x1e 640 #define ENSEQX_0x1f 0x1f 641 #define ENSEQX_0x22 0x22 642 #define ENSEQX_0x23 0x23 643 #define ENSEQX_0x24 0x24 644 #define ENSEQX_0x25 0x25 645 #define ENSEQX_0x26 0x26 // ddc 646 #define ENSEQX_0x27 0x27 647 #define ENSEQX_0x28 0x28 648 #define ENSEQX_0x29 0x29 649 #define ENSEQX_0x2a 0x2a 650 #define ENSEQX_0x2b 0x2b 651 #define ENSEQX_0x2e 0x2e 652 #define ENSEQX_MSIZE_CLE266 0x34 653 #define ENSEQX_MSIZE_OTHER 0x39 654 #define ENSEQX_PLL_RESET 0x40 655 #define ENSEQX_0x44 0x44 656 #define ENSEQX_0x45 0x45 657 #define ENSEQX_PPLL_P_OTH 0x44 658 #define ENSEQX_PPLL_M_OTH 0x45 659 #define ENSEQX_PPLL_N_OTH 0x46 660 #define ENSEQX_PPLL_MP_CLE 0x46 661 #define ENSEQX_PPLL_N_CLE 0x47 662 663 /* VIA GRAPHICS indexed registers */ 664 /* VGA standard registers: */ 665 #define ENGRPHX_ENSETRESET 0x01 666 #define ENGRPHX_DATAROTATE 0x03 667 #define ENGRPHX_READMAPSEL 0x04 668 #define ENGRPHX_MODE 0x05 669 #define ENGRPHX_MISC 0x06 670 #define ENGRPHX_BITMASK 0x08 671 //end via new. 672 673 /* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ 674 #define ENBES_NV04_INTE 0x00680140 675 #define ENBES_NV04_ISCALVH 0x00680200 676 #define ENBES_NV04_CTRL_V 0x00680204 677 #define ENBES_NV04_CTRL_H 0x00680208 678 #define ENBES_NV04_OE_STATE 0x00680224 679 #define ENBES_NV04_SU_STATE 0x00680228 680 #define ENBES_NV04_RM_STATE 0x0068022c 681 #define ENBES_NV04_DSTREF 0x00680230 682 #define ENBES_NV04_DSTSIZE 0x00680234 683 #define ENBES_NV04_FIFOTHRS 0x00680238 684 #define ENBES_NV04_FIFOBURL 0x0068023c 685 #define ENBES_NV04_COLKEY 0x00680240 686 #define ENBES_NV04_GENCTRL 0x00680244 687 #define ENBES_NV04_RED_AMP 0x00680280 688 #define ENBES_NV04_GRN_AMP 0x00680284 689 #define ENBES_NV04_BLU_AMP 0x00680288 690 #define ENBES_NV04_SAT 0x0068028c 691 /* buffer 0 */ 692 #define ENBES_NV04_0BUFADR 0x0068020c 693 #define ENBES_NV04_0SRCPTCH 0x00680214 694 #define ENBES_NV04_0OFFSET 0x0068021c 695 /* buffer 1 */ 696 #define ENBES_NV04_1BUFADR 0x00680210 697 #define ENBES_NV04_1SRCPTCH 0x00680218 698 #define ENBES_NV04_1OFFSET 0x00680220 699 700 /* Nvidia BES (Back End Scaler) registers (>= NV10) */ 701 #define ENBES_NV10_INTE 0x00008140 702 #define ENBES_NV10_BUFSEL 0x00008700 703 #define ENBES_NV10_GENCTRL 0x00008704 704 #define ENBES_NV10_COLKEY 0x00008b00 705 /* buffer 0 */ 706 #define ENBES_NV10_0BUFADR 0x00008900 707 #define ENBES_NV10_0MEMMASK 0x00008908 708 #define ENBES_NV10_0BRICON 0x00008910 709 #define ENBES_NV10_0SAT 0x00008918 710 #define ENBES_NV10_0OFFSET 0x00008920 711 #define ENBES_NV10_0SRCSIZE 0x00008928 712 #define ENBES_NV10_0SRCREF 0x00008930 713 #define ENBES_NV10_0ISCALH 0x00008938 714 #define ENBES_NV10_0ISCALV 0x00008940 715 #define ENBES_NV10_0DSTREF 0x00008948 716 #define ENBES_NV10_0DSTSIZE 0x00008950 717 #define ENBES_NV10_0SRCPTCH 0x00008958 718 /* buffer 1 */ 719 #define ENBES_NV10_1BUFADR 0x00008904 720 #define ENBES_NV10_1MEMMASK 0x0000890c 721 #define ENBES_NV10_1BRICON 0x00008914 722 #define ENBES_NV10_1SAT 0x0000891c 723 #define ENBES_NV10_1OFFSET 0x00008924 724 #define ENBES_NV10_1SRCSIZE 0x0000892c 725 #define ENBES_NV10_1SRCREF 0x00008934 726 #define ENBES_NV10_1ISCALH 0x0000893c 727 #define ENBES_NV10_1ISCALV 0x00008944 728 #define ENBES_NV10_1DSTREF 0x0000894c 729 #define ENBES_NV10_1DSTSIZE 0x00008954 730 #define ENBES_NV10_1SRCPTCH 0x0000895c 731 /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ 732 #define ENBES_DEC_GENCTRL 0x00001588 733 734 //old: 735 /*MAVEN registers (<= G400) */ 736 #define ENMAV_PGM 0x3E 737 #define ENMAV_PIXPLLM 0x80 738 #define ENMAV_PIXPLLN 0x81 739 #define ENMAV_PIXPLLP 0x82 740 #define ENMAV_GAMMA1 0x83 741 #define ENMAV_GAMMA2 0x84 742 #define ENMAV_GAMMA3 0x85 743 #define ENMAV_GAMMA4 0x86 744 #define ENMAV_GAMMA5 0x87 745 #define ENMAV_GAMMA6 0x88 746 #define ENMAV_GAMMA7 0x89 747 #define ENMAV_GAMMA8 0x8A 748 #define ENMAV_GAMMA9 0x8B 749 #define ENMAV_MONSET 0x8C 750 #define ENMAV_TEST 0x8D 751 #define ENMAV_WREG_0X8E_L 0x8E 752 #define ENMAV_WREG_0X8E_H 0x8F 753 #define ENMAV_HSCALETV 0x90 754 #define ENMAV_TSCALETVL 0x91 755 #define ENMAV_TSCALETVH 0x92 756 #define ENMAV_FFILTER 0x93 757 #define ENMAV_MONEN 0x94 758 #define ENMAV_RESYNC 0x95 759 #define ENMAV_LASTLINEL 0x96 760 #define ENMAV_LASTLINEH 0x97 761 #define ENMAV_WREG_0X98_L 0x98 762 #define ENMAV_WREG_0X98_H 0x99 763 #define ENMAV_HSYNCLENL 0x9A 764 #define ENMAV_HSYNCLENH 0x9B 765 #define ENMAV_HSYNCSTRL 0x9C 766 #define ENMAV_HSYNCSTRH 0x9D 767 #define ENMAV_HDISPLAYL 0x9E 768 #define ENMAV_HDISPLAYH 0x9F 769 #define ENMAV_HTOTALL 0xA0 770 #define ENMAV_HTOTALH 0xA1 771 #define ENMAV_VSYNCLENL 0xA2 772 #define ENMAV_VSYNCLENH 0xA3 773 #define ENMAV_VSYNCSTRL 0xA4 774 #define ENMAV_VSYNCSTRH 0xA5 775 #define ENMAV_VDISPLAYL 0xA6 776 #define ENMAV_VDISPLAYH 0xA7 777 #define ENMAV_VTOTALL 0xA8 778 #define ENMAV_VTOTALH 0xA9 779 #define ENMAV_HVIDRSTL 0xAA 780 #define ENMAV_HVIDRSTH 0xAB 781 #define ENMAV_VVIDRSTL 0xAC 782 #define ENMAV_VVIDRSTH 0xAD 783 #define ENMAV_VSOMETHINGL 0xAE 784 #define ENMAV_VSOMETHINGH 0xAF 785 #define ENMAV_OUTMODE 0xB0 786 #define ENMAV_LOCK 0xB3 787 #define ENMAV_LUMA 0xB9 788 #define ENMAV_VDISPLAYTV 0xBE 789 #define ENMAV_STABLE 0xBF 790 #define ENMAV_HDISPLAYTV 0xC2 791 #define ENMAV_BREG_0XC6 0xC6 792 //end old. 793 794 //new via 795 #define ENCRTC_CURSOR_MODE 0x000002d0 796 #define ENCRTC_CURSOR_POS 0x000002d4 797 #define ENCRTC_CURSOR_ORG 0x000002d8 798 #define ENCRTC_CURSOR_BG 0x000002dc 799 #define ENCRTC_CURSOR_FG 0x000002e0 800 //end new. 801 802 /* Macros for convenient accesses to the NV chips */ 803 #define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 804 #define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 805 #define ENG_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 806 807 /* read and write to PCI config space */ 808 #define CFGR(A) (eng_pci_access.offset=ENCFG_##A, ioctl(fd,ENG_GET_PCI, &eng_pci_access,sizeof(eng_pci_access)), eng_pci_access.value) 809 #define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) 810 811 /* read and write from ISA I/O space */ 812 #define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) 813 #define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) 814 #define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data) 815 #define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data) 816 817 //new via 818 /* read and write from the dac registers */ 819 #define CRTCDR(A) (ENG_REG32(ENCRTC_##A)) 820 #define CRTCDW(A,B) (ENG_REG32(ENCRTC_##A)=B) 821 //end new. 822 823 /* read and write from the dac registers */ 824 #define DACR(A) (ENG_REG32(ENDAC_##A)) 825 #define DACW(A,B) (ENG_REG32(ENDAC_##A)=B) 826 827 /* read and write from the secondary dac registers */ 828 #define DAC2R(A) (ENG_REG32(ENDAC2_##A)) 829 #define DAC2W(A,B) (ENG_REG32(ENDAC2_##A)=B) 830 831 /* read and write from the backend scaler registers */ 832 #define BESR(A) (ENG_REG32(ENBES_##A)) 833 #define BESW(A,B) (ENG_REG32(ENBES_##A)=B) 834 835 /* read and write from CRTC indexed registers */ 836 #define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) 837 #define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) 838 839 /* read and write from second CRTC indexed registers */ 840 #define CRTC2W(A,B)(ENG_REG16(RG16_CRTC2IND) = ((ENCRTCX_##A) | ((B) << 8))) 841 #define CRTC2R(A) (ENG_REG8(RG8_CRTC2IND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTC2DAT)) 842 843 /* read and write from ATTRIBUTE indexed registers */ 844 #define ATBW(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATW) = (B)) 845 #define ATBR(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATR)) 846 847 /* read and write from ATTRIBUTE indexed registers */ 848 #define ATB2W(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATW) = (B)) 849 #define ATB2R(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATR)) 850 851 /* read and write from SEQUENCER indexed registers */ 852 #define SEQW(A,B)(ENG_REG16(RG16_SEQIND) = ((ENSEQX_##A) | ((B) << 8))) 853 #define SEQR(A) (ENG_REG8(RG8_SEQIND) = (ENSEQX_##A), ENG_REG8(RG8_SEQDAT)) 854 855 /* read and write from PCI GRAPHICS indexed registers */ 856 #define GRPHW(A,B)(ENG_REG16(RG16_GRPHIND) = ((ENGRPHX_##A) | ((B) << 8))) 857 #define GRPHR(A) (ENG_REG8(RG8_GRPHIND) = (ENGRPHX_##A), ENG_REG8(RG8_GRPHDAT)) 858 859 /* read and write from the acceleration engine registers */ 860 #define ACCR(A) (ENG_REG32(ENACC_##A)) 861 #define ACCW(A,B) (ENG_REG32(ENACC_##A)=B) 862 863 //old: 864 /* read and write from maven (<= G400) */ 865 #define MAVR(A) (i2c_maven_read (ENMAV_##A )) 866 #define MAVW(A,B) (i2c_maven_write(ENMAV_##A ,B)) 867 #define MAVRW(A) (i2c_maven_read (ENMAV_##A )|(i2c_maven_read(ENMAV_##A +1)<<8)) 868 #define MAVWW(A,B) (i2c_maven_write(ENMAV_##A ,B &0xFF),i2c_maven_write(ENMAV_##A +1,B >>8)) 869