1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-9/2004. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "skel" 22 23 /* 24 Internal driver state (also for sharing info between driver and accelerant) 25 */ 26 #if defined(__cplusplus) 27 extern "C" { 28 #endif 29 30 typedef struct { 31 sem_id sem; 32 int32 ben; 33 } benaphore; 34 35 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 36 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 37 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 38 #define DELETE_BEN(x) delete_sem(x.sem); 39 40 41 #define SKEL_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 42 43 /*dualhead extensions to flags*/ 44 #define DUALHEAD_OFF (0<<6) 45 #define DUALHEAD_CLONE (1<<6) 46 #define DUALHEAD_ON (2<<6) 47 #define DUALHEAD_SWITCH (3<<6) 48 #define DUALHEAD_BITS (3<<6) 49 #define DUALHEAD_CAPABLE (1<<8) 50 #define TV_BITS (3<<9) 51 #define TV_MON (0<<9 52 #define TV_PAL (1<<9) 53 #define TV_NTSC (2<<9) 54 #define TV_CAPABLE (1<<11) 55 #define TV_VIDEO (1<<12) 56 57 #define SKD_MOVE_CURSOR 0x00000001 58 #define SKD_PROGRAM_CLUT 0x00000002 59 #define SKD_SET_START_ADDR 0x00000004 60 #define SKD_SET_CURSOR 0x00000008 61 #define SKD_HANDLER_INSTALLED 0x80000000 62 63 enum { 64 ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 65 ENG_GET_PCI, 66 ENG_SET_PCI, 67 ENG_DEVICE_NAME, 68 ENG_RUN_INTERRUPTS, 69 ENG_GET_NTH_AGP_INFO, 70 ENG_ENABLE_AGP, 71 ENG_ISA_OUT, 72 ENG_ISA_IN 73 }; 74 75 /* max. number of overlay buffers */ 76 #define MAXBUFFERS 3 77 78 /* internal used info on overlay buffers */ 79 typedef struct 80 { 81 uint16 slopspace; 82 uint32 size; 83 } int_buf_info; 84 85 typedef struct settings { // apsed, see comments in skel.settings 86 // for driver 87 char accelerant[B_FILE_NAME_LENGTH]; 88 bool dumprom; 89 // for accelerant 90 uint32 logmask; 91 uint32 memory; 92 bool usebios; 93 bool hardcursor; 94 bool switchhead; 95 bool force_pci; 96 bool unhide_fw; 97 bool pgm_panel; 98 } settings; 99 100 /*shared info*/ 101 typedef struct { 102 /*a few ID things*/ 103 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 104 uint16 device_id; /* PCI device ID, from pci_info */ 105 uint8 revision; /* PCI device revsion, from pci_info */ 106 uint8 bus; /* PCI bus number, from pci_info */ 107 uint8 device; /* PCI device number on bus, from pci_info */ 108 uint8 function; /* PCI function number in device, from pci_info */ 109 110 /* bug workaround for 4.5.0 */ 111 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 112 uint32 * clone_bugfix_regs; 113 114 /*memory mappings*/ 115 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 116 It will be cloned into the accelerant's address 117 space. */ 118 119 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 120 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 121 area_id dma_buffer_area; /* Area assigned for dma*/ 122 123 void *framebuffer; /* As viewed from virtual memory */ 124 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 125 126 void *pseudo_dma; /* As viewed from virtual memory */ 127 128 void *dma_buffer; /* buffer for dma*/ 129 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 130 131 /*screenmode list*/ 132 area_id mode_area; /* Contains the list of display modes the driver supports */ 133 uint32 mode_count; /* Number of display modes in the list */ 134 135 /*flags - used by driver*/ 136 uint32 flags; 137 138 /*vblank semaphore*/ 139 sem_id vblank; /* The vertical blank semaphore. Ownership will be 140 transfered to the team opening the device first */ 141 /*cursor information*/ 142 struct { 143 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 144 uint16 hot_y; /* is 0,0 */ 145 uint16 x; /* The location of the cursor hot spot on the */ 146 uint16 y; /* desktop */ 147 uint16 width; /* Width and height of the cursor shape (always 16!) */ 148 uint16 height; 149 bool is_visible; /* Is the cursor currently displayed? */ 150 bool dh_right; /* Is cursor on right side of stretched screen? */ 151 } cursor; 152 153 /*colour lookup table*/ 154 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 155 156 /*more display mode stuff*/ 157 display_mode dm; /* current display mode configuration: head1 */ 158 display_mode dm2; /* current display mode configuration: head2 */ 159 bool acc_mode; /* signals (non)accelerated mode */ 160 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 161 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 162 163 /*frame buffer config - for BDirectScreen*/ 164 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 165 frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ 166 167 /*acceleration engine*/ 168 struct { 169 uint32 count; /* last dwgsync slot used */ 170 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 171 benaphore lock; /* for serializing access to the acceleration engine */ 172 } engine; 173 174 /* card info - information gathered from PINS (and other sources) */ 175 enum 176 { // card_type in order of date of NV chip design 177 NV04 = 0, 178 NV05, 179 NV05M64, 180 NV06, 181 NV10, 182 NV11, 183 NV11M, 184 NV15, 185 NV17, 186 NV17M, 187 NV18, 188 NV18M, 189 NV20, 190 NV25, 191 NV28, 192 NV30, 193 NV31, 194 NV34, 195 NV35, 196 NV36, 197 NV38, 198 NV40, 199 NV41, 200 NV43, 201 NV45 202 }; 203 enum 204 { // card_arch in order of date of NV chip design 205 NV04A = 0, 206 NV10A, 207 NV20A, 208 NV30A, 209 NV40A 210 }; 211 enum 212 { // tvout_chip_type in order of capability (more or less) 213 NONE = 0, 214 CH7003, 215 CH7004, 216 CH7005, 217 CH7006, 218 CH7007, 219 CH7008, 220 SAA7102, 221 SAA7103, 222 SAA7104, 223 SAA7105, 224 BT868, 225 BT869, 226 CX25870, 227 CX25871, 228 NVIDIA 229 }; 230 231 struct 232 { 233 /* specialised registers for card initialisation read from NV BIOS (pins) */ 234 235 /* general card information */ 236 uint32 card_type; /* see card_type enum above */ 237 uint32 card_arch; /* see card_arch enum above */ 238 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 239 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 240 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 241 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 242 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 243 bool tmds1_active; /* found panel on CRTC1 that is active */ 244 bool tmds2_active; /* found panel on CRTC2 that is active */ 245 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 246 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 247 float panel1_aspect; /* panel's aspect ratio */ 248 float panel2_aspect; /* panel's aspect ratio */ 249 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 250 uint32 tvout_chip_type; /* see tvchip_type enum above */ 251 uint8 monitors; /* output devices connection matrix */ 252 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 253 254 /* PINS */ 255 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 256 bool ext_pll; /* the extended PLL contains more dividers */ 257 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 258 uint32 min_system_vco; 259 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 260 uint32 min_pixel_vco; 261 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 262 uint32 min_video_vco; 263 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 264 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 265 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 266 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 267 uint32 max_dac1_clock_16; 268 uint32 max_dac1_clock_24; 269 uint32 max_dac1_clock_32; 270 uint32 max_dac1_clock_32dh; 271 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 272 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 273 uint32 max_dac2_clock_16; 274 uint32 max_dac2_clock_24; 275 uint32 max_dac2_clock_32; 276 uint32 max_dac2_clock_32dh; 277 bool secondary_head; /* presence of functions */ 278 bool tvout; 279 bool primary_dvi; 280 bool secondary_dvi; 281 uint32 memory_size; /* memory (in bytes) */ 282 } ps; 283 284 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 285 uint8 rom_mirror[65536]; 286 287 /* some configuration settings from ~/config/settings/kernel/drivers/skel.settings if exists */ 288 settings settings; 289 290 struct 291 { 292 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 293 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 294 overlay_token myToken; /* scaler is free/in use */ 295 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 296 bool crtc; /* location of overlay unit */ 297 /* variables needed for virtualscreens (move_overlay()): */ 298 bool active; /* true is overlay currently in use */ 299 overlay_window ow; /* current position of overlay output window */ 300 overlay_buffer ob; /* current inputbuffer in use */ 301 overlay_view my_ov; /* current corrected view in inputbuffer */ 302 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 303 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 304 } overlay; 305 306 } shared_info; 307 308 /* Read or write a value in PCI configuration space */ 309 typedef struct { 310 uint32 magic; /* magic number to make sure the caller groks us */ 311 uint32 offset; /* Offset to read/write */ 312 uint32 size; /* Number of bytes to transfer */ 313 uint32 value; /* The value read or written */ 314 } eng_get_set_pci; 315 316 /* Set some boolean condition (like enabling or disabling interrupts) */ 317 typedef struct { 318 uint32 magic; /* magic number to make sure the caller groks us */ 319 bool do_it; /* state to set */ 320 } eng_set_bool_state; 321 322 /* Retrieve the area_id of the kernel/accelerant shared info */ 323 typedef struct { 324 uint32 magic; /* magic number to make sure the caller groks us */ 325 area_id shared_info_area; /* area_id containing the shared information */ 326 } eng_get_private_data; 327 328 /* Retrieve the device name. Usefull for when we have a file handle, but want 329 to know the device name (like when we are cloning the accelerant) */ 330 typedef struct { 331 uint32 magic; /* magic number to make sure the caller groks us */ 332 char *name; /* The name of the device, less the /dev root */ 333 } eng_device_name; 334 335 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 336 used (pre 3.x or 3.x) */ 337 typedef struct { 338 uint32 magic; /* magic number to make sure the caller groks us */ 339 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 340 uint8 index; /* device index in list of devices found */ 341 bool exist; /* we got AGP device info */ 342 agp_info agpi; /* AGP interface info of a device */ 343 } eng_nth_agp_info; 344 345 /* Execute an AGP command */ 346 typedef struct { 347 uint32 magic; /* magic number to make sure the caller groks us */ 348 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 349 uint32 cmd; /* actual command to execute */ 350 } eng_cmd_agp; 351 352 /* Read or write a value in ISA I/O space */ 353 typedef struct { 354 uint32 magic; /* magic number to make sure the caller groks us */ 355 uint16 adress; /* Offset to read/write */ 356 uint8 size; /* Number of bytes to transfer */ 357 uint16 data; /* The value read or written */ 358 } eng_in_out_isa; 359 360 enum { 361 362 _WAIT_FOR_VBLANK = (1 << 0) 363 }; 364 365 #if defined(__cplusplus) 366 } 367 #endif 368 369 370 #endif 371