1 /* 2 Copyright 2007-2008 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Authors: 6 Gerald Zajac 2007-2008 7 */ 8 9 #ifndef DRIVERINTERFACE_H 10 #define DRIVERINTERFACE_H 11 12 13 #include <Accelerant.h> 14 #include <GraphicsDefs.h> 15 #include <Drivers.h> 16 #include <edid.h> 17 18 19 // This file contains info that is shared between the kernel driver and the 20 // accelerant, and info that is shared among the source files of the accelerant. 21 22 23 #define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog 24 25 26 #define NUM_ELEMENTS(a) ((int)(sizeof(a) / sizeof(a[0]))) // for computing number of elements in an array 27 28 struct Benaphore { 29 sem_id sem; 30 int32 count; 31 32 status_t Init(const char* name) 33 { 34 count = 0; 35 sem = create_sem(0, name); 36 return sem < 0 ? sem : B_OK; 37 } 38 39 status_t Acquire() 40 { 41 if (atomic_add(&count, 1) > 0) 42 return acquire_sem(sem); 43 return B_OK; 44 } 45 46 status_t Release() 47 { 48 if (atomic_add(&count, -1) > 1) 49 return release_sem(sem); 50 return B_OK; 51 } 52 53 void Delete() { delete_sem(sem); } 54 }; 55 56 57 #define S3_PRIVATE_DATA_MAGIC 0x4521 // a private driver rev, of sorts 58 59 60 enum { 61 S3_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 62 S3_DEVICE_NAME, 63 S3_GET_EDID, 64 S3_GET_PIO, 65 S3_SET_PIO, 66 S3_RUN_INTERRUPTS, 67 }; 68 69 70 // Chip type numbers. These are used to group the chips into related 71 // groups. See table S3_ChipTable in driver.c 72 73 enum ChipType { 74 S3_TRIO64 = 1, 75 S3_TRIO64_VP, // Trio64V+ has same ID as Trio64 but different revision number 76 S3_TRIO64_UVP, 77 S3_TRIO64_V2, 78 Trio64ChipsEnd, 79 S3_VIRGE, 80 S3_VIRGE_VX, 81 S3_VIRGE_DXGX, 82 S3_VIRGE_GX2, 83 S3_VIRGE_MX, 84 S3_VIRGE_MXP, 85 S3_TRIO_3D, 86 S3_TRIO_3D_2X, 87 VirgeChipsEnd, 88 S3_SAVAGE_3D, 89 S3_SAVAGE_MX, 90 S3_SAVAGE4, 91 S3_PROSAVAGE, 92 S3_TWISTER, 93 S3_PROSAVAGE_DDR, 94 S3_SUPERSAVAGE, 95 S3_SAVAGE2000, 96 }; 97 98 99 #define S3_TRIO64_FAMILY(chip) (chip < Trio64ChipsEnd) 100 #define S3_VIRGE_FAMILY(chip) (chip > Trio64ChipsEnd && chip < VirgeChipsEnd) 101 #define S3_SAVAGE_FAMILY(chip) (chip > VirgeChipsEnd) 102 103 #define S3_VIRGE_GX2_SERIES(chip) (chip == S3_VIRGE_GX2 || chip == S3_TRIO_3D_2X) 104 #define S3_VIRGE_MX_SERIES(chip) (chip == S3_VIRGE_MX || chip == S3_VIRGE_MXP) 105 106 #define S3_SAVAGE_3D_SERIES(chip) ((chip == S3_SAVAGE_3D) || (chip == S3_SAVAGE_MX)) 107 #define S3_SAVAGE4_SERIES(chip) ((chip == S3_SAVAGE4) \ 108 || (chip == S3_PROSAVAGE) \ 109 || (chip == S3_TWISTER) \ 110 || (chip == S3_PROSAVAGE_DDR)) 111 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip == S3_SAVAGE_MX) \ 112 || (chip == S3_SUPERSAVAGE)) 113 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip == S3_TWISTER) \ 114 || (chip == S3_PROSAVAGE_DDR)) 115 116 117 118 enum MonitorType { 119 MT_CRT, 120 MT_LCD, // laptop LCD display 121 MT_DFP // DVI display 122 }; 123 124 125 126 struct DisplayModeEx : display_mode { 127 uint32 bpp; // bits/pixel 128 uint32 bytesPerRow; // actual number of bytes in one line/row 129 }; 130 131 132 struct SharedInfo { 133 // Device ID info. 134 uint16 vendorID; // PCI vendor ID, from pci_info 135 uint16 deviceID; // PCI device ID, from pci_info 136 uint8 revision; // PCI device revsion, from pci_info 137 uint32 chipType; // indicates group in which chip belongs (a group has similar functionality) 138 char chipName[32]; // user recognizable name of chip 139 140 bool bAccelerantInUse; // true = accelerant has been initialized 141 bool bInterruptAssigned; // card has a useable interrupt assigned to it 142 143 bool bDisableHdwCursor; // true = disable hardware cursor & use software cursor 144 bool bDisableAccelDraw; // true = disable accelerated drawing 145 146 sem_id vertBlankSem; // vertical blank semaphore; if < 0, there is no semaphore 147 148 // Memory mappings. 149 area_id regsArea; // area_id for the memory mapped registers. It will 150 // be cloned into accelerant's address space. 151 area_id videoMemArea; // video memory area_id. The addresses are shared with all teams. 152 void* videoMemAddr; // video memory addr as viewed from virtual memory 153 void* videoMemPCI; // video memory addr as viewed from the PCI bus (for DMA) 154 uint32 videoMemSize; // video memory size in bytes. 155 156 uint32 cursorOffset; // offset of cursor in video memory 157 uint32 frameBufferOffset; // offset of frame buffer in video memory 158 uint32 maxFrameBufferSize; // max available video memory for frame buffer 159 160 // Color spaces supported by current video chip/driver. 161 color_space colorSpaces[6]; 162 uint32 colorSpaceCount; // number of color spaces in array colorSpaces 163 164 // List of screen modes. 165 area_id modeArea; // area containing list of display modes the driver supports 166 uint32 modeCount; // number of display modes in the list 167 168 uint16 cursorHotX; // Cursor hot spot. Top left corner of the cursor 169 uint16 cursorHotY; // is 0,0 170 171 // Current display mode configuration, and other parameters related to 172 // current display mode. 173 DisplayModeEx displayMode; // current display mode configuration 174 int32 commonCmd; // flags common to drawing commands of current display mode 175 176 edid1_info edidInfo; 177 bool bHaveEDID; // true = EDID info from device is in edidInfo 178 179 Benaphore engineLock; // for serializing access to the acceleration engine 180 181 int mclk; 182 183 MonitorType displayType; 184 185 uint16 panelX; // laptop LCD width 186 uint16 panelY; // laptop LCD height 187 188 // Command Overflow Buffer (COB) parameters for Savage chips. 189 uint32 cobSizeIndex; // size index 190 uint32 cobOffset; // offset in video memory 191 192 uint32 globalBitmapDesc; // Global Bitmap Descriptor for BCI 193 }; 194 195 196 // Set some boolean condition (like enabling or disabling interrupts) 197 struct S3SetBoolState { 198 uint32 magic; // magic number 199 bool bEnable; // state to set 200 }; 201 202 203 // Retrieve the area_id of the kernel/accelerant shared info 204 struct S3GetPrivateData { 205 uint32 magic; // magic number 206 area_id sharedInfoArea; // ID of area containing shared information 207 }; 208 209 210 struct S3GetEDID { 211 uint32 magic; // magic number 212 edid1_raw rawEdid; // raw EDID info to obtain 213 }; 214 215 216 struct S3GetSetPIO { 217 uint32 magic; // magic number 218 uint32 offset; // offset of PIO register to read/write 219 uint32 size; // number of bytes to transfer 220 uint32 value; // value to write or value that was read 221 }; 222 223 224 #endif // DRIVERINTERFACE_H 225