1 /* 2 Copyright 2007-2008 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Authors: 6 Gerald Zajac 2007-2008 7 */ 8 9 #ifndef DRIVERINTERFACE_H 10 #define DRIVERINTERFACE_H 11 12 13 #include <Accelerant.h> 14 #include <GraphicsDefs.h> 15 #include <Drivers.h> 16 #include <edid.h> 17 18 19 // This file contains info that is shared between the kernel driver and the 20 // accelerant, and info that is shared among the source files of the accelerant. 21 22 23 #define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog 24 25 26 struct Benaphore { 27 sem_id sem; 28 int32 count; 29 30 status_t Init(const char* name) 31 { 32 count = 0; 33 sem = create_sem(0, name); 34 return sem < 0 ? sem : B_OK; 35 } 36 37 status_t Acquire() 38 { 39 if (atomic_add(&count, 1) > 0) 40 return acquire_sem(sem); 41 return B_OK; 42 } 43 44 status_t Release() 45 { 46 if (atomic_add(&count, -1) > 1) 47 return release_sem(sem); 48 return B_OK; 49 } 50 51 void Delete() { delete_sem(sem); } 52 }; 53 54 55 #define S3_PRIVATE_DATA_MAGIC 0x4521 // a private driver rev, of sorts 56 57 58 enum { 59 S3_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 60 S3_DEVICE_NAME, 61 S3_GET_EDID, 62 S3_GET_PIO, 63 S3_SET_PIO, 64 S3_RUN_INTERRUPTS, 65 }; 66 67 68 // Chip type numbers. These are used to group the chips into related 69 // groups. See table S3_ChipTable in driver.c 70 71 enum ChipType { 72 S3_TRIO64 = 1, 73 S3_TRIO64_VP, // Trio64V+ has same ID as Trio64 but different revision number 74 S3_TRIO64_UVP, 75 S3_TRIO64_V2, 76 Trio64ChipsEnd, 77 S3_VIRGE, 78 S3_VIRGE_VX, 79 S3_VIRGE_DXGX, 80 S3_VIRGE_GX2, 81 S3_VIRGE_MX, 82 S3_VIRGE_MXP, 83 S3_TRIO_3D, 84 S3_TRIO_3D_2X, 85 VirgeChipsEnd, 86 S3_SAVAGE_3D, 87 S3_SAVAGE_MX, 88 S3_SAVAGE4, 89 S3_PROSAVAGE, 90 S3_TWISTER, 91 S3_PROSAVAGE_DDR, 92 S3_SUPERSAVAGE, 93 S3_SAVAGE2000, 94 }; 95 96 97 #define S3_TRIO64_FAMILY(chip) (chip < Trio64ChipsEnd) 98 #define S3_VIRGE_FAMILY(chip) (chip > Trio64ChipsEnd && chip < VirgeChipsEnd) 99 #define S3_SAVAGE_FAMILY(chip) (chip > VirgeChipsEnd) 100 101 #define S3_VIRGE_GX2_SERIES(chip) (chip == S3_VIRGE_GX2 || chip == S3_TRIO_3D_2X) 102 #define S3_VIRGE_MX_SERIES(chip) (chip == S3_VIRGE_MX || chip == S3_VIRGE_MXP) 103 104 #define S3_SAVAGE_3D_SERIES(chip) ((chip == S3_SAVAGE_3D) || (chip == S3_SAVAGE_MX)) 105 #define S3_SAVAGE4_SERIES(chip) ((chip == S3_SAVAGE4) \ 106 || (chip == S3_PROSAVAGE) \ 107 || (chip == S3_TWISTER) \ 108 || (chip == S3_PROSAVAGE_DDR)) 109 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip == S3_SAVAGE_MX) \ 110 || (chip == S3_SUPERSAVAGE)) 111 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip == S3_TWISTER) \ 112 || (chip == S3_PROSAVAGE_DDR)) 113 114 115 116 enum MonitorType { 117 MT_CRT, 118 MT_LCD, // laptop LCD display 119 MT_DFP // DVI display 120 }; 121 122 123 124 struct DisplayModeEx : display_mode { 125 uint32 bpp; // bits/pixel 126 uint32 bytesPerRow; // actual number of bytes in one line/row 127 }; 128 129 130 struct SharedInfo { 131 // Device ID info. 132 uint16 vendorID; // PCI vendor ID, from pci_info 133 uint16 deviceID; // PCI device ID, from pci_info 134 uint8 revision; // PCI device revsion, from pci_info 135 uint32 chipType; // indicates group in which chip belongs (a group has similar functionality) 136 char chipName[32]; // user recognizable name of chip 137 138 bool bAccelerantInUse; // true = accelerant has been initialized 139 bool bInterruptAssigned; // card has a useable interrupt assigned to it 140 141 bool bDisableHdwCursor; // true = disable hardware cursor & use software cursor 142 bool bDisableAccelDraw; // true = disable accelerated drawing 143 144 sem_id vertBlankSem; // vertical blank semaphore; if < 0, there is no semaphore 145 146 // Memory mappings. 147 area_id regsArea; // area_id for the memory mapped registers. It will 148 // be cloned into accelerant's address space. 149 area_id videoMemArea; // video memory area_id. The addresses are shared with all teams. 150 void* videoMemAddr; // video memory addr as viewed from virtual memory 151 void* videoMemPCI; // video memory addr as viewed from the PCI bus (for DMA) 152 uint32 videoMemSize; // video memory size in bytes. 153 154 uint32 cursorOffset; // offset of cursor in video memory 155 uint32 frameBufferOffset; // offset of frame buffer in video memory 156 uint32 maxFrameBufferSize; // max available video memory for frame buffer 157 158 // Color spaces supported by current video chip/driver. 159 color_space colorSpaces[6]; 160 uint32 colorSpaceCount; // number of color spaces in array colorSpaces 161 162 // List of screen modes. 163 area_id modeArea; // area containing list of display modes the driver supports 164 uint32 modeCount; // number of display modes in the list 165 166 uint16 cursorHotX; // Cursor hot spot. Top left corner of the cursor 167 uint16 cursorHotY; // is 0,0 168 169 // Current display mode configuration, and other parameters related to 170 // current display mode. 171 DisplayModeEx displayMode; // current display mode configuration 172 int32 commonCmd; // flags common to drawing commands of current display mode 173 174 edid1_info edidInfo; 175 bool bHaveEDID; // true = EDID info from device is in edidInfo 176 177 Benaphore engineLock; // for serializing access to the acceleration engine 178 179 int mclk; 180 181 MonitorType displayType; 182 183 uint16 panelX; // laptop LCD width 184 uint16 panelY; // laptop LCD height 185 186 // Command Overflow Buffer (COB) parameters for Savage chips. 187 uint32 cobSizeIndex; // size index 188 uint32 cobOffset; // offset in video memory 189 190 uint32 globalBitmapDesc; // Global Bitmap Descriptor for BCI 191 }; 192 193 194 // Set some boolean condition (like enabling or disabling interrupts) 195 struct S3SetBoolState { 196 uint32 magic; // magic number 197 bool bEnable; // state to set 198 }; 199 200 201 // Retrieve the area_id of the kernel/accelerant shared info 202 struct S3GetPrivateData { 203 uint32 magic; // magic number 204 area_id sharedInfoArea; // ID of area containing shared information 205 }; 206 207 208 struct S3GetEDID { 209 uint32 magic; // magic number 210 edid1_raw rawEdid; // raw EDID info to obtain 211 }; 212 213 214 struct S3GetSetPIO { 215 uint32 magic; // magic number 216 uint32 offset; // offset of PIO register to read/write 217 uint32 size; // number of bytes to transfer 218 uint32 value; // value to write or value that was read 219 }; 220 221 222 #endif // DRIVERINTERFACE_H 223