1 /* 2 Copyright 2007-2008 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Other authors: 6 Gerald Zajac 2007-2008 7 */ 8 9 #ifndef DRIVERINTERFACE_H 10 #define DRIVERINTERFACE_H 11 12 13 #include <Accelerant.h> 14 #include <GraphicsDefs.h> 15 #include <Drivers.h> 16 #include <edid.h> 17 18 19 // This is the info that needs to be shared between the kernel driver and 20 // the accelerant for the sample driver. 21 22 #if defined(__cplusplus) 23 extern "C" { 24 #endif 25 26 #define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog 27 28 29 #define NUM_ELEMENTS(a) ((int)(sizeof(a) / sizeof(a[0]))) // for computing number of elements in an array 30 31 struct benaphore { 32 sem_id sem; 33 int32 ben; 34 }; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "S3 "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define S3_PRIVATE_DATA_MAGIC 0x4521 // a private driver rev, of sorts 43 44 45 enum { 46 S3_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 47 S3_DEVICE_NAME, 48 S3_GET_PIO, 49 S3_SET_PIO, 50 S3_RUN_INTERRUPTS, 51 }; 52 53 54 // Chip type numbers. These are used to group the chips into related 55 // groups. See table S3_ChipTable in driver.c 56 57 enum S3_ChipType { 58 S3_TRIO64 = 1, 59 S3_TRIO64_VP, // Trio64V+ has same ID as Trio64 but different revision number 60 S3_TRIO64_UVP, 61 S3_TRIO64_V2, 62 Trio64ChipsEnd, 63 S3_VIRGE, 64 S3_VIRGE_VX, 65 S3_VIRGE_DXGX, 66 S3_VIRGE_GX2, 67 S3_VIRGE_MX, 68 S3_VIRGE_MXP, 69 S3_TRIO_3D, 70 S3_TRIO_3D_2X, 71 VirgeChipsEnd, 72 S3_SAVAGE_3D, 73 S3_SAVAGE_MX, 74 S3_SAVAGE4, 75 S3_PROSAVAGE, 76 S3_TWISTER, 77 S3_PROSAVAGE_DDR, 78 S3_SUPERSAVAGE, 79 S3_SAVAGE2000, 80 }; 81 82 83 #define S3_TRIO64_FAMILY(chip) (chip < Trio64ChipsEnd) 84 #define S3_VIRGE_FAMILY(chip) (chip > Trio64ChipsEnd && chip < VirgeChipsEnd) 85 #define S3_SAVAGE_FAMILY(chip) (chip > VirgeChipsEnd) 86 87 #define S3_VIRGE_GX2_SERIES(chip) (chip == S3_VIRGE_GX2 || chip == S3_TRIO_3D_2X) 88 #define S3_VIRGE_MX_SERIES(chip) (chip == S3_VIRGE_MX || chip == S3_VIRGE_MXP) 89 90 #define S3_SAVAGE_3D_SERIES(chip) ((chip == S3_SAVAGE_3D) || (chip == S3_SAVAGE_MX)) 91 #define S3_SAVAGE4_SERIES(chip) ((chip == S3_SAVAGE4) \ 92 || (chip == S3_PROSAVAGE) \ 93 || (chip == S3_TWISTER) \ 94 || (chip == S3_PROSAVAGE_DDR)) 95 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip == S3_SAVAGE_MX) \ 96 || (chip == S3_SUPERSAVAGE)) 97 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip == S3_TWISTER) \ 98 || (chip == S3_PROSAVAGE_DDR)) 99 100 101 102 enum MonitorType { 103 MT_CRT, 104 MT_LCD, // laptop LCD display 105 MT_DFP // DVI display 106 }; 107 108 109 // Bitmap descriptor structures for BCI (for Savage chips) 110 struct HIGH { 111 unsigned short Stride; 112 unsigned char Bpp; 113 unsigned char ResBWTile; 114 }; 115 116 struct BMPDESC1 { 117 unsigned long Offset; 118 HIGH HighPart; 119 }; 120 121 struct BMPDESC2 { 122 unsigned long LoPart; 123 unsigned long HiPart; 124 }; 125 126 union BMPDESC { 127 BMPDESC1 bd1; 128 BMPDESC2 bd2; 129 }; 130 131 132 133 struct DisplayModeEx : display_mode { 134 uint32 bpp; // bits/pixel 135 uint32 bytesPerRow; // number of bytes in one line/row 136 }; 137 138 139 struct SharedInfo { 140 // Device ID info. 141 uint16 vendorID; // PCI vendor ID, from pci_info 142 uint16 deviceID; // PCI device ID, from pci_info 143 uint8 revision; // PCI device revsion, from pci_info 144 uint32 chipType; // indicates group in which chip belongs (a group has similar functionality) 145 char chipName[32]; // user recognizable name of chip 146 147 bool bAccelerantInUse; // true = accelerant has been initialized 148 bool bInterruptAssigned; // card has a useable interrupt assigned to it 149 150 sem_id vertBlankSem; // vertical blank semaphore; if < 0, there is no semaphore 151 152 // Memory mappings. 153 area_id regsArea; // area_id for the memory mapped registers. It will 154 // be cloned into accelerant's address space. 155 area_id videoMemArea; // video memory area_id. The addresses are shared with all teams. 156 void* videoMemAddr; // video memory addr as viewed from virtual memory 157 void* videoMemPCI; // video memory addr as viewed from the PCI bus (for DMA) 158 uint32 videoMemSize; // video memory size in bytes. 159 160 uint32 cursorOffset; // offset of cursor in video memory 161 uint32 frameBufferOffset; // offset of frame buffer in video memory 162 uint32 maxFrameBufferSize; // max available video memory for frame buffer 163 164 // Color spaces supported by current video chip/driver. 165 color_space colorSpaces[6]; 166 uint32 colorSpaceCount; // number of color spaces in array colorSpaces 167 168 // List of screen modes. 169 area_id modeArea; // area containing list of display modes the driver supports 170 uint32 modeCount; // number of display modes in the list 171 172 // Cursor info. 173 struct { 174 uint16 hot_x; // Cursor hot spot. Top left corner of the cursor 175 uint16 hot_y; // is 0,0 176 } cursor; 177 178 // Current display mode configuration, and other parameters related to 179 // current display mode. 180 DisplayModeEx displayMode; // current display mode configuration 181 int32 commonCmd; // flags common to drawing commands of current display mode 182 183 edid1_info edidInfo; 184 bool bHaveEDID; // true = EDID info from device is in edidInfo 185 186 // Acceleration engine. 187 struct { 188 uint64 count; // last fifo slot used 189 uint64 lastIdle; // last fifo slot we *know* the engine was idle after 190 benaphore lock; // for serializing access to the acceleration engine 191 } engine; 192 193 int mclk; 194 195 MonitorType displayType; 196 197 uint16 panelX; // laptop LCD width 198 uint16 panelY; // laptop LCD height 199 200 // Command Overflow Buffer (COB) parameters for Savage chips. 201 bool bDisableCOB; // enable/disable COB for Savage 4 & ProSavage 202 uint32 cobIndex; // size index 203 uint32 cobSize; // size in bytes 204 uint32 cobOffset; // offset in video memory 205 uint32 bciThresholdLo; // low and high thresholds for 206 uint32 bciThresholdHi; // shadow status update (32bit words) 207 208 BMPDESC GlobalBD; // Bitmap Descriptor for BCI 209 }; 210 211 212 // Set some boolean condition (like enabling or disabling interrupts) 213 struct S3SetBoolState { 214 uint32 magic; // magic number to make sure the caller groks us 215 bool bEnable; // state to set 216 }; 217 218 219 // Retrieve the area_id of the kernel/accelerant shared info 220 struct S3GetPrivateData { 221 uint32 magic; // magic number to make sure the caller groks us 222 area_id sharedInfoArea; // ID of area containing shared information 223 }; 224 225 226 struct S3GetSetPIO { 227 uint32 magic; // magic number to make sure the caller groks us 228 uint32 offset; // offset of PIO register to read/write 229 uint32 size; // number of bytes to transfer 230 uint32 value; // value to write or value that was read 231 }; 232 233 234 #if defined(__cplusplus) 235 } 236 #endif 237 238 #endif // DRIVERINTERFACE_H 239