1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm 18 #include "avivo_reg.h" 19 #include "r600_reg.h" 20 #include "r700_reg.h" 21 #include "evergreen_reg.h" 22 #include "si_reg.h" 23 #include "ni_reg.h" 24 25 #include <Accelerant.h> 26 #include <Drivers.h> 27 #include <edid.h> 28 #include <PCI.h> 29 30 31 #define VENDOR_ID_ATI 0x1002 32 33 // Card chipset flags 34 #define CHIP_STD (1 << 0) // Standard chipset 35 #define CHIP_X2 (1 << 1) // Dual cpu 36 #define CHIP_IGP (1 << 2) // IGP chipset 37 #define CHIP_MOBILE (1 << 3) // Mobile chipset 38 #define CHIP_DISCREET (1 << 4) // Discreet chipset 39 #define CHIP_APU (1 << 5) // APU chipset 40 41 #define DEVICE_NAME "radeon_hd" 42 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 43 44 // Used to collect EDID from boot loader 45 #define EDID_BOOT_INFO "vesa_edid/v1" 46 #define MODES_BOOT_INFO "vesa_modes/v1" 47 48 #define RHD_POWER_ON 0 49 #define RHD_POWER_RESET 1 /* off temporarily */ 50 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 51 #define RHD_POWER_UNKNOWN 3 /* initial state */ 52 53 54 // Radeon Chipsets 55 enum radeon_chipset { 56 RADEON_R420 = 0, //r400, Radeon X700-X850 57 RADEON_R423, 58 RADEON_RV410, 59 RADEON_RS400, 60 RADEON_RS480, 61 RADEON_RS600, 62 RADEON_RS690, 63 RADEON_RS740, 64 RADEON_RV515, 65 RADEON_R520, //r500, DCE 1.0 66 RADEON_RV530, // DCE 1.0 67 RADEON_RV560, // DCE 1.0 68 RADEON_RV570, // DCE 1.0 69 RADEON_R580, // DCE 1.0 70 RADEON_R600, //r600, DCE 2.0 71 RADEON_RV610, // DCE 2.0 72 RADEON_RV630, // DCE 2.0 73 RADEON_RV670, // DCE 2.0 74 RADEON_RV620, // DCE 3.0 75 RADEON_RV635, // DCE 3.0 76 RADEON_RS780, // DCE 3.0 77 RADEON_RS880, // DCE 3.0 78 RADEON_RV770, //r700, DCE 3.1 79 RADEON_RV730, // DCE 3.2 80 RADEON_RV710, // DCE 3.2 81 RADEON_RV740, // DCE 3.2 82 RADEON_CEDAR, //Evergreen, DCE 4.0 83 RADEON_REDWOOD, // DCE 4.0 84 RADEON_JUNIPER, // DCE 4.0 85 RADEON_CYPRESS, // DCE 4.0 86 RADEON_HEMLOCK, // DCE 4.0? 87 RADEON_PALM, //Fusion APU (NI), DCE 4.1 88 RADEON_SUMO, // DCE 4.1 89 RADEON_SUMO2, // DCE 4.1 90 RADEON_CAICOS, //Nothern Islands, DCE 5.0 91 RADEON_TURKS, // DCE 5.0 92 RADEON_BARTS, // DCE 5.0 93 RADEON_CAYMAN, // DCE 5.0 94 RADEON_ANTILLES, // DCE 5.0? 95 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 96 RADEON_PITCAIRN, // DCE 6.0 97 RADEON_TAHITI, // DCE 6.0 98 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 99 RADEON_OLAND, // DCE 6.4 100 RADEON_HAINAN, // NO DCE 101 RADEON_KAVERI, //Sea Islands, DCE 8.1 102 RADEON_BONAIRE, // DCE 8.2 103 RADEON_KABINI, // DCE 8.3 104 }; 105 106 107 struct ring_buffer { 108 struct lock lock; 109 uint32 register_base; 110 uint32 offset; 111 uint32 size; 112 uint32 position; 113 uint32 space_left; 114 uint8* base; 115 }; 116 117 118 struct overlay_registers; 119 120 121 struct radeon_shared_info { 122 uint32 deviceIndex; // accelerant index 123 uint32 pciID; // device pciid 124 area_id mode_list_area; // area containing display mode list 125 uint32 mode_count; 126 127 bool has_rom; // was rom mapped? 128 area_id rom_area; // area of mapped rom 129 uint32 rom_phys; // rom base location 130 uint32 rom_size; // rom size 131 uint8* rom; // cloned, memory mapped PCI ROM 132 133 display_mode current_mode; 134 uint32 bytes_per_row; 135 uint32 bits_per_pixel; 136 uint32 dpms_mode; 137 138 area_id registers_area; // area of memory mapped registers 139 uint8* status_page; 140 addr_t physical_status_page; 141 uint32 graphics_memory_size; 142 143 uint8* frame_buffer; // virtual memory mapped FB 144 area_id frame_buffer_area; // area of memory mapped FB 145 addr_t frame_buffer_phys; // card PCI BAR address of FB 146 uint32 frame_buffer_size; // FB size mapped 147 148 bool has_edid; 149 edid1_info edid_info; 150 151 struct lock accelerant_lock; 152 struct lock engine_lock; 153 154 ring_buffer primary_ring_buffer; 155 156 int32 overlay_channel_used; 157 bool overlay_active; 158 uint32 overlay_token; 159 addr_t physical_overlay_registers; 160 uint32 overlay_offset; 161 162 bool hardware_cursor_enabled; 163 sem_id vblank_sem; 164 165 uint8* cursor_memory; 166 addr_t physical_cursor_memory; 167 uint32 cursor_buffer_offset; 168 uint32 cursor_format; 169 bool cursor_visible; 170 uint16 cursor_hot_x; 171 uint16 cursor_hot_y; 172 173 char deviceName[32]; 174 uint16 chipsetID; 175 char chipsetName[16]; 176 uint32 chipsetFlags; 177 uint8 dceMajor; 178 uint8 dceMinor; 179 180 uint16 color_data[3 * 256]; // colour lookup table 181 }; 182 183 //----------------- ioctl() interface ---------------- 184 185 // magic code for ioctls 186 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 187 188 // list ioctls 189 enum { 190 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 191 192 RADEON_GET_DEVICE_NAME, 193 RADEON_ALLOCATE_GRAPHICS_MEMORY, 194 RADEON_FREE_GRAPHICS_MEMORY 195 }; 196 197 // retrieve the area_id of the kernel/accelerant shared info 198 struct radeon_get_private_data { 199 uint32 magic; // magic number 200 area_id shared_info_area; 201 }; 202 203 // allocate graphics memory 204 struct radeon_allocate_graphics_memory { 205 uint32 magic; 206 uint32 size; 207 uint32 alignment; 208 uint32 flags; 209 uint32 buffer_base; 210 }; 211 212 // free graphics memory 213 struct radeon_free_graphics_memory { 214 uint32 magic; 215 uint32 buffer_base; 216 }; 217 218 // registers 219 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 220 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 221 #define CONFIG_MEMSIZE 0x5428 // r600> 222 223 // PCI bridge memory management 224 225 // overlay 226 227 #define RADEON_OVERLAY_UPDATE 0x30000 228 #define RADEON_OVERLAY_TEST 0x30004 229 #define RADEON_OVERLAY_STATUS 0x30008 230 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 231 #define RADEON_OVERLAY_GAMMA_5 0x30010 232 #define RADEON_OVERLAY_GAMMA_4 0x30014 233 #define RADEON_OVERLAY_GAMMA_3 0x30018 234 #define RADEON_OVERLAY_GAMMA_2 0x3001c 235 #define RADEON_OVERLAY_GAMMA_1 0x30020 236 #define RADEON_OVERLAY_GAMMA_0 0x30024 237 238 struct overlay_scale { 239 uint32 _reserved0 : 3; 240 uint32 horizontal_scale_fraction : 12; 241 uint32 _reserved1 : 1; 242 uint32 horizontal_downscale_factor : 3; 243 uint32 _reserved2 : 1; 244 uint32 vertical_scale_fraction : 12; 245 }; 246 247 #define OVERLAY_FORMAT_RGB15 0x2 248 #define OVERLAY_FORMAT_RGB16 0x3 249 #define OVERLAY_FORMAT_RGB32 0x1 250 #define OVERLAY_FORMAT_YCbCr422 0x8 251 #define OVERLAY_FORMAT_YCbCr411 0x9 252 #define OVERLAY_FORMAT_YCbCr420 0xc 253 254 #define OVERLAY_MIRROR_NORMAL 0x0 255 #define OVERLAY_MIRROR_HORIZONTAL 0x1 256 #define OVERLAY_MIRROR_VERTICAL 0x2 257 258 // The real overlay registers are written to using an update buffer 259 260 struct overlay_registers { 261 uint32 buffer_rgb0; 262 uint32 buffer_rgb1; 263 uint32 buffer_u0; 264 uint32 buffer_v0; 265 uint32 buffer_u1; 266 uint32 buffer_v1; 267 // (0x18) OSTRIDE - overlay stride 268 uint16 stride_rgb; 269 uint16 stride_uv; 270 // (0x1c) YRGB_VPH - Y/RGB vertical phase 271 uint16 vertical_phase0_rgb; 272 uint16 vertical_phase1_rgb; 273 // (0x20) UV_VPH - UV vertical phase 274 uint16 vertical_phase0_uv; 275 uint16 vertical_phase1_uv; 276 // (0x24) HORZ_PH - horizontal phase 277 uint16 horizontal_phase_rgb; 278 uint16 horizontal_phase_uv; 279 // (0x28) INIT_PHS - initial phase shift 280 uint32 initial_vertical_phase0_shift_rgb0 : 4; 281 uint32 initial_vertical_phase1_shift_rgb0 : 4; 282 uint32 initial_horizontal_phase_shift_rgb0 : 4; 283 uint32 initial_vertical_phase0_shift_uv : 4; 284 uint32 initial_vertical_phase1_shift_uv : 4; 285 uint32 initial_horizontal_phase_shift_uv : 4; 286 uint32 _reserved0 : 8; 287 // (0x2c) DWINPOS - destination window position 288 uint16 window_left; 289 uint16 window_top; 290 // (0x30) DWINSZ - destination window size 291 uint16 window_width; 292 uint16 window_height; 293 // (0x34) SWIDTH - source width 294 uint16 source_width_rgb; 295 uint16 source_width_uv; 296 // (0x38) SWITDHSW - source width in 8 byte steps 297 uint16 source_bytes_per_row_rgb; 298 uint16 source_bytes_per_row_uv; 299 uint16 source_height_rgb; 300 uint16 source_height_uv; 301 overlay_scale scale_rgb; 302 overlay_scale scale_uv; 303 // (0x48) OCLRC0 - overlay color correction 0 304 uint32 brightness_correction : 8; // signed, -128 to 127 305 uint32 _reserved1 : 10; 306 uint32 contrast_correction : 9; // fixed point: 3.6 bits 307 uint32 _reserved2 : 5; 308 // (0x4c) OCLRC1 - overlay color correction 1 309 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 310 uint32 _reserved3 : 6; 311 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 312 uint32 _reserved4 : 5; 313 // (0x50) DCLRKV - destination color key value 314 uint32 color_key_blue : 8; 315 uint32 color_key_green : 8; 316 uint32 color_key_red : 8; 317 uint32 _reserved5 : 8; 318 // (0x54) DCLRKM - destination color key mask 319 uint32 color_key_mask_blue : 8; 320 uint32 color_key_mask_green : 8; 321 uint32 color_key_mask_red : 8; 322 uint32 _reserved6 : 7; 323 uint32 color_key_enabled : 1; 324 // (0x58) SCHRKVH - source chroma key high value 325 uint32 source_chroma_key_high_red : 8; 326 uint32 source_chroma_key_high_blue : 8; 327 uint32 source_chroma_key_high_green : 8; 328 uint32 _reserved7 : 8; 329 // (0x5c) SCHRKVL - source chroma key low value 330 uint32 source_chroma_key_low_red : 8; 331 uint32 source_chroma_key_low_blue : 8; 332 uint32 source_chroma_key_low_green : 8; 333 uint32 _reserved8 : 8; 334 // (0x60) SCHRKEN - source chroma key enable 335 uint32 _reserved9 : 24; 336 uint32 source_chroma_key_red_enabled : 1; 337 uint32 source_chroma_key_blue_enabled : 1; 338 uint32 source_chroma_key_green_enabled : 1; 339 uint32 _reserved10 : 5; 340 // (0x64) OCONFIG - overlay configuration 341 uint32 _reserved11 : 3; 342 uint32 color_control_output_mode : 1; 343 uint32 yuv_to_rgb_bypass : 1; 344 uint32 _reserved12 : 11; 345 uint32 gamma2_enabled : 1; 346 uint32 _reserved13 : 1; 347 uint32 select_pipe : 1; 348 uint32 slot_time : 8; 349 uint32 _reserved14 : 5; 350 // (0x68) OCOMD - overlay command 351 uint32 overlay_enabled : 1; 352 uint32 active_field : 1; 353 uint32 active_buffer : 2; 354 uint32 test_mode : 1; 355 uint32 buffer_field_mode : 1; 356 uint32 _reserved15 : 1; 357 uint32 tv_flip_field_enabled : 1; 358 uint32 _reserved16 : 1; 359 uint32 tv_flip_field_parity : 1; 360 uint32 source_format : 4; 361 uint32 ycbcr422_order : 2; 362 uint32 _reserved18 : 1; 363 uint32 mirroring_mode : 2; 364 uint32 _reserved19 : 13; 365 366 uint32 _reserved20; 367 368 uint32 start_0y; 369 uint32 start_1y; 370 uint32 start_0u; 371 uint32 start_0v; 372 uint32 start_1u; 373 uint32 start_1v; 374 uint32 _reserved21[6]; 375 #if 0 376 // (0x70) AWINPOS - alpha blend window position 377 uint32 awinpos; 378 // (0x74) AWINSZ - alpha blend window size 379 uint32 awinsz; 380 381 uint32 _reserved21[10]; 382 #endif 383 384 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 385 // the next two registers switch the usual Y/RGB vs. UV order) 386 uint16 horizontal_scale_uv; 387 uint16 horizontal_scale_rgb; 388 // (0xa4) UVSCALEV - vertical downscale 389 uint16 vertical_scale_uv; 390 uint16 vertical_scale_rgb; 391 392 uint32 _reserved22[86]; 393 394 // (0x200) polyphase filter coefficients 395 uint16 vertical_coefficients_rgb[128]; 396 uint16 horizontal_coefficients_rgb[128]; 397 398 uint32 _reserved23[64]; 399 400 // (0x500) 401 uint16 vertical_coefficients_uv[128]; 402 uint16 horizontal_coefficients_uv[128]; 403 }; 404 405 406 struct hardware_status { 407 uint32 interrupt_status_register; 408 uint32 _reserved0[3]; 409 void* primary_ring_head_storage; 410 uint32 _reserved1[3]; 411 void* secondary_ring_0_head_storage; 412 void* secondary_ring_1_head_storage; 413 uint32 _reserved2[2]; 414 void* binning_head_storage; 415 uint32 _reserved3[3]; 416 uint32 store[1008]; 417 }; 418 419 #endif /* RADEON_HD_H */ 420