1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm 18 #include "avivo_reg.h" 19 #include "r600_reg.h" 20 #include "r700_reg.h" 21 #include "evergreen_reg.h" 22 #include "si_reg.h" 23 24 #include <Accelerant.h> 25 #include <Drivers.h> 26 #include <edid.h> 27 #include <PCI.h> 28 29 30 #define VENDOR_ID_ATI 0x1002 31 32 // Card chipset flags 33 #define CHIP_STD (1 << 0) // Standard chipset 34 #define CHIP_IGP (1 << 1) // IGP chipset 35 #define CHIP_MOBILE (1 << 2) // Mobile chipset 36 #define CHIP_DISCREET (1 << 3) // Discreet chipset 37 #define CHIP_APU (1 << 4) // APU chipset 38 39 #define DEVICE_NAME "radeon_hd" 40 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 41 42 // Used to collect EDID from boot loader 43 #define EDID_BOOT_INFO "vesa_edid/v1" 44 #define MODES_BOOT_INFO "vesa_modes/v1" 45 46 #define RHD_POWER_ON 0 47 #define RHD_POWER_RESET 1 /* off temporarily */ 48 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 49 #define RHD_POWER_UNKNOWN 3 /* initial state */ 50 51 52 // Radeon Chipsets 53 enum radeon_chipset { 54 RADEON_R420 = 0, //r400, Radeon X700-X850 55 RADEON_R423, 56 RADEON_RV410, 57 RADEON_RS400, 58 RADEON_RS480, 59 RADEON_RS600, 60 RADEON_RS690, 61 RADEON_RS740, 62 RADEON_RV515, 63 RADEON_R520, //r500, Radeon X1300-X1950 64 RADEON_RV530, 65 RADEON_RV560, 66 RADEON_RV570, 67 RADEON_R580, 68 RADEON_R600, //r600, Radeon HD 2000, 3000 69 RADEON_RV610, 70 RADEON_RV630, 71 RADEON_RV670, 72 RADEON_RV620, 73 RADEON_RV635, 74 RADEON_RS780, 75 RADEON_RS880, 76 RADEON_RV770, //r700, Radeon HD 4000 77 RADEON_RV730, 78 RADEON_RV710, 79 RADEON_RV740, 80 RADEON_CEDAR, //Evergreen, Radeon HD 5000 81 RADEON_REDWOOD, 82 RADEON_JUNIPER, 83 RADEON_CYPRESS, 84 RADEON_HEMLOCK, 85 RADEON_PALM, //Fusion APU (NI), Radeon HD 6000 86 RADEON_SUMO, 87 RADEON_SUMO2, 88 RADEON_CAICOS, //Nothern Islands, Radeon HD 6000 89 RADEON_TURKS, 90 RADEON_BARTS, 91 RADEON_CAYMAN, 92 RADEON_ANTILLES, 93 RADEON_LOMBOK, //Southern Islands, Radeon HD 7000 94 RADEON_CAPEVERDE, 95 RADEON_PITCAIRN, 96 RADEON_TAHITI, 97 RADEON_NEWZEALAND 98 }; 99 100 101 struct ring_buffer { 102 struct lock lock; 103 uint32 register_base; 104 uint32 offset; 105 uint32 size; 106 uint32 position; 107 uint32 space_left; 108 uint8* base; 109 }; 110 111 112 struct overlay_registers; 113 114 115 struct radeon_shared_info { 116 uint32 deviceIndex; // accelerant index 117 uint32 pciID; // device pciid 118 area_id mode_list_area; // area containing display mode list 119 uint32 mode_count; 120 121 bool has_rom; // was rom mapped? 122 area_id rom_area; // area of mapped rom 123 uint32 rom_phys; // rom base location 124 uint32 rom_size; // rom size 125 uint8* rom; // cloned, memory mapped PCI ROM 126 127 display_mode current_mode; 128 uint32 bytes_per_row; 129 uint32 bits_per_pixel; 130 uint32 dpms_mode; 131 132 area_id registers_area; // area of memory mapped registers 133 uint8* status_page; 134 addr_t physical_status_page; 135 uint32 graphics_memory_size; 136 137 uint8* frame_buffer; // virtual memory mapped FB 138 area_id frame_buffer_area; // area of memory mapped FB 139 addr_t frame_buffer_phys; // card PCI BAR address of FB 140 uint32 frame_buffer_size; // FB size mapped 141 142 bool has_edid; 143 edid1_info edid_info; 144 145 struct lock accelerant_lock; 146 struct lock engine_lock; 147 148 ring_buffer primary_ring_buffer; 149 150 int32 overlay_channel_used; 151 bool overlay_active; 152 uint32 overlay_token; 153 addr_t physical_overlay_registers; 154 uint32 overlay_offset; 155 156 bool hardware_cursor_enabled; 157 sem_id vblank_sem; 158 159 uint8* cursor_memory; 160 addr_t physical_cursor_memory; 161 uint32 cursor_buffer_offset; 162 uint32 cursor_format; 163 bool cursor_visible; 164 uint16 cursor_hot_x; 165 uint16 cursor_hot_y; 166 167 char deviceName[32]; 168 uint16 chipsetID; 169 char chipsetName[16]; 170 uint32 chipsetFlags; 171 uint8 dceMajor; 172 uint8 dceMinor; 173 }; 174 175 //----------------- ioctl() interface ---------------- 176 177 // magic code for ioctls 178 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 179 180 // list ioctls 181 enum { 182 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 183 184 RADEON_GET_DEVICE_NAME, 185 RADEON_ALLOCATE_GRAPHICS_MEMORY, 186 RADEON_FREE_GRAPHICS_MEMORY 187 }; 188 189 // retrieve the area_id of the kernel/accelerant shared info 190 struct radeon_get_private_data { 191 uint32 magic; // magic number 192 area_id shared_info_area; 193 }; 194 195 // allocate graphics memory 196 struct radeon_allocate_graphics_memory { 197 uint32 magic; 198 uint32 size; 199 uint32 alignment; 200 uint32 flags; 201 uint32 buffer_base; 202 }; 203 204 // free graphics memory 205 struct radeon_free_graphics_memory { 206 uint32 magic; 207 uint32 buffer_base; 208 }; 209 210 // registers 211 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 212 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 213 #define CONFIG_MEMSIZE 0x5428 // r600> 214 215 // PCI bridge memory management 216 217 // overlay 218 219 #define RADEON_OVERLAY_UPDATE 0x30000 220 #define RADEON_OVERLAY_TEST 0x30004 221 #define RADEON_OVERLAY_STATUS 0x30008 222 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 223 #define RADEON_OVERLAY_GAMMA_5 0x30010 224 #define RADEON_OVERLAY_GAMMA_4 0x30014 225 #define RADEON_OVERLAY_GAMMA_3 0x30018 226 #define RADEON_OVERLAY_GAMMA_2 0x3001c 227 #define RADEON_OVERLAY_GAMMA_1 0x30020 228 #define RADEON_OVERLAY_GAMMA_0 0x30024 229 230 struct overlay_scale { 231 uint32 _reserved0 : 3; 232 uint32 horizontal_scale_fraction : 12; 233 uint32 _reserved1 : 1; 234 uint32 horizontal_downscale_factor : 3; 235 uint32 _reserved2 : 1; 236 uint32 vertical_scale_fraction : 12; 237 }; 238 239 #define OVERLAY_FORMAT_RGB15 0x2 240 #define OVERLAY_FORMAT_RGB16 0x3 241 #define OVERLAY_FORMAT_RGB32 0x1 242 #define OVERLAY_FORMAT_YCbCr422 0x8 243 #define OVERLAY_FORMAT_YCbCr411 0x9 244 #define OVERLAY_FORMAT_YCbCr420 0xc 245 246 #define OVERLAY_MIRROR_NORMAL 0x0 247 #define OVERLAY_MIRROR_HORIZONTAL 0x1 248 #define OVERLAY_MIRROR_VERTICAL 0x2 249 250 // The real overlay registers are written to using an update buffer 251 252 struct overlay_registers { 253 uint32 buffer_rgb0; 254 uint32 buffer_rgb1; 255 uint32 buffer_u0; 256 uint32 buffer_v0; 257 uint32 buffer_u1; 258 uint32 buffer_v1; 259 // (0x18) OSTRIDE - overlay stride 260 uint16 stride_rgb; 261 uint16 stride_uv; 262 // (0x1c) YRGB_VPH - Y/RGB vertical phase 263 uint16 vertical_phase0_rgb; 264 uint16 vertical_phase1_rgb; 265 // (0x20) UV_VPH - UV vertical phase 266 uint16 vertical_phase0_uv; 267 uint16 vertical_phase1_uv; 268 // (0x24) HORZ_PH - horizontal phase 269 uint16 horizontal_phase_rgb; 270 uint16 horizontal_phase_uv; 271 // (0x28) INIT_PHS - initial phase shift 272 uint32 initial_vertical_phase0_shift_rgb0 : 4; 273 uint32 initial_vertical_phase1_shift_rgb0 : 4; 274 uint32 initial_horizontal_phase_shift_rgb0 : 4; 275 uint32 initial_vertical_phase0_shift_uv : 4; 276 uint32 initial_vertical_phase1_shift_uv : 4; 277 uint32 initial_horizontal_phase_shift_uv : 4; 278 uint32 _reserved0 : 8; 279 // (0x2c) DWINPOS - destination window position 280 uint16 window_left; 281 uint16 window_top; 282 // (0x30) DWINSZ - destination window size 283 uint16 window_width; 284 uint16 window_height; 285 // (0x34) SWIDTH - source width 286 uint16 source_width_rgb; 287 uint16 source_width_uv; 288 // (0x38) SWITDHSW - source width in 8 byte steps 289 uint16 source_bytes_per_row_rgb; 290 uint16 source_bytes_per_row_uv; 291 uint16 source_height_rgb; 292 uint16 source_height_uv; 293 overlay_scale scale_rgb; 294 overlay_scale scale_uv; 295 // (0x48) OCLRC0 - overlay color correction 0 296 uint32 brightness_correction : 8; // signed, -128 to 127 297 uint32 _reserved1 : 10; 298 uint32 contrast_correction : 9; // fixed point: 3.6 bits 299 uint32 _reserved2 : 5; 300 // (0x4c) OCLRC1 - overlay color correction 1 301 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 302 uint32 _reserved3 : 6; 303 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 304 uint32 _reserved4 : 5; 305 // (0x50) DCLRKV - destination color key value 306 uint32 color_key_blue : 8; 307 uint32 color_key_green : 8; 308 uint32 color_key_red : 8; 309 uint32 _reserved5 : 8; 310 // (0x54) DCLRKM - destination color key mask 311 uint32 color_key_mask_blue : 8; 312 uint32 color_key_mask_green : 8; 313 uint32 color_key_mask_red : 8; 314 uint32 _reserved6 : 7; 315 uint32 color_key_enabled : 1; 316 // (0x58) SCHRKVH - source chroma key high value 317 uint32 source_chroma_key_high_red : 8; 318 uint32 source_chroma_key_high_blue : 8; 319 uint32 source_chroma_key_high_green : 8; 320 uint32 _reserved7 : 8; 321 // (0x5c) SCHRKVL - source chroma key low value 322 uint32 source_chroma_key_low_red : 8; 323 uint32 source_chroma_key_low_blue : 8; 324 uint32 source_chroma_key_low_green : 8; 325 uint32 _reserved8 : 8; 326 // (0x60) SCHRKEN - source chroma key enable 327 uint32 _reserved9 : 24; 328 uint32 source_chroma_key_red_enabled : 1; 329 uint32 source_chroma_key_blue_enabled : 1; 330 uint32 source_chroma_key_green_enabled : 1; 331 uint32 _reserved10 : 5; 332 // (0x64) OCONFIG - overlay configuration 333 uint32 _reserved11 : 3; 334 uint32 color_control_output_mode : 1; 335 uint32 yuv_to_rgb_bypass : 1; 336 uint32 _reserved12 : 11; 337 uint32 gamma2_enabled : 1; 338 uint32 _reserved13 : 1; 339 uint32 select_pipe : 1; 340 uint32 slot_time : 8; 341 uint32 _reserved14 : 5; 342 // (0x68) OCOMD - overlay command 343 uint32 overlay_enabled : 1; 344 uint32 active_field : 1; 345 uint32 active_buffer : 2; 346 uint32 test_mode : 1; 347 uint32 buffer_field_mode : 1; 348 uint32 _reserved15 : 1; 349 uint32 tv_flip_field_enabled : 1; 350 uint32 _reserved16 : 1; 351 uint32 tv_flip_field_parity : 1; 352 uint32 source_format : 4; 353 uint32 ycbcr422_order : 2; 354 uint32 _reserved18 : 1; 355 uint32 mirroring_mode : 2; 356 uint32 _reserved19 : 13; 357 358 uint32 _reserved20; 359 360 uint32 start_0y; 361 uint32 start_1y; 362 uint32 start_0u; 363 uint32 start_0v; 364 uint32 start_1u; 365 uint32 start_1v; 366 uint32 _reserved21[6]; 367 #if 0 368 // (0x70) AWINPOS - alpha blend window position 369 uint32 awinpos; 370 // (0x74) AWINSZ - alpha blend window size 371 uint32 awinsz; 372 373 uint32 _reserved21[10]; 374 #endif 375 376 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 377 // the next two registers switch the usual Y/RGB vs. UV order) 378 uint16 horizontal_scale_uv; 379 uint16 horizontal_scale_rgb; 380 // (0xa4) UVSCALEV - vertical downscale 381 uint16 vertical_scale_uv; 382 uint16 vertical_scale_rgb; 383 384 uint32 _reserved22[86]; 385 386 // (0x200) polyphase filter coefficients 387 uint16 vertical_coefficients_rgb[128]; 388 uint16 horizontal_coefficients_rgb[128]; 389 390 uint32 _reserved23[64]; 391 392 // (0x500) 393 uint16 vertical_coefficients_uv[128]; 394 uint16 horizontal_coefficients_uv[128]; 395 }; 396 397 398 struct hardware_status { 399 uint32 interrupt_status_register; 400 uint32 _reserved0[3]; 401 void* primary_ring_head_storage; 402 uint32 _reserved1[3]; 403 void* secondary_ring_0_head_storage; 404 void* secondary_ring_1_head_storage; 405 uint32 _reserved2[2]; 406 void* binning_head_storage; 407 uint32 _reserved3[3]; 408 uint32 store[1008]; 409 }; 410 411 #endif /* RADEON_HD_H */ 412