1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 #include "pol_reg.h" // DCE 12 28 29 #include <Accelerant.h> 30 #include <Drivers.h> 31 #include <edid.h> 32 #include <PCI.h> 33 34 35 #define VENDOR_ID_ATI 0x1002 36 37 // Card chipset flags 38 #define CHIP_STD (1 << 0) // Standard chipset 39 #define CHIP_X2 (1 << 1) // Dual cpu 40 #define CHIP_IGP (1 << 2) // IGP chipset 41 #define CHIP_MOBILE (1 << 3) // Mobile chipset 42 #define CHIP_DISCREET (1 << 4) // Discreet chipset 43 #define CHIP_APU (1 << 5) // APU chipset 44 45 #define DEVICE_NAME "radeon_hd" 46 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 47 48 #define MAX_NAME_LENGTH 32 49 50 // Used to collect EDID from boot loader 51 #define EDID_BOOT_INFO "vesa_edid/v1" 52 #define MODES_BOOT_INFO "vesa_modes/v1" 53 54 #define RHD_POWER_ON 0 55 #define RHD_POWER_RESET 1 /* off temporarily */ 56 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 57 #define RHD_POWER_UNKNOWN 3 /* initial state */ 58 59 60 // Radeon Chipsets 61 // !! Must match chipset names below 62 enum radeon_chipset { 63 RADEON_R420 = 0, //r400, Radeon X700-X850 64 RADEON_R423, 65 RADEON_RV410, 66 RADEON_RS400, 67 RADEON_RS480, 68 RADEON_RS600, 69 RADEON_RS690, 70 RADEON_RS740, 71 RADEON_RV515, 72 RADEON_R520, //r500, DCE 1.0 73 RADEON_RV530, // DCE 1.0 74 RADEON_RV560, // DCE 1.0 75 RADEON_RV570, // DCE 1.0 76 RADEON_R580, // DCE 1.0 77 RADEON_R600, //r600, DCE 2.0 78 RADEON_RV610, // DCE 2.0 79 RADEON_RV630, // DCE 2.0 80 RADEON_RV670, // DCE 2.0 81 RADEON_RV620, // DCE 3.0 82 RADEON_RV635, // DCE 3.0 83 RADEON_RS780, // DCE 3.0 84 RADEON_RS880, // DCE 3.0 85 RADEON_RV770, //r700, DCE 3.1 86 RADEON_RV730, // DCE 3.2 87 RADEON_RV710, // DCE 3.2 88 RADEON_RV740, // DCE 3.2 89 RADEON_CEDAR, //Evergreen, DCE 4.0 90 RADEON_REDWOOD, // DCE 4.0 91 RADEON_JUNIPER, // DCE 4.0 92 RADEON_CYPRESS, // DCE 4.0 93 RADEON_HEMLOCK, // DCE 4.0? 94 RADEON_PALM, //Fusion APU (NI), DCE 4.1 95 RADEON_SUMO, // DCE 4.1 96 RADEON_SUMO2, // DCE 4.1 97 RADEON_CAICOS, //Nothern Islands, DCE 5.0 98 RADEON_TURKS, // DCE 5.0 99 RADEON_BARTS, // DCE 5.0 100 RADEON_CAYMAN, // DCE 5.0 101 RADEON_ANTILLES, // DCE 5.0? 102 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 103 RADEON_PITCAIRN, // DCE 6.0 104 RADEON_TAHITI, // DCE 6.0 105 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 106 RADEON_OLAND, // DCE 6.4 107 RADEON_HAINAN, // NO DCE, only compute 108 RADEON_KAVERI, //Sea Islands, DCE 8.1 109 RADEON_BONAIRE, // DCE 8.2 110 RADEON_KABINI, // DCE 8.3 111 RADEON_MULLINS, // DCE 8.3 112 RADEON_HAWAII, // DCE 8.5 113 RADEON_TOPAZ, //Volcanic Islands, NO DCE 114 RADEON_TONGA, // DCE 10.0 115 RADEON_FIJI, // DCE 10.1? 116 RADEON_CARRIZO, // DCE 11.0 117 RADEON_STONEY, // DCE 11.1? 118 RADEON_POLARIS11, //Artic Islands, DCE 12.1? 119 RADEON_POLARIS10, // DCE 12.0? 120 RADEON_POLARIS12, // DCE 12.2? 121 RADEON_VEGAM, // DCE 13.0? 122 RADEON_VEGA10, // DCE 13.0? 123 RADEON_VEGA12, // DCE 13.0? 124 RADEON_VEGA20, // DCE 13.0? 125 RADEON_RAVEN, // DCE 13? 126 RADEON_NAVI, // DCE 13.0? 127 }; 128 129 // !! Must match chipset families above 130 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 131 "R420", 132 "R423", 133 "RV410", 134 "RS400", 135 "RS480", 136 "RS600", 137 "RS690", 138 "RS740", 139 "RV515", 140 "R520", 141 "RV530", 142 "RV560", 143 "RV570", 144 "R580", 145 "R600", 146 "RV610", 147 "RV630", 148 "RV670", 149 "RV620", 150 "RV635", 151 "RS780", 152 "RS880", 153 "RV770", 154 "RV730", 155 "RV710", 156 "RV740", 157 "Cedar", 158 "Redwood", 159 "Juniper", 160 "Cypress", 161 "Hemlock", 162 "Palm", 163 "Sumo", 164 "Sumo2", 165 "Caicos", 166 "Turks", 167 "Barts", 168 "Cayman", 169 "Antilles", 170 "Cape Verde", 171 "Pitcairn", 172 "Tahiti", 173 "Aruba", 174 "Oland", 175 "Hainan", 176 "Kaveri", 177 "Bonaire", 178 "Kabini", 179 "Mullins", 180 "Hawaii", 181 "Topaz", 182 "Tonga", 183 "Fiji", 184 "Carrizo", 185 "Stoney Ridge", 186 "Polaris 11", 187 "Polaris 10", 188 "Polaris 12", 189 "Vega Mobile", 190 "Vega 10", 191 "Vega 12", 192 "Vega 20", 193 "Raven", 194 "Navi", 195 }; 196 197 198 struct ring_buffer { 199 struct lock lock; 200 uint32 register_base; 201 uint32 offset; 202 uint32 size; 203 uint32 position; 204 uint32 space_left; 205 uint8* base; 206 }; 207 208 209 struct overlay_registers; 210 211 212 struct radeon_shared_info { 213 uint32 deviceIndex; // accelerant index 214 uint32 pciID; // device pci id 215 uint32 pciRev; // device pci revision 216 area_id mode_list_area; // area containing display mode list 217 uint32 mode_count; 218 219 bool has_rom; // was rom mapped? 220 area_id rom_area; // area of mapped rom 221 uint32 rom_phys; // rom base location 222 uint32 rom_size; // rom size 223 uint8* rom; // cloned, memory mapped PCI ROM 224 225 display_mode current_mode; 226 uint32 bytes_per_row; 227 uint32 bits_per_pixel; 228 uint32 dpms_mode; 229 230 area_id registers_area; // area of memory mapped registers 231 uint8* status_page; 232 addr_t physical_status_page; 233 uint32 graphics_memory_size; 234 235 uint8* frame_buffer; // virtual memory mapped FB 236 area_id frame_buffer_area; // area of memory mapped FB 237 addr_t frame_buffer_phys; // card PCI BAR address of FB 238 uint32 frame_buffer_size; // FB size mapped 239 240 bool has_edid; 241 edid1_info edid_info; 242 243 struct lock accelerant_lock; 244 struct lock engine_lock; 245 246 ring_buffer primary_ring_buffer; 247 248 int32 overlay_channel_used; 249 bool overlay_active; 250 uint32 overlay_token; 251 addr_t physical_overlay_registers; 252 uint32 overlay_offset; 253 254 bool hardware_cursor_enabled; 255 sem_id vblank_sem; 256 257 uint8* cursor_memory; 258 addr_t physical_cursor_memory; 259 uint32 cursor_buffer_offset; 260 uint32 cursor_format; 261 bool cursor_visible; 262 uint16 cursor_hot_x; 263 uint16 cursor_hot_y; 264 265 char deviceName[MAX_NAME_LENGTH]; 266 uint16 chipsetID; 267 char chipsetName[MAX_NAME_LENGTH]; 268 uint32 chipsetFlags; 269 uint8 dceMajor; 270 uint8 dceMinor; 271 272 uint16 color_data[3 * 256]; // colour lookup table 273 }; 274 275 //----------------- ioctl() interface ---------------- 276 277 // magic code for ioctls 278 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 279 280 // list ioctls 281 enum { 282 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 283 284 RADEON_GET_DEVICE_NAME, 285 RADEON_ALLOCATE_GRAPHICS_MEMORY, 286 RADEON_FREE_GRAPHICS_MEMORY 287 }; 288 289 // retrieve the area_id of the kernel/accelerant shared info 290 struct radeon_get_private_data { 291 uint32 magic; // magic number 292 area_id shared_info_area; 293 }; 294 295 // allocate graphics memory 296 struct radeon_allocate_graphics_memory { 297 uint32 magic; 298 uint32 size; 299 uint32 alignment; 300 uint32 flags; 301 uint32 buffer_base; 302 }; 303 304 // free graphics memory 305 struct radeon_free_graphics_memory { 306 uint32 magic; 307 uint32 buffer_base; 308 }; 309 310 // registers 311 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 312 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 313 #define CONFIG_MEMSIZE 0x5428 // r600> 314 315 // PCI bridge memory management 316 317 // overlay 318 319 #define RADEON_OVERLAY_UPDATE 0x30000 320 #define RADEON_OVERLAY_TEST 0x30004 321 #define RADEON_OVERLAY_STATUS 0x30008 322 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 323 #define RADEON_OVERLAY_GAMMA_5 0x30010 324 #define RADEON_OVERLAY_GAMMA_4 0x30014 325 #define RADEON_OVERLAY_GAMMA_3 0x30018 326 #define RADEON_OVERLAY_GAMMA_2 0x3001c 327 #define RADEON_OVERLAY_GAMMA_1 0x30020 328 #define RADEON_OVERLAY_GAMMA_0 0x30024 329 330 struct overlay_scale { 331 uint32 _reserved0 : 3; 332 uint32 horizontal_scale_fraction : 12; 333 uint32 _reserved1 : 1; 334 uint32 horizontal_downscale_factor : 3; 335 uint32 _reserved2 : 1; 336 uint32 vertical_scale_fraction : 12; 337 }; 338 339 #define OVERLAY_FORMAT_RGB15 0x2 340 #define OVERLAY_FORMAT_RGB16 0x3 341 #define OVERLAY_FORMAT_RGB32 0x1 342 #define OVERLAY_FORMAT_YCbCr422 0x8 343 #define OVERLAY_FORMAT_YCbCr411 0x9 344 #define OVERLAY_FORMAT_YCbCr420 0xc 345 346 #define OVERLAY_MIRROR_NORMAL 0x0 347 #define OVERLAY_MIRROR_HORIZONTAL 0x1 348 #define OVERLAY_MIRROR_VERTICAL 0x2 349 350 // The real overlay registers are written to using an update buffer 351 352 struct overlay_registers { 353 uint32 buffer_rgb0; 354 uint32 buffer_rgb1; 355 uint32 buffer_u0; 356 uint32 buffer_v0; 357 uint32 buffer_u1; 358 uint32 buffer_v1; 359 // (0x18) OSTRIDE - overlay stride 360 uint16 stride_rgb; 361 uint16 stride_uv; 362 // (0x1c) YRGB_VPH - Y/RGB vertical phase 363 uint16 vertical_phase0_rgb; 364 uint16 vertical_phase1_rgb; 365 // (0x20) UV_VPH - UV vertical phase 366 uint16 vertical_phase0_uv; 367 uint16 vertical_phase1_uv; 368 // (0x24) HORZ_PH - horizontal phase 369 uint16 horizontal_phase_rgb; 370 uint16 horizontal_phase_uv; 371 // (0x28) INIT_PHS - initial phase shift 372 uint32 initial_vertical_phase0_shift_rgb0 : 4; 373 uint32 initial_vertical_phase1_shift_rgb0 : 4; 374 uint32 initial_horizontal_phase_shift_rgb0 : 4; 375 uint32 initial_vertical_phase0_shift_uv : 4; 376 uint32 initial_vertical_phase1_shift_uv : 4; 377 uint32 initial_horizontal_phase_shift_uv : 4; 378 uint32 _reserved0 : 8; 379 // (0x2c) DWINPOS - destination window position 380 uint16 window_left; 381 uint16 window_top; 382 // (0x30) DWINSZ - destination window size 383 uint16 window_width; 384 uint16 window_height; 385 // (0x34) SWIDTH - source width 386 uint16 source_width_rgb; 387 uint16 source_width_uv; 388 // (0x38) SWITDHSW - source width in 8 byte steps 389 uint16 source_bytes_per_row_rgb; 390 uint16 source_bytes_per_row_uv; 391 uint16 source_height_rgb; 392 uint16 source_height_uv; 393 overlay_scale scale_rgb; 394 overlay_scale scale_uv; 395 // (0x48) OCLRC0 - overlay color correction 0 396 uint32 brightness_correction : 8; // signed, -128 to 127 397 uint32 _reserved1 : 10; 398 uint32 contrast_correction : 9; // fixed point: 3.6 bits 399 uint32 _reserved2 : 5; 400 // (0x4c) OCLRC1 - overlay color correction 1 401 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 402 uint32 _reserved3 : 6; 403 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 404 uint32 _reserved4 : 5; 405 // (0x50) DCLRKV - destination color key value 406 uint32 color_key_blue : 8; 407 uint32 color_key_green : 8; 408 uint32 color_key_red : 8; 409 uint32 _reserved5 : 8; 410 // (0x54) DCLRKM - destination color key mask 411 uint32 color_key_mask_blue : 8; 412 uint32 color_key_mask_green : 8; 413 uint32 color_key_mask_red : 8; 414 uint32 _reserved6 : 7; 415 uint32 color_key_enabled : 1; 416 // (0x58) SCHRKVH - source chroma key high value 417 uint32 source_chroma_key_high_red : 8; 418 uint32 source_chroma_key_high_blue : 8; 419 uint32 source_chroma_key_high_green : 8; 420 uint32 _reserved7 : 8; 421 // (0x5c) SCHRKVL - source chroma key low value 422 uint32 source_chroma_key_low_red : 8; 423 uint32 source_chroma_key_low_blue : 8; 424 uint32 source_chroma_key_low_green : 8; 425 uint32 _reserved8 : 8; 426 // (0x60) SCHRKEN - source chroma key enable 427 uint32 _reserved9 : 24; 428 uint32 source_chroma_key_red_enabled : 1; 429 uint32 source_chroma_key_blue_enabled : 1; 430 uint32 source_chroma_key_green_enabled : 1; 431 uint32 _reserved10 : 5; 432 // (0x64) OCONFIG - overlay configuration 433 uint32 _reserved11 : 3; 434 uint32 color_control_output_mode : 1; 435 uint32 yuv_to_rgb_bypass : 1; 436 uint32 _reserved12 : 11; 437 uint32 gamma2_enabled : 1; 438 uint32 _reserved13 : 1; 439 uint32 select_pipe : 1; 440 uint32 slot_time : 8; 441 uint32 _reserved14 : 5; 442 // (0x68) OCOMD - overlay command 443 uint32 overlay_enabled : 1; 444 uint32 active_field : 1; 445 uint32 active_buffer : 2; 446 uint32 test_mode : 1; 447 uint32 buffer_field_mode : 1; 448 uint32 _reserved15 : 1; 449 uint32 tv_flip_field_enabled : 1; 450 uint32 _reserved16 : 1; 451 uint32 tv_flip_field_parity : 1; 452 uint32 source_format : 4; 453 uint32 ycbcr422_order : 2; 454 uint32 _reserved18 : 1; 455 uint32 mirroring_mode : 2; 456 uint32 _reserved19 : 13; 457 458 uint32 _reserved20; 459 460 uint32 start_0y; 461 uint32 start_1y; 462 uint32 start_0u; 463 uint32 start_0v; 464 uint32 start_1u; 465 uint32 start_1v; 466 uint32 _reserved21[6]; 467 #if 0 468 // (0x70) AWINPOS - alpha blend window position 469 uint32 awinpos; 470 // (0x74) AWINSZ - alpha blend window size 471 uint32 awinsz; 472 473 uint32 _reserved21[10]; 474 #endif 475 476 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 477 // the next two registers switch the usual Y/RGB vs. UV order) 478 uint16 horizontal_scale_uv; 479 uint16 horizontal_scale_rgb; 480 // (0xa4) UVSCALEV - vertical downscale 481 uint16 vertical_scale_uv; 482 uint16 vertical_scale_rgb; 483 484 uint32 _reserved22[86]; 485 486 // (0x200) polyphase filter coefficients 487 uint16 vertical_coefficients_rgb[128]; 488 uint16 horizontal_coefficients_rgb[128]; 489 490 uint32 _reserved23[64]; 491 492 // (0x500) 493 uint16 vertical_coefficients_uv[128]; 494 uint16 horizontal_coefficients_uv[128]; 495 }; 496 497 498 struct hardware_status { 499 uint32 interrupt_status_register; 500 uint32 _reserved0[3]; 501 void* primary_ring_head_storage; 502 uint32 _reserved1[3]; 503 void* secondary_ring_0_head_storage; 504 void* secondary_ring_1_head_storage; 505 uint32 _reserved2[2]; 506 void* binning_head_storage; 507 uint32 _reserved3[3]; 508 uint32 store[1008]; 509 }; 510 511 #endif /* RADEON_HD_H */ 512