1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 28 #include <Accelerant.h> 29 #include <Drivers.h> 30 #include <edid.h> 31 #include <PCI.h> 32 33 34 #define VENDOR_ID_ATI 0x1002 35 36 // Card chipset flags 37 #define CHIP_STD (1 << 0) // Standard chipset 38 #define CHIP_X2 (1 << 1) // Dual cpu 39 #define CHIP_IGP (1 << 2) // IGP chipset 40 #define CHIP_MOBILE (1 << 3) // Mobile chipset 41 #define CHIP_DISCREET (1 << 4) // Discreet chipset 42 #define CHIP_APU (1 << 5) // APU chipset 43 44 #define DEVICE_NAME "radeon_hd" 45 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 46 47 #define MAX_NAME_LENGTH 32 48 49 // Used to collect EDID from boot loader 50 #define EDID_BOOT_INFO "vesa_edid/v1" 51 #define MODES_BOOT_INFO "vesa_modes/v1" 52 53 #define RHD_POWER_ON 0 54 #define RHD_POWER_RESET 1 /* off temporarily */ 55 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 56 #define RHD_POWER_UNKNOWN 3 /* initial state */ 57 58 59 // Radeon Chipsets 60 // !! Must match chipset names below 61 enum radeon_chipset { 62 RADEON_R420 = 0, //r400, Radeon X700-X850 63 RADEON_R423, 64 RADEON_RV410, 65 RADEON_RS400, 66 RADEON_RS480, 67 RADEON_RS600, 68 RADEON_RS690, 69 RADEON_RS740, 70 RADEON_RV515, 71 RADEON_R520, //r500, DCE 1.0 72 RADEON_RV530, // DCE 1.0 73 RADEON_RV560, // DCE 1.0 74 RADEON_RV570, // DCE 1.0 75 RADEON_R580, // DCE 1.0 76 RADEON_R600, //r600, DCE 2.0 77 RADEON_RV610, // DCE 2.0 78 RADEON_RV630, // DCE 2.0 79 RADEON_RV670, // DCE 2.0 80 RADEON_RV620, // DCE 3.0 81 RADEON_RV635, // DCE 3.0 82 RADEON_RS780, // DCE 3.0 83 RADEON_RS880, // DCE 3.0 84 RADEON_RV770, //r700, DCE 3.1 85 RADEON_RV730, // DCE 3.2 86 RADEON_RV710, // DCE 3.2 87 RADEON_RV740, // DCE 3.2 88 RADEON_CEDAR, //Evergreen, DCE 4.0 89 RADEON_REDWOOD, // DCE 4.0 90 RADEON_JUNIPER, // DCE 4.0 91 RADEON_CYPRESS, // DCE 4.0 92 RADEON_HEMLOCK, // DCE 4.0? 93 RADEON_PALM, //Fusion APU (NI), DCE 4.1 94 RADEON_SUMO, // DCE 4.1 95 RADEON_SUMO2, // DCE 4.1 96 RADEON_CAICOS, //Nothern Islands, DCE 5.0 97 RADEON_TURKS, // DCE 5.0 98 RADEON_BARTS, // DCE 5.0 99 RADEON_CAYMAN, // DCE 5.0 100 RADEON_ANTILLES, // DCE 5.0? 101 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 102 RADEON_PITCAIRN, // DCE 6.0 103 RADEON_TAHITI, // DCE 6.0 104 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 105 RADEON_OLAND, // DCE 6.4 106 RADEON_HAINAN, // NO DCE, only compute 107 RADEON_KAVERI, //Sea Islands, DCE 8.1 108 RADEON_BONAIRE, // DCE 8.2 109 RADEON_KABINI, // DCE 8.3 110 RADEON_MULLINS, // DCE 8.3 111 RADEON_HAWAII, // DCE 8.5 112 RADEON_TOPAZ, //Volcanic Islands, NO DCE 113 RADEON_TONGA, // DCE 10.0 114 RADEON_CARRIZO, // DCE 11.0 115 RADEON_POLARIS //Artic Islands, DCE 12.0 116 }; 117 118 // !! Must match chipset families above 119 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 120 "R420", 121 "R423", 122 "RV410", 123 "RS400", 124 "RS480", 125 "RS600", 126 "RS690", 127 "RS740", 128 "RV515", 129 "R520", 130 "RV530", 131 "RV560", 132 "RV570", 133 "R580", 134 "R600", 135 "RV610", 136 "RV630", 137 "RV670", 138 "RV620", 139 "RV635", 140 "RS780", 141 "RS880", 142 "RV770", 143 "RV730", 144 "RV710", 145 "RV740", 146 "Cedar", 147 "Redwood", 148 "Juniper", 149 "Cypress", 150 "Hemlock", 151 "Palm", 152 "Sumo", 153 "Sumo2", 154 "Caicos", 155 "Turks", 156 "Barts", 157 "Cayman", 158 "Antilles", 159 "Cape Verde", 160 "Pitcairn", 161 "Tahiti", 162 "Aruba", 163 "Oland", 164 "Hainan", 165 "Kaveri", 166 "Bonaire", 167 "Kabini", 168 "Mullins", 169 "Hawaii", 170 "Topaz", 171 "Tonga", 172 "Carrizo", 173 "Polaris" 174 }; 175 176 177 struct ring_buffer { 178 struct lock lock; 179 uint32 register_base; 180 uint32 offset; 181 uint32 size; 182 uint32 position; 183 uint32 space_left; 184 uint8* base; 185 }; 186 187 188 struct overlay_registers; 189 190 191 struct radeon_shared_info { 192 uint32 deviceIndex; // accelerant index 193 uint32 pciID; // device pciid 194 area_id mode_list_area; // area containing display mode list 195 uint32 mode_count; 196 197 bool has_rom; // was rom mapped? 198 area_id rom_area; // area of mapped rom 199 uint32 rom_phys; // rom base location 200 uint32 rom_size; // rom size 201 uint8* rom; // cloned, memory mapped PCI ROM 202 203 display_mode current_mode; 204 uint32 bytes_per_row; 205 uint32 bits_per_pixel; 206 uint32 dpms_mode; 207 208 area_id registers_area; // area of memory mapped registers 209 uint8* status_page; 210 addr_t physical_status_page; 211 uint32 graphics_memory_size; 212 213 uint8* frame_buffer; // virtual memory mapped FB 214 area_id frame_buffer_area; // area of memory mapped FB 215 addr_t frame_buffer_phys; // card PCI BAR address of FB 216 uint32 frame_buffer_size; // FB size mapped 217 218 bool has_edid; 219 edid1_info edid_info; 220 221 struct lock accelerant_lock; 222 struct lock engine_lock; 223 224 ring_buffer primary_ring_buffer; 225 226 int32 overlay_channel_used; 227 bool overlay_active; 228 uint32 overlay_token; 229 addr_t physical_overlay_registers; 230 uint32 overlay_offset; 231 232 bool hardware_cursor_enabled; 233 sem_id vblank_sem; 234 235 uint8* cursor_memory; 236 addr_t physical_cursor_memory; 237 uint32 cursor_buffer_offset; 238 uint32 cursor_format; 239 bool cursor_visible; 240 uint16 cursor_hot_x; 241 uint16 cursor_hot_y; 242 243 char deviceName[MAX_NAME_LENGTH]; 244 uint16 chipsetID; 245 char chipsetName[MAX_NAME_LENGTH]; 246 uint32 chipsetFlags; 247 uint8 dceMajor; 248 uint8 dceMinor; 249 250 uint16 color_data[3 * 256]; // colour lookup table 251 }; 252 253 //----------------- ioctl() interface ---------------- 254 255 // magic code for ioctls 256 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 257 258 // list ioctls 259 enum { 260 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 261 262 RADEON_GET_DEVICE_NAME, 263 RADEON_ALLOCATE_GRAPHICS_MEMORY, 264 RADEON_FREE_GRAPHICS_MEMORY 265 }; 266 267 // retrieve the area_id of the kernel/accelerant shared info 268 struct radeon_get_private_data { 269 uint32 magic; // magic number 270 area_id shared_info_area; 271 }; 272 273 // allocate graphics memory 274 struct radeon_allocate_graphics_memory { 275 uint32 magic; 276 uint32 size; 277 uint32 alignment; 278 uint32 flags; 279 uint32 buffer_base; 280 }; 281 282 // free graphics memory 283 struct radeon_free_graphics_memory { 284 uint32 magic; 285 uint32 buffer_base; 286 }; 287 288 // registers 289 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 290 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 291 #define CONFIG_MEMSIZE 0x5428 // r600> 292 293 // PCI bridge memory management 294 295 // overlay 296 297 #define RADEON_OVERLAY_UPDATE 0x30000 298 #define RADEON_OVERLAY_TEST 0x30004 299 #define RADEON_OVERLAY_STATUS 0x30008 300 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 301 #define RADEON_OVERLAY_GAMMA_5 0x30010 302 #define RADEON_OVERLAY_GAMMA_4 0x30014 303 #define RADEON_OVERLAY_GAMMA_3 0x30018 304 #define RADEON_OVERLAY_GAMMA_2 0x3001c 305 #define RADEON_OVERLAY_GAMMA_1 0x30020 306 #define RADEON_OVERLAY_GAMMA_0 0x30024 307 308 struct overlay_scale { 309 uint32 _reserved0 : 3; 310 uint32 horizontal_scale_fraction : 12; 311 uint32 _reserved1 : 1; 312 uint32 horizontal_downscale_factor : 3; 313 uint32 _reserved2 : 1; 314 uint32 vertical_scale_fraction : 12; 315 }; 316 317 #define OVERLAY_FORMAT_RGB15 0x2 318 #define OVERLAY_FORMAT_RGB16 0x3 319 #define OVERLAY_FORMAT_RGB32 0x1 320 #define OVERLAY_FORMAT_YCbCr422 0x8 321 #define OVERLAY_FORMAT_YCbCr411 0x9 322 #define OVERLAY_FORMAT_YCbCr420 0xc 323 324 #define OVERLAY_MIRROR_NORMAL 0x0 325 #define OVERLAY_MIRROR_HORIZONTAL 0x1 326 #define OVERLAY_MIRROR_VERTICAL 0x2 327 328 // The real overlay registers are written to using an update buffer 329 330 struct overlay_registers { 331 uint32 buffer_rgb0; 332 uint32 buffer_rgb1; 333 uint32 buffer_u0; 334 uint32 buffer_v0; 335 uint32 buffer_u1; 336 uint32 buffer_v1; 337 // (0x18) OSTRIDE - overlay stride 338 uint16 stride_rgb; 339 uint16 stride_uv; 340 // (0x1c) YRGB_VPH - Y/RGB vertical phase 341 uint16 vertical_phase0_rgb; 342 uint16 vertical_phase1_rgb; 343 // (0x20) UV_VPH - UV vertical phase 344 uint16 vertical_phase0_uv; 345 uint16 vertical_phase1_uv; 346 // (0x24) HORZ_PH - horizontal phase 347 uint16 horizontal_phase_rgb; 348 uint16 horizontal_phase_uv; 349 // (0x28) INIT_PHS - initial phase shift 350 uint32 initial_vertical_phase0_shift_rgb0 : 4; 351 uint32 initial_vertical_phase1_shift_rgb0 : 4; 352 uint32 initial_horizontal_phase_shift_rgb0 : 4; 353 uint32 initial_vertical_phase0_shift_uv : 4; 354 uint32 initial_vertical_phase1_shift_uv : 4; 355 uint32 initial_horizontal_phase_shift_uv : 4; 356 uint32 _reserved0 : 8; 357 // (0x2c) DWINPOS - destination window position 358 uint16 window_left; 359 uint16 window_top; 360 // (0x30) DWINSZ - destination window size 361 uint16 window_width; 362 uint16 window_height; 363 // (0x34) SWIDTH - source width 364 uint16 source_width_rgb; 365 uint16 source_width_uv; 366 // (0x38) SWITDHSW - source width in 8 byte steps 367 uint16 source_bytes_per_row_rgb; 368 uint16 source_bytes_per_row_uv; 369 uint16 source_height_rgb; 370 uint16 source_height_uv; 371 overlay_scale scale_rgb; 372 overlay_scale scale_uv; 373 // (0x48) OCLRC0 - overlay color correction 0 374 uint32 brightness_correction : 8; // signed, -128 to 127 375 uint32 _reserved1 : 10; 376 uint32 contrast_correction : 9; // fixed point: 3.6 bits 377 uint32 _reserved2 : 5; 378 // (0x4c) OCLRC1 - overlay color correction 1 379 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 380 uint32 _reserved3 : 6; 381 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 382 uint32 _reserved4 : 5; 383 // (0x50) DCLRKV - destination color key value 384 uint32 color_key_blue : 8; 385 uint32 color_key_green : 8; 386 uint32 color_key_red : 8; 387 uint32 _reserved5 : 8; 388 // (0x54) DCLRKM - destination color key mask 389 uint32 color_key_mask_blue : 8; 390 uint32 color_key_mask_green : 8; 391 uint32 color_key_mask_red : 8; 392 uint32 _reserved6 : 7; 393 uint32 color_key_enabled : 1; 394 // (0x58) SCHRKVH - source chroma key high value 395 uint32 source_chroma_key_high_red : 8; 396 uint32 source_chroma_key_high_blue : 8; 397 uint32 source_chroma_key_high_green : 8; 398 uint32 _reserved7 : 8; 399 // (0x5c) SCHRKVL - source chroma key low value 400 uint32 source_chroma_key_low_red : 8; 401 uint32 source_chroma_key_low_blue : 8; 402 uint32 source_chroma_key_low_green : 8; 403 uint32 _reserved8 : 8; 404 // (0x60) SCHRKEN - source chroma key enable 405 uint32 _reserved9 : 24; 406 uint32 source_chroma_key_red_enabled : 1; 407 uint32 source_chroma_key_blue_enabled : 1; 408 uint32 source_chroma_key_green_enabled : 1; 409 uint32 _reserved10 : 5; 410 // (0x64) OCONFIG - overlay configuration 411 uint32 _reserved11 : 3; 412 uint32 color_control_output_mode : 1; 413 uint32 yuv_to_rgb_bypass : 1; 414 uint32 _reserved12 : 11; 415 uint32 gamma2_enabled : 1; 416 uint32 _reserved13 : 1; 417 uint32 select_pipe : 1; 418 uint32 slot_time : 8; 419 uint32 _reserved14 : 5; 420 // (0x68) OCOMD - overlay command 421 uint32 overlay_enabled : 1; 422 uint32 active_field : 1; 423 uint32 active_buffer : 2; 424 uint32 test_mode : 1; 425 uint32 buffer_field_mode : 1; 426 uint32 _reserved15 : 1; 427 uint32 tv_flip_field_enabled : 1; 428 uint32 _reserved16 : 1; 429 uint32 tv_flip_field_parity : 1; 430 uint32 source_format : 4; 431 uint32 ycbcr422_order : 2; 432 uint32 _reserved18 : 1; 433 uint32 mirroring_mode : 2; 434 uint32 _reserved19 : 13; 435 436 uint32 _reserved20; 437 438 uint32 start_0y; 439 uint32 start_1y; 440 uint32 start_0u; 441 uint32 start_0v; 442 uint32 start_1u; 443 uint32 start_1v; 444 uint32 _reserved21[6]; 445 #if 0 446 // (0x70) AWINPOS - alpha blend window position 447 uint32 awinpos; 448 // (0x74) AWINSZ - alpha blend window size 449 uint32 awinsz; 450 451 uint32 _reserved21[10]; 452 #endif 453 454 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 455 // the next two registers switch the usual Y/RGB vs. UV order) 456 uint16 horizontal_scale_uv; 457 uint16 horizontal_scale_rgb; 458 // (0xa4) UVSCALEV - vertical downscale 459 uint16 vertical_scale_uv; 460 uint16 vertical_scale_rgb; 461 462 uint32 _reserved22[86]; 463 464 // (0x200) polyphase filter coefficients 465 uint16 vertical_coefficients_rgb[128]; 466 uint16 horizontal_coefficients_rgb[128]; 467 468 uint32 _reserved23[64]; 469 470 // (0x500) 471 uint16 vertical_coefficients_uv[128]; 472 uint16 horizontal_coefficients_uv[128]; 473 }; 474 475 476 struct hardware_status { 477 uint32 interrupt_status_register; 478 uint32 _reserved0[3]; 479 void* primary_ring_head_storage; 480 uint32 _reserved1[3]; 481 void* secondary_ring_0_head_storage; 482 void* secondary_ring_1_head_storage; 483 uint32 _reserved2[2]; 484 void* binning_head_storage; 485 uint32 _reserved3[3]; 486 uint32 store[1008]; 487 }; 488 489 #endif /* RADEON_HD_H */ 490