1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "rhd_regs.h" 16 #include "r600_reg.h" 17 #include "r800_reg.h" 18 19 #include <Accelerant.h> 20 #include <Drivers.h> 21 #include <edid.h> 22 #include <PCI.h> 23 24 25 #define VENDOR_ID_ATI 0x1002 26 27 #define RADEON_R600 0x0600 28 #define RADEON_R700 0x0700 29 #define RADEON_R800 0x0800 30 31 #define RADEON_VBIOS_SIZE 0x10000 32 33 #define DEVICE_NAME "radeon_hd" 34 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 35 36 // Used to collect EDID from boot loader 37 #define EDID_BOOT_INFO "vesa_edid/v1" 38 #define MODES_BOOT_INFO "vesa_modes/v1" 39 40 41 // info about PLL on graphics card 42 struct pll_info { 43 uint32 reference_frequency; 44 uint32 max_frequency; 45 uint32 min_frequency; 46 uint32 divisor_register; 47 }; 48 49 50 struct ring_buffer { 51 struct lock lock; 52 uint32 register_base; 53 uint32 offset; 54 uint32 size; 55 uint32 position; 56 uint32 space_left; 57 uint8* base; 58 }; 59 60 61 struct overlay_registers; 62 63 64 struct radeon_shared_info { 65 area_id mode_list_area; // area containing display mode list 66 uint32 mode_count; 67 68 display_mode current_mode; 69 uint32 bytes_per_row; 70 uint32 bits_per_pixel; 71 uint32 dpms_mode; 72 73 area_id registers_area; // area of memory mapped registers 74 uint8* status_page; 75 addr_t physical_status_page; 76 uint8* graphics_memory; 77 uint32 graphics_memory_size; 78 79 addr_t frame_buffer_phys; // card PCI BAR address of FB 80 uint32 frame_buffer_int; // card internal offset of FB 81 uint32 frame_buffer_size; // card internal FB aperture size 82 uint32 frame_buffer_offset; // offset within FB (pri vs sec) 83 84 bool has_edid; 85 edid1_info edid_info; 86 87 struct lock accelerant_lock; 88 struct lock engine_lock; 89 90 ring_buffer primary_ring_buffer; 91 92 int32 overlay_channel_used; 93 bool overlay_active; 94 uint32 overlay_token; 95 addr_t physical_overlay_registers; 96 uint32 overlay_offset; 97 98 bool hardware_cursor_enabled; 99 sem_id vblank_sem; 100 101 uint8* cursor_memory; 102 addr_t physical_cursor_memory; 103 uint32 cursor_buffer_offset; 104 uint32 cursor_format; 105 bool cursor_visible; 106 uint16 cursor_hot_x; 107 uint16 cursor_hot_y; 108 109 uint16 device_chipset; 110 char device_identifier[32]; 111 struct pll_info pll_info; 112 }; 113 114 //----------------- ioctl() interface ---------------- 115 116 // magic code for ioctls 117 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 118 119 // list ioctls 120 enum { 121 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 122 123 RADEON_GET_DEVICE_NAME, 124 RADEON_ALLOCATE_GRAPHICS_MEMORY, 125 RADEON_FREE_GRAPHICS_MEMORY 126 }; 127 128 // retrieve the area_id of the kernel/accelerant shared info 129 struct radeon_get_private_data { 130 uint32 magic; // magic number 131 area_id shared_info_area; 132 }; 133 134 // allocate graphics memory 135 struct radeon_allocate_graphics_memory { 136 uint32 magic; 137 uint32 size; 138 uint32 alignment; 139 uint32 flags; 140 uint32 buffer_base; 141 }; 142 143 // free graphics memory 144 struct radeon_free_graphics_memory { 145 uint32 magic; 146 uint32 buffer_base; 147 }; 148 149 // registers 150 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 151 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 152 153 // cursor 154 #define RADEON_CURSOR_CONTROL 0x70080 155 #define RADEON_CURSOR_BASE 0x70084 156 #define RADEON_CURSOR_POSITION 0x70088 157 #define RADEON_CURSOR_PALETTE 0x70090 // (- 0x7009f) 158 #define RADEON_CURSOR_SIZE 0x700a0 159 #define CURSOR_ENABLED (1UL << 31) 160 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 161 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 162 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 163 #define CURSOR_FORMAT_ARGB (4UL << 24) 164 #define CURSOR_FORMAT_XRGB (5UL << 24) 165 #define CURSOR_POSITION_NEGATIVE 0x8000 166 #define CURSOR_POSITION_MASK 0x3fff 167 168 // overlay flip 169 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 170 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 171 #define COMMAND_OVERLAY_ON (1 << 21) 172 #define COMMAND_OVERLAY_OFF (2 << 21) 173 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 174 175 // 2D acceleration 176 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 177 #define XY_COMMAND_COLOR_BLIT 0x54000004 178 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 179 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 180 #define COMMAND_COLOR_BLIT 0x50000003 181 #define COMMAND_BLIT_RGBA 0x00300000 182 183 #define COMMAND_MODE_SOLID_PATTERN 0x80 184 #define COMMAND_MODE_CMAP8 0x00 185 #define COMMAND_MODE_RGB15 0x02 186 #define COMMAND_MODE_RGB16 0x01 187 #define COMMAND_MODE_RGB32 0x03 188 189 // display 190 191 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 192 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 193 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 194 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 195 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 196 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 197 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 198 199 // PCI bridge memory management 200 201 // overlay 202 203 #define RADEON_OVERLAY_UPDATE 0x30000 204 #define RADEON_OVERLAY_TEST 0x30004 205 #define RADEON_OVERLAY_STATUS 0x30008 206 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 207 #define RADEON_OVERLAY_GAMMA_5 0x30010 208 #define RADEON_OVERLAY_GAMMA_4 0x30014 209 #define RADEON_OVERLAY_GAMMA_3 0x30018 210 #define RADEON_OVERLAY_GAMMA_2 0x3001c 211 #define RADEON_OVERLAY_GAMMA_1 0x30020 212 #define RADEON_OVERLAY_GAMMA_0 0x30024 213 214 struct overlay_scale { 215 uint32 _reserved0 : 3; 216 uint32 horizontal_scale_fraction : 12; 217 uint32 _reserved1 : 1; 218 uint32 horizontal_downscale_factor : 3; 219 uint32 _reserved2 : 1; 220 uint32 vertical_scale_fraction : 12; 221 }; 222 223 #define OVERLAY_FORMAT_RGB15 0x2 224 #define OVERLAY_FORMAT_RGB16 0x3 225 #define OVERLAY_FORMAT_RGB32 0x1 226 #define OVERLAY_FORMAT_YCbCr422 0x8 227 #define OVERLAY_FORMAT_YCbCr411 0x9 228 #define OVERLAY_FORMAT_YCbCr420 0xc 229 230 #define OVERLAY_MIRROR_NORMAL 0x0 231 #define OVERLAY_MIRROR_HORIZONTAL 0x1 232 #define OVERLAY_MIRROR_VERTICAL 0x2 233 234 // The real overlay registers are written to using an update buffer 235 236 struct overlay_registers { 237 uint32 buffer_rgb0; 238 uint32 buffer_rgb1; 239 uint32 buffer_u0; 240 uint32 buffer_v0; 241 uint32 buffer_u1; 242 uint32 buffer_v1; 243 // (0x18) OSTRIDE - overlay stride 244 uint16 stride_rgb; 245 uint16 stride_uv; 246 // (0x1c) YRGB_VPH - Y/RGB vertical phase 247 uint16 vertical_phase0_rgb; 248 uint16 vertical_phase1_rgb; 249 // (0x20) UV_VPH - UV vertical phase 250 uint16 vertical_phase0_uv; 251 uint16 vertical_phase1_uv; 252 // (0x24) HORZ_PH - horizontal phase 253 uint16 horizontal_phase_rgb; 254 uint16 horizontal_phase_uv; 255 // (0x28) INIT_PHS - initial phase shift 256 uint32 initial_vertical_phase0_shift_rgb0 : 4; 257 uint32 initial_vertical_phase1_shift_rgb0 : 4; 258 uint32 initial_horizontal_phase_shift_rgb0 : 4; 259 uint32 initial_vertical_phase0_shift_uv : 4; 260 uint32 initial_vertical_phase1_shift_uv : 4; 261 uint32 initial_horizontal_phase_shift_uv : 4; 262 uint32 _reserved0 : 8; 263 // (0x2c) DWINPOS - destination window position 264 uint16 window_left; 265 uint16 window_top; 266 // (0x30) DWINSZ - destination window size 267 uint16 window_width; 268 uint16 window_height; 269 // (0x34) SWIDTH - source width 270 uint16 source_width_rgb; 271 uint16 source_width_uv; 272 // (0x38) SWITDHSW - source width in 8 byte steps 273 uint16 source_bytes_per_row_rgb; 274 uint16 source_bytes_per_row_uv; 275 uint16 source_height_rgb; 276 uint16 source_height_uv; 277 overlay_scale scale_rgb; 278 overlay_scale scale_uv; 279 // (0x48) OCLRC0 - overlay color correction 0 280 uint32 brightness_correction : 8; // signed, -128 to 127 281 uint32 _reserved1 : 10; 282 uint32 contrast_correction : 9; // fixed point: 3.6 bits 283 uint32 _reserved2 : 5; 284 // (0x4c) OCLRC1 - overlay color correction 1 285 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 286 uint32 _reserved3 : 6; 287 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 288 uint32 _reserved4 : 5; 289 // (0x50) DCLRKV - destination color key value 290 uint32 color_key_blue : 8; 291 uint32 color_key_green : 8; 292 uint32 color_key_red : 8; 293 uint32 _reserved5 : 8; 294 // (0x54) DCLRKM - destination color key mask 295 uint32 color_key_mask_blue : 8; 296 uint32 color_key_mask_green : 8; 297 uint32 color_key_mask_red : 8; 298 uint32 _reserved6 : 7; 299 uint32 color_key_enabled : 1; 300 // (0x58) SCHRKVH - source chroma key high value 301 uint32 source_chroma_key_high_red : 8; 302 uint32 source_chroma_key_high_blue : 8; 303 uint32 source_chroma_key_high_green : 8; 304 uint32 _reserved7 : 8; 305 // (0x5c) SCHRKVL - source chroma key low value 306 uint32 source_chroma_key_low_red : 8; 307 uint32 source_chroma_key_low_blue : 8; 308 uint32 source_chroma_key_low_green : 8; 309 uint32 _reserved8 : 8; 310 // (0x60) SCHRKEN - source chroma key enable 311 uint32 _reserved9 : 24; 312 uint32 source_chroma_key_red_enabled : 1; 313 uint32 source_chroma_key_blue_enabled : 1; 314 uint32 source_chroma_key_green_enabled : 1; 315 uint32 _reserved10 : 5; 316 // (0x64) OCONFIG - overlay configuration 317 uint32 _reserved11 : 3; 318 uint32 color_control_output_mode : 1; 319 uint32 yuv_to_rgb_bypass : 1; 320 uint32 _reserved12 : 11; 321 uint32 gamma2_enabled : 1; 322 uint32 _reserved13 : 1; 323 uint32 select_pipe : 1; 324 uint32 slot_time : 8; 325 uint32 _reserved14 : 5; 326 // (0x68) OCOMD - overlay command 327 uint32 overlay_enabled : 1; 328 uint32 active_field : 1; 329 uint32 active_buffer : 2; 330 uint32 test_mode : 1; 331 uint32 buffer_field_mode : 1; 332 uint32 _reserved15 : 1; 333 uint32 tv_flip_field_enabled : 1; 334 uint32 _reserved16 : 1; 335 uint32 tv_flip_field_parity : 1; 336 uint32 source_format : 4; 337 uint32 ycbcr422_order : 2; 338 uint32 _reserved18 : 1; 339 uint32 mirroring_mode : 2; 340 uint32 _reserved19 : 13; 341 342 uint32 _reserved20; 343 344 uint32 start_0y; 345 uint32 start_1y; 346 uint32 start_0u; 347 uint32 start_0v; 348 uint32 start_1u; 349 uint32 start_1v; 350 uint32 _reserved21[6]; 351 #if 0 352 // (0x70) AWINPOS - alpha blend window position 353 uint32 awinpos; 354 // (0x74) AWINSZ - alpha blend window size 355 uint32 awinsz; 356 357 uint32 _reserved21[10]; 358 #endif 359 360 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 361 // the next two registers switch the usual Y/RGB vs. UV order) 362 uint16 horizontal_scale_uv; 363 uint16 horizontal_scale_rgb; 364 // (0xa4) UVSCALEV - vertical downscale 365 uint16 vertical_scale_uv; 366 uint16 vertical_scale_rgb; 367 368 uint32 _reserved22[86]; 369 370 // (0x200) polyphase filter coefficients 371 uint16 vertical_coefficients_rgb[128]; 372 uint16 horizontal_coefficients_rgb[128]; 373 374 uint32 _reserved23[64]; 375 376 // (0x500) 377 uint16 vertical_coefficients_uv[128]; 378 uint16 horizontal_coefficients_uv[128]; 379 }; 380 381 382 struct hardware_status { 383 uint32 interrupt_status_register; 384 uint32 _reserved0[3]; 385 void* primary_ring_head_storage; 386 uint32 _reserved1[3]; 387 void* secondary_ring_0_head_storage; 388 void* secondary_ring_1_head_storage; 389 uint32 _reserved2[2]; 390 void* binning_head_storage; 391 uint32 _reserved3[3]; 392 uint32 store[1008]; 393 }; 394 395 #endif /* RADEON_HD_H */ 396