1 /* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 10 /* Copyright for portions of this file (Xorg radeonhd registers) 11 * 12 * Copyright 2007, 2008 Luc Verhaegen <libv@exsuse.de> 13 * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> 14 * Copyright 2007, 2008 Egbert Eich <eich@novell.com> 15 * Copyright 2007, 2008 Advanced Micro Devices, Inc. 16 * 17 * Permission is hereby granted, free of charge, to any person obtaining a 18 * copy of this software and associated documentation files (the "Software"), 19 * to deal in the Software without restriction, including without limitation 20 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 21 * and/or sell copies of the Software, and to permit persons to whom the 22 * Software is furnished to do so, subject to the following conditions: 23 * 24 * The above copyright notice and this permission notice shall be included in 25 * all copies or substantial portions of the Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 #ifndef RADEON_HD_H 36 #define RADEON_HD_H 37 38 39 #include "lock.h" 40 41 #include <Accelerant.h> 42 #include <Drivers.h> 43 #include <PCI.h> 44 45 46 #define VENDOR_ID_ATI 0x1002 47 48 // TODO : Remove masks as they don't apply to radeon 49 #define RADEON_TYPE_FAMILY_MASK 0xf000 50 #define RADEON_TYPE_GROUP_MASK 0xfff0 51 #define RADEON_TYPE_MODEL_MASK 0xffff 52 53 #define RADEON_R600 0x0600 54 #define RADEON_R700 0x0700 55 #define RADEON_R800 0x0800 56 57 #define DEVICE_NAME "radeon_hd" 58 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 59 60 61 struct DeviceType { 62 uint32 type; 63 64 DeviceType(int t) 65 { 66 type = t; 67 } 68 69 DeviceType& operator=(int t) 70 { 71 type = t; 72 return *this; 73 } 74 75 bool InFamily(uint32 family) const 76 { 77 return (type & RADEON_TYPE_FAMILY_MASK) == family; 78 } 79 80 bool InGroup(uint32 group) const 81 { 82 return (type & RADEON_TYPE_GROUP_MASK) == group; 83 } 84 85 bool IsModel(uint32 model) const 86 { 87 return (type & RADEON_TYPE_MODEL_MASK) == model; 88 } 89 }; 90 91 92 // info about PLL on graphics card 93 struct pll_info { 94 uint32 reference_frequency; 95 uint32 max_frequency; 96 uint32 min_frequency; 97 uint32 divisor_register; 98 }; 99 100 101 struct ring_buffer { 102 struct lock lock; 103 uint32 register_base; 104 uint32 offset; 105 uint32 size; 106 uint32 position; 107 uint32 space_left; 108 uint8* base; 109 }; 110 111 112 struct overlay_registers; 113 114 115 struct radeon_shared_info { 116 area_id mode_list_area; // area containing display mode list 117 uint32 mode_count; 118 119 display_mode current_mode; 120 uint32 bytes_per_row; 121 uint32 bits_per_pixel; 122 uint32 dpms_mode; 123 124 area_id registers_area; // area of memory mapped registers 125 uint8* status_page; 126 addr_t physical_status_page; 127 uint8* graphics_memory; 128 addr_t physical_graphics_memory; 129 uint32 graphics_memory_size; 130 131 addr_t frame_buffer; 132 uint32 frame_buffer_offset; 133 134 struct lock accelerant_lock; 135 struct lock engine_lock; 136 137 ring_buffer primary_ring_buffer; 138 139 int32 overlay_channel_used; 140 bool overlay_active; 141 uint32 overlay_token; 142 addr_t physical_overlay_registers; 143 uint32 overlay_offset; 144 145 bool hardware_cursor_enabled; 146 sem_id vblank_sem; 147 148 uint8* cursor_memory; 149 addr_t physical_cursor_memory; 150 uint32 cursor_buffer_offset; 151 uint32 cursor_format; 152 bool cursor_visible; 153 uint16 cursor_hot_x; 154 uint16 cursor_hot_y; 155 156 DeviceType device_type; 157 char device_identifier[32]; 158 struct pll_info pll_info; 159 }; 160 161 //----------------- ioctl() interface ---------------- 162 163 // magic code for ioctls 164 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 165 166 // list ioctls 167 enum { 168 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 169 170 RADEON_GET_DEVICE_NAME, 171 RADEON_ALLOCATE_GRAPHICS_MEMORY, 172 RADEON_FREE_GRAPHICS_MEMORY 173 }; 174 175 // retrieve the area_id of the kernel/accelerant shared info 176 struct radeon_get_private_data { 177 uint32 magic; // magic number 178 area_id shared_info_area; 179 }; 180 181 // allocate graphics memory 182 struct radeon_allocate_graphics_memory { 183 uint32 magic; 184 uint32 size; 185 uint32 alignment; 186 uint32 flags; 187 uint32 buffer_base; 188 }; 189 190 // free graphics memory 191 struct radeon_free_graphics_memory { 192 uint32 magic; 193 uint32 buffer_base; 194 }; 195 196 // ---------------------------------------------------------- 197 // Register definitions, taken from X driver 198 199 // Generic Radeon registers 200 enum { 201 CLOCK_CNTL_INDEX = 0x8, /* (RW) */ 202 CLOCK_CNTL_DATA = 0xC, /* (RW) */ 203 BUS_CNTL = 0x4C, /* (RW) */ 204 MC_IND_INDEX = 0x70, /* (RW) */ 205 MC_IND_DATA = 0x74, /* (RW) */ 206 RS600_MC_INDEX = 0x70, 207 RS600_MC_DATA = 0x74, 208 RS690_MC_INDEX = 0x78, 209 RS690_MC_DATA = 0x7c, 210 RS780_MC_INDEX = 0x28f8, 211 RS780_MC_DATA = 0x28fc, 212 213 RS60_MC_NB_MC_INDEX = 0x78, 214 RS60_MC_NB_MC_DATA = 0x7C, 215 CONFIG_CNTL = 0xE0, 216 PCIE_RS69_MC_INDEX = 0xE8, 217 PCIE_RS69_MC_DATA = 0xEC, 218 R5XX_CONFIG_MEMSIZE = 0x00F8, 219 220 HDP_FB_LOCATION = 0x0134, 221 222 SEPROM_CNTL1 = 0x1C0, /* (RW) */ 223 224 AGP_BASE = 0x0170, 225 226 GPIOPAD_MASK = 0x198, /* (RW) */ 227 GPIOPAD_A = 0x19C, /* (RW) */ 228 GPIOPAD_EN = 0x1A0, /* (RW) */ 229 VIPH_CONTROL = 0xC40, /* (RW) */ 230 231 ROM_CNTL = 0x1600, 232 GENERAL_PWRMGT = 0x0618, 233 LOW_VID_LOWER_GPIO_CNTL = 0x0724, 234 MEDIUM_VID_LOWER_GPIO_CNTL = 0x0720, 235 HIGH_VID_LOWER_GPIO_CNTL = 0x071C, 236 CTXSW_VID_LOWER_GPIO_CNTL = 0x0718, 237 LOWER_GPIO_ENABLE = 0x0710, 238 239 /* VGA registers */ 240 VGA_RENDER_CONTROL = 0x0300, 241 VGA_MODE_CONTROL = 0x0308, 242 VGA_MEMORY_BASE_ADDRESS = 0x0310, 243 VGA_HDP_CONTROL = 0x0328, 244 D1VGA_CONTROL = 0x0330, 245 D2VGA_CONTROL = 0x0338, 246 247 EXT1_PPLL_REF_DIV_SRC = 0x0400, 248 EXT1_PPLL_REF_DIV = 0x0404, 249 EXT1_PPLL_UPDATE_LOCK = 0x0408, 250 EXT1_PPLL_UPDATE_CNTL = 0x040C, 251 EXT2_PPLL_REF_DIV_SRC = 0x0410, 252 EXT2_PPLL_REF_DIV = 0x0414, 253 EXT2_PPLL_UPDATE_LOCK = 0x0418, 254 EXT2_PPLL_UPDATE_CNTL = 0x041C, 255 256 EXT1_PPLL_FB_DIV = 0x0430, 257 EXT2_PPLL_FB_DIV = 0x0434, 258 EXT1_PPLL_POST_DIV_SRC = 0x0438, 259 EXT1_PPLL_POST_DIV = 0x043C, 260 EXT2_PPLL_POST_DIV_SRC = 0x0440, 261 EXT2_PPLL_POST_DIV = 0x0444, 262 EXT1_PPLL_CNTL = 0x0448, 263 EXT2_PPLL_CNTL = 0x044C, 264 P1PLL_CNTL = 0x0450, 265 P2PLL_CNTL = 0x0454, 266 P1PLL_INT_SS_CNTL = 0x0458, 267 P2PLL_INT_SS_CNTL = 0x045C, 268 269 P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */ 270 P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */ 271 EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */ 272 EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */ 273 274 PCLK_CRTC1_CNTL = 0x0480, 275 PCLK_CRTC2_CNTL = 0x0484, 276 277 // TODO : xorg reverse engineered registers 278 }; 279 280 281 // ATI r600 specific 282 enum _r6xxRegs { 283 /* MCLK */ 284 R6_MCLK_PWRMGT_CNTL = 0x620, 285 /* I2C */ 286 R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */ 287 R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */ 288 R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ 289 R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */ 290 R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */ 291 R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */ 292 R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */ 293 R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */ 294 R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */ 295 R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */ 296 R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */ 297 R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */ 298 R6_DC_I2C_DATA = 0x7D74, /* (RW) */ 299 R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */ 300 R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */ 301 R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */ 302 R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */ 303 R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */ 304 R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ 305 R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ 306 R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ 307 R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */ 308 R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ 309 R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ 310 R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ 311 R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */ 312 R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ 313 R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ 314 R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */ 315 R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */ 316 }; 317 318 319 // PLL Clock Controls 320 enum { 321 /* CLOCK_CNTL_INDEX */ 322 PLL_ADDR = (0x3f << 0), 323 PLL_WR_EN = (0x1 << 7), 324 PPLL_DIV_SEL = (0x3 << 8), 325 326 /* SPLL_FUNC_CNTL */ 327 SPLL_CHG_STATUS = (0x1 << 29), 328 SPLL_BYPASS_EN = (0x1 << 25), 329 330 /* MC_IND_INDEX */ 331 MC_IND_ADDR = (0xffff << 0), 332 MC_IND_SEQ_RBS_0 = (0x1 << 16), 333 MC_IND_SEQ_RBS_1 = (0x1 << 17), 334 MC_IND_SEQ_RBS_2 = (0x1 << 18), 335 MC_IND_SEQ_RBS_3 = (0x1 << 19), 336 MC_IND_AIC_RBS = (0x1 << 20), 337 MC_IND_CITF_ARB0 = (0x1 << 21), 338 MC_IND_CITF_ARB1 = (0x1 << 22), 339 MC_IND_WR_EN = (0x1 << 23), 340 MC_IND_RD_INV = (0x1 << 24) 341 }; 342 343 344 /* CLOCK_CNTL_DATA */ 345 #define PLL_DATA 0xffffffff 346 /* MC_IND_DATA */ 347 #define MC_IND_ALL (MC_IND_SEQ_RBS_0 | MC_IND_SEQ_RBS_1 \ 348 | MC_IND_SEQ_RBS_2 | MC_IND_SEQ_RBS_3 \ 349 | MC_IND_AIC_RBS | MC_IND_CITF_ARB0 \ 350 | MC_IND_CITF_ARB1) 351 #define MC_IND_DATA_BIT 0xffffffff 352 353 354 // cursor 355 #define RADEON_CURSOR_CONTROL 0x70080 356 #define RADEON_CURSOR_BASE 0x70084 357 #define RADEON_CURSOR_POSITION 0x70088 358 #define RADEON_CURSOR_PALETTE 0x70090 // (- 0x7009f) 359 #define RADEON_CURSOR_SIZE 0x700a0 360 #define CURSOR_ENABLED (1UL << 31) 361 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 362 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 363 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 364 #define CURSOR_FORMAT_ARGB (4UL << 24) 365 #define CURSOR_FORMAT_XRGB (5UL << 24) 366 #define CURSOR_POSITION_NEGATIVE 0x8000 367 #define CURSOR_POSITION_MASK 0x3fff 368 369 // overlay flip 370 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 371 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 372 #define COMMAND_OVERLAY_ON (1 << 21) 373 #define COMMAND_OVERLAY_OFF (2 << 21) 374 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 375 376 // 2D acceleration 377 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 378 #define XY_COMMAND_COLOR_BLIT 0x54000004 379 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 380 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 381 #define COMMAND_COLOR_BLIT 0x50000003 382 #define COMMAND_BLIT_RGBA 0x00300000 383 384 #define COMMAND_MODE_SOLID_PATTERN 0x80 385 #define COMMAND_MODE_CMAP8 0x00 386 #define COMMAND_MODE_RGB15 0x02 387 #define COMMAND_MODE_RGB16 0x01 388 #define COMMAND_MODE_RGB32 0x03 389 390 // display 391 392 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 393 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 394 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 395 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 396 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 397 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 398 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 399 400 // PCI bridge memory management 401 402 // overlay 403 404 #define RADEON_OVERLAY_UPDATE 0x30000 405 #define RADEON_OVERLAY_TEST 0x30004 406 #define RADEON_OVERLAY_STATUS 0x30008 407 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 408 #define RADEON_OVERLAY_GAMMA_5 0x30010 409 #define RADEON_OVERLAY_GAMMA_4 0x30014 410 #define RADEON_OVERLAY_GAMMA_3 0x30018 411 #define RADEON_OVERLAY_GAMMA_2 0x3001c 412 #define RADEON_OVERLAY_GAMMA_1 0x30020 413 #define RADEON_OVERLAY_GAMMA_0 0x30024 414 415 struct overlay_scale { 416 uint32 _reserved0 : 3; 417 uint32 horizontal_scale_fraction : 12; 418 uint32 _reserved1 : 1; 419 uint32 horizontal_downscale_factor : 3; 420 uint32 _reserved2 : 1; 421 uint32 vertical_scale_fraction : 12; 422 }; 423 424 #define OVERLAY_FORMAT_RGB15 0x2 425 #define OVERLAY_FORMAT_RGB16 0x3 426 #define OVERLAY_FORMAT_RGB32 0x1 427 #define OVERLAY_FORMAT_YCbCr422 0x8 428 #define OVERLAY_FORMAT_YCbCr411 0x9 429 #define OVERLAY_FORMAT_YCbCr420 0xc 430 431 #define OVERLAY_MIRROR_NORMAL 0x0 432 #define OVERLAY_MIRROR_HORIZONTAL 0x1 433 #define OVERLAY_MIRROR_VERTICAL 0x2 434 435 // The real overlay registers are written to using an update buffer 436 437 struct overlay_registers { 438 uint32 buffer_rgb0; 439 uint32 buffer_rgb1; 440 uint32 buffer_u0; 441 uint32 buffer_v0; 442 uint32 buffer_u1; 443 uint32 buffer_v1; 444 // (0x18) OSTRIDE - overlay stride 445 uint16 stride_rgb; 446 uint16 stride_uv; 447 // (0x1c) YRGB_VPH - Y/RGB vertical phase 448 uint16 vertical_phase0_rgb; 449 uint16 vertical_phase1_rgb; 450 // (0x20) UV_VPH - UV vertical phase 451 uint16 vertical_phase0_uv; 452 uint16 vertical_phase1_uv; 453 // (0x24) HORZ_PH - horizontal phase 454 uint16 horizontal_phase_rgb; 455 uint16 horizontal_phase_uv; 456 // (0x28) INIT_PHS - initial phase shift 457 uint32 initial_vertical_phase0_shift_rgb0 : 4; 458 uint32 initial_vertical_phase1_shift_rgb0 : 4; 459 uint32 initial_horizontal_phase_shift_rgb0 : 4; 460 uint32 initial_vertical_phase0_shift_uv : 4; 461 uint32 initial_vertical_phase1_shift_uv : 4; 462 uint32 initial_horizontal_phase_shift_uv : 4; 463 uint32 _reserved0 : 8; 464 // (0x2c) DWINPOS - destination window position 465 uint16 window_left; 466 uint16 window_top; 467 // (0x30) DWINSZ - destination window size 468 uint16 window_width; 469 uint16 window_height; 470 // (0x34) SWIDTH - source width 471 uint16 source_width_rgb; 472 uint16 source_width_uv; 473 // (0x38) SWITDHSW - source width in 8 byte steps 474 uint16 source_bytes_per_row_rgb; 475 uint16 source_bytes_per_row_uv; 476 uint16 source_height_rgb; 477 uint16 source_height_uv; 478 overlay_scale scale_rgb; 479 overlay_scale scale_uv; 480 // (0x48) OCLRC0 - overlay color correction 0 481 uint32 brightness_correction : 8; // signed, -128 to 127 482 uint32 _reserved1 : 10; 483 uint32 contrast_correction : 9; // fixed point: 3.6 bits 484 uint32 _reserved2 : 5; 485 // (0x4c) OCLRC1 - overlay color correction 1 486 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 487 uint32 _reserved3 : 6; 488 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 489 uint32 _reserved4 : 5; 490 // (0x50) DCLRKV - destination color key value 491 uint32 color_key_blue : 8; 492 uint32 color_key_green : 8; 493 uint32 color_key_red : 8; 494 uint32 _reserved5 : 8; 495 // (0x54) DCLRKM - destination color key mask 496 uint32 color_key_mask_blue : 8; 497 uint32 color_key_mask_green : 8; 498 uint32 color_key_mask_red : 8; 499 uint32 _reserved6 : 7; 500 uint32 color_key_enabled : 1; 501 // (0x58) SCHRKVH - source chroma key high value 502 uint32 source_chroma_key_high_red : 8; 503 uint32 source_chroma_key_high_blue : 8; 504 uint32 source_chroma_key_high_green : 8; 505 uint32 _reserved7 : 8; 506 // (0x5c) SCHRKVL - source chroma key low value 507 uint32 source_chroma_key_low_red : 8; 508 uint32 source_chroma_key_low_blue : 8; 509 uint32 source_chroma_key_low_green : 8; 510 uint32 _reserved8 : 8; 511 // (0x60) SCHRKEN - source chroma key enable 512 uint32 _reserved9 : 24; 513 uint32 source_chroma_key_red_enabled : 1; 514 uint32 source_chroma_key_blue_enabled : 1; 515 uint32 source_chroma_key_green_enabled : 1; 516 uint32 _reserved10 : 5; 517 // (0x64) OCONFIG - overlay configuration 518 uint32 _reserved11 : 3; 519 uint32 color_control_output_mode : 1; 520 uint32 yuv_to_rgb_bypass : 1; 521 uint32 _reserved12 : 11; 522 uint32 gamma2_enabled : 1; 523 uint32 _reserved13 : 1; 524 uint32 select_pipe : 1; 525 uint32 slot_time : 8; 526 uint32 _reserved14 : 5; 527 // (0x68) OCOMD - overlay command 528 uint32 overlay_enabled : 1; 529 uint32 active_field : 1; 530 uint32 active_buffer : 2; 531 uint32 test_mode : 1; 532 uint32 buffer_field_mode : 1; 533 uint32 _reserved15 : 1; 534 uint32 tv_flip_field_enabled : 1; 535 uint32 _reserved16 : 1; 536 uint32 tv_flip_field_parity : 1; 537 uint32 source_format : 4; 538 uint32 ycbcr422_order : 2; 539 uint32 _reserved18 : 1; 540 uint32 mirroring_mode : 2; 541 uint32 _reserved19 : 13; 542 543 uint32 _reserved20; 544 545 uint32 start_0y; 546 uint32 start_1y; 547 uint32 start_0u; 548 uint32 start_0v; 549 uint32 start_1u; 550 uint32 start_1v; 551 uint32 _reserved21[6]; 552 #if 0 553 // (0x70) AWINPOS - alpha blend window position 554 uint32 awinpos; 555 // (0x74) AWINSZ - alpha blend window size 556 uint32 awinsz; 557 558 uint32 _reserved21[10]; 559 #endif 560 561 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 562 // the next two registers switch the usual Y/RGB vs. UV order) 563 uint16 horizontal_scale_uv; 564 uint16 horizontal_scale_rgb; 565 // (0xa4) UVSCALEV - vertical downscale 566 uint16 vertical_scale_uv; 567 uint16 vertical_scale_rgb; 568 569 uint32 _reserved22[86]; 570 571 // (0x200) polyphase filter coefficients 572 uint16 vertical_coefficients_rgb[128]; 573 uint16 horizontal_coefficients_rgb[128]; 574 575 uint32 _reserved23[64]; 576 577 // (0x500) 578 uint16 vertical_coefficients_uv[128]; 579 uint16 horizontal_coefficients_uv[128]; 580 }; 581 582 583 struct hardware_status { 584 uint32 interrupt_status_register; 585 uint32 _reserved0[3]; 586 void* primary_ring_head_storage; 587 uint32 _reserved1[3]; 588 void* secondary_ring_0_head_storage; 589 void* secondary_ring_1_head_storage; 590 uint32 _reserved2[2]; 591 void* binning_head_storage; 592 uint32 _reserved3[3]; 593 uint32 store[1008]; 594 }; 595 596 #endif /* RADEON_HD_H */ 597