1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm 18 #include "avivo_reg.h" 19 #include "r600_reg.h" 20 #include "r700_reg.h" 21 #include "evergreen_reg.h" 22 #include "si_reg.h" 23 #include "ni_reg.h" 24 25 #include <Accelerant.h> 26 #include <Drivers.h> 27 #include <edid.h> 28 #include <PCI.h> 29 30 31 #define VENDOR_ID_ATI 0x1002 32 33 // Card chipset flags 34 #define CHIP_STD (1 << 0) // Standard chipset 35 #define CHIP_X2 (1 << 1) // Dual cpu 36 #define CHIP_IGP (1 << 2) // IGP chipset 37 #define CHIP_MOBILE (1 << 3) // Mobile chipset 38 #define CHIP_DISCREET (1 << 4) // Discreet chipset 39 #define CHIP_APU (1 << 5) // APU chipset 40 41 #define DEVICE_NAME "radeon_hd" 42 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 43 44 #define MAX_NAME_LENGTH 32 45 46 // Used to collect EDID from boot loader 47 #define EDID_BOOT_INFO "vesa_edid/v1" 48 #define MODES_BOOT_INFO "vesa_modes/v1" 49 50 #define RHD_POWER_ON 0 51 #define RHD_POWER_RESET 1 /* off temporarily */ 52 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 53 #define RHD_POWER_UNKNOWN 3 /* initial state */ 54 55 56 // Radeon Chipsets 57 // !! Must match chipset names below 58 enum radeon_chipset { 59 RADEON_R420 = 0, //r400, Radeon X700-X850 60 RADEON_R423, 61 RADEON_RV410, 62 RADEON_RS400, 63 RADEON_RS480, 64 RADEON_RS600, 65 RADEON_RS690, 66 RADEON_RS740, 67 RADEON_RV515, 68 RADEON_R520, //r500, DCE 1.0 69 RADEON_RV530, // DCE 1.0 70 RADEON_RV560, // DCE 1.0 71 RADEON_RV570, // DCE 1.0 72 RADEON_R580, // DCE 1.0 73 RADEON_R600, //r600, DCE 2.0 74 RADEON_RV610, // DCE 2.0 75 RADEON_RV630, // DCE 2.0 76 RADEON_RV670, // DCE 2.0 77 RADEON_RV620, // DCE 3.0 78 RADEON_RV635, // DCE 3.0 79 RADEON_RS780, // DCE 3.0 80 RADEON_RS880, // DCE 3.0 81 RADEON_RV770, //r700, DCE 3.1 82 RADEON_RV730, // DCE 3.2 83 RADEON_RV710, // DCE 3.2 84 RADEON_RV740, // DCE 3.2 85 RADEON_CEDAR, //Evergreen, DCE 4.0 86 RADEON_REDWOOD, // DCE 4.0 87 RADEON_JUNIPER, // DCE 4.0 88 RADEON_CYPRESS, // DCE 4.0 89 RADEON_HEMLOCK, // DCE 4.0? 90 RADEON_PALM, //Fusion APU (NI), DCE 4.1 91 RADEON_SUMO, // DCE 4.1 92 RADEON_SUMO2, // DCE 4.1 93 RADEON_CAICOS, //Nothern Islands, DCE 5.0 94 RADEON_TURKS, // DCE 5.0 95 RADEON_BARTS, // DCE 5.0 96 RADEON_CAYMAN, // DCE 5.0 97 RADEON_ANTILLES, // DCE 5.0? 98 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 99 RADEON_PITCAIRN, // DCE 6.0 100 RADEON_TAHITI, // DCE 6.0 101 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 102 RADEON_OLAND, // DCE 6.4 103 RADEON_HAINAN, // NO DCE, only compute 104 RADEON_KAVERI, //Sea Islands, DCE 8.1 105 RADEON_BONAIRE, // DCE 8.2 106 RADEON_KABINI, // DCE 8.3 107 RADEON_MULLINS, // DCE 8.3 108 RADEON_HAWAII, // ?? 109 }; 110 111 // !! Must match chipset families above 112 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 113 "R420", 114 "R423", 115 "RV410", 116 "RS400", 117 "RS480", 118 "RS600", 119 "RS690", 120 "RS740", 121 "RV515", 122 "R520", 123 "RV530", 124 "RV560", 125 "RV570", 126 "R580", 127 "R600", 128 "RV610", 129 "RV630", 130 "RV670", 131 "RV620", 132 "RV635", 133 "RS780", 134 "RS880", 135 "RV770", 136 "RV730", 137 "RV710", 138 "RV740", 139 "Cedar", 140 "Redwood", 141 "Juniper", 142 "Cypress", 143 "Hemlock", 144 "Palm", 145 "Sumo", 146 "Sumo2", 147 "Caicos", 148 "Turks", 149 "Barts", 150 "Cayman", 151 "Antilles", 152 "Cape Verde", 153 "Pitcairn", 154 "Tahiti", 155 "Aruba", 156 "Oland", 157 "Hainan", 158 "Kaveri", 159 "Bonaire", 160 "Kabini", 161 "Mullins", 162 "Hawaii" 163 }; 164 165 166 struct ring_buffer { 167 struct lock lock; 168 uint32 register_base; 169 uint32 offset; 170 uint32 size; 171 uint32 position; 172 uint32 space_left; 173 uint8* base; 174 }; 175 176 177 struct overlay_registers; 178 179 180 struct radeon_shared_info { 181 uint32 deviceIndex; // accelerant index 182 uint32 pciID; // device pciid 183 area_id mode_list_area; // area containing display mode list 184 uint32 mode_count; 185 186 bool has_rom; // was rom mapped? 187 area_id rom_area; // area of mapped rom 188 uint32 rom_phys; // rom base location 189 uint32 rom_size; // rom size 190 uint8* rom; // cloned, memory mapped PCI ROM 191 192 display_mode current_mode; 193 uint32 bytes_per_row; 194 uint32 bits_per_pixel; 195 uint32 dpms_mode; 196 197 area_id registers_area; // area of memory mapped registers 198 uint8* status_page; 199 addr_t physical_status_page; 200 uint32 graphics_memory_size; 201 202 uint8* frame_buffer; // virtual memory mapped FB 203 area_id frame_buffer_area; // area of memory mapped FB 204 addr_t frame_buffer_phys; // card PCI BAR address of FB 205 uint32 frame_buffer_size; // FB size mapped 206 207 bool has_edid; 208 edid1_info edid_info; 209 210 struct lock accelerant_lock; 211 struct lock engine_lock; 212 213 ring_buffer primary_ring_buffer; 214 215 int32 overlay_channel_used; 216 bool overlay_active; 217 uint32 overlay_token; 218 addr_t physical_overlay_registers; 219 uint32 overlay_offset; 220 221 bool hardware_cursor_enabled; 222 sem_id vblank_sem; 223 224 uint8* cursor_memory; 225 addr_t physical_cursor_memory; 226 uint32 cursor_buffer_offset; 227 uint32 cursor_format; 228 bool cursor_visible; 229 uint16 cursor_hot_x; 230 uint16 cursor_hot_y; 231 232 char deviceName[MAX_NAME_LENGTH]; 233 uint16 chipsetID; 234 char chipsetName[MAX_NAME_LENGTH]; 235 uint32 chipsetFlags; 236 uint8 dceMajor; 237 uint8 dceMinor; 238 239 uint16 color_data[3 * 256]; // colour lookup table 240 }; 241 242 //----------------- ioctl() interface ---------------- 243 244 // magic code for ioctls 245 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 246 247 // list ioctls 248 enum { 249 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 250 251 RADEON_GET_DEVICE_NAME, 252 RADEON_ALLOCATE_GRAPHICS_MEMORY, 253 RADEON_FREE_GRAPHICS_MEMORY 254 }; 255 256 // retrieve the area_id of the kernel/accelerant shared info 257 struct radeon_get_private_data { 258 uint32 magic; // magic number 259 area_id shared_info_area; 260 }; 261 262 // allocate graphics memory 263 struct radeon_allocate_graphics_memory { 264 uint32 magic; 265 uint32 size; 266 uint32 alignment; 267 uint32 flags; 268 uint32 buffer_base; 269 }; 270 271 // free graphics memory 272 struct radeon_free_graphics_memory { 273 uint32 magic; 274 uint32 buffer_base; 275 }; 276 277 // registers 278 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 279 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 280 #define CONFIG_MEMSIZE 0x5428 // r600> 281 282 // PCI bridge memory management 283 284 // overlay 285 286 #define RADEON_OVERLAY_UPDATE 0x30000 287 #define RADEON_OVERLAY_TEST 0x30004 288 #define RADEON_OVERLAY_STATUS 0x30008 289 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 290 #define RADEON_OVERLAY_GAMMA_5 0x30010 291 #define RADEON_OVERLAY_GAMMA_4 0x30014 292 #define RADEON_OVERLAY_GAMMA_3 0x30018 293 #define RADEON_OVERLAY_GAMMA_2 0x3001c 294 #define RADEON_OVERLAY_GAMMA_1 0x30020 295 #define RADEON_OVERLAY_GAMMA_0 0x30024 296 297 struct overlay_scale { 298 uint32 _reserved0 : 3; 299 uint32 horizontal_scale_fraction : 12; 300 uint32 _reserved1 : 1; 301 uint32 horizontal_downscale_factor : 3; 302 uint32 _reserved2 : 1; 303 uint32 vertical_scale_fraction : 12; 304 }; 305 306 #define OVERLAY_FORMAT_RGB15 0x2 307 #define OVERLAY_FORMAT_RGB16 0x3 308 #define OVERLAY_FORMAT_RGB32 0x1 309 #define OVERLAY_FORMAT_YCbCr422 0x8 310 #define OVERLAY_FORMAT_YCbCr411 0x9 311 #define OVERLAY_FORMAT_YCbCr420 0xc 312 313 #define OVERLAY_MIRROR_NORMAL 0x0 314 #define OVERLAY_MIRROR_HORIZONTAL 0x1 315 #define OVERLAY_MIRROR_VERTICAL 0x2 316 317 // The real overlay registers are written to using an update buffer 318 319 struct overlay_registers { 320 uint32 buffer_rgb0; 321 uint32 buffer_rgb1; 322 uint32 buffer_u0; 323 uint32 buffer_v0; 324 uint32 buffer_u1; 325 uint32 buffer_v1; 326 // (0x18) OSTRIDE - overlay stride 327 uint16 stride_rgb; 328 uint16 stride_uv; 329 // (0x1c) YRGB_VPH - Y/RGB vertical phase 330 uint16 vertical_phase0_rgb; 331 uint16 vertical_phase1_rgb; 332 // (0x20) UV_VPH - UV vertical phase 333 uint16 vertical_phase0_uv; 334 uint16 vertical_phase1_uv; 335 // (0x24) HORZ_PH - horizontal phase 336 uint16 horizontal_phase_rgb; 337 uint16 horizontal_phase_uv; 338 // (0x28) INIT_PHS - initial phase shift 339 uint32 initial_vertical_phase0_shift_rgb0 : 4; 340 uint32 initial_vertical_phase1_shift_rgb0 : 4; 341 uint32 initial_horizontal_phase_shift_rgb0 : 4; 342 uint32 initial_vertical_phase0_shift_uv : 4; 343 uint32 initial_vertical_phase1_shift_uv : 4; 344 uint32 initial_horizontal_phase_shift_uv : 4; 345 uint32 _reserved0 : 8; 346 // (0x2c) DWINPOS - destination window position 347 uint16 window_left; 348 uint16 window_top; 349 // (0x30) DWINSZ - destination window size 350 uint16 window_width; 351 uint16 window_height; 352 // (0x34) SWIDTH - source width 353 uint16 source_width_rgb; 354 uint16 source_width_uv; 355 // (0x38) SWITDHSW - source width in 8 byte steps 356 uint16 source_bytes_per_row_rgb; 357 uint16 source_bytes_per_row_uv; 358 uint16 source_height_rgb; 359 uint16 source_height_uv; 360 overlay_scale scale_rgb; 361 overlay_scale scale_uv; 362 // (0x48) OCLRC0 - overlay color correction 0 363 uint32 brightness_correction : 8; // signed, -128 to 127 364 uint32 _reserved1 : 10; 365 uint32 contrast_correction : 9; // fixed point: 3.6 bits 366 uint32 _reserved2 : 5; 367 // (0x4c) OCLRC1 - overlay color correction 1 368 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 369 uint32 _reserved3 : 6; 370 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 371 uint32 _reserved4 : 5; 372 // (0x50) DCLRKV - destination color key value 373 uint32 color_key_blue : 8; 374 uint32 color_key_green : 8; 375 uint32 color_key_red : 8; 376 uint32 _reserved5 : 8; 377 // (0x54) DCLRKM - destination color key mask 378 uint32 color_key_mask_blue : 8; 379 uint32 color_key_mask_green : 8; 380 uint32 color_key_mask_red : 8; 381 uint32 _reserved6 : 7; 382 uint32 color_key_enabled : 1; 383 // (0x58) SCHRKVH - source chroma key high value 384 uint32 source_chroma_key_high_red : 8; 385 uint32 source_chroma_key_high_blue : 8; 386 uint32 source_chroma_key_high_green : 8; 387 uint32 _reserved7 : 8; 388 // (0x5c) SCHRKVL - source chroma key low value 389 uint32 source_chroma_key_low_red : 8; 390 uint32 source_chroma_key_low_blue : 8; 391 uint32 source_chroma_key_low_green : 8; 392 uint32 _reserved8 : 8; 393 // (0x60) SCHRKEN - source chroma key enable 394 uint32 _reserved9 : 24; 395 uint32 source_chroma_key_red_enabled : 1; 396 uint32 source_chroma_key_blue_enabled : 1; 397 uint32 source_chroma_key_green_enabled : 1; 398 uint32 _reserved10 : 5; 399 // (0x64) OCONFIG - overlay configuration 400 uint32 _reserved11 : 3; 401 uint32 color_control_output_mode : 1; 402 uint32 yuv_to_rgb_bypass : 1; 403 uint32 _reserved12 : 11; 404 uint32 gamma2_enabled : 1; 405 uint32 _reserved13 : 1; 406 uint32 select_pipe : 1; 407 uint32 slot_time : 8; 408 uint32 _reserved14 : 5; 409 // (0x68) OCOMD - overlay command 410 uint32 overlay_enabled : 1; 411 uint32 active_field : 1; 412 uint32 active_buffer : 2; 413 uint32 test_mode : 1; 414 uint32 buffer_field_mode : 1; 415 uint32 _reserved15 : 1; 416 uint32 tv_flip_field_enabled : 1; 417 uint32 _reserved16 : 1; 418 uint32 tv_flip_field_parity : 1; 419 uint32 source_format : 4; 420 uint32 ycbcr422_order : 2; 421 uint32 _reserved18 : 1; 422 uint32 mirroring_mode : 2; 423 uint32 _reserved19 : 13; 424 425 uint32 _reserved20; 426 427 uint32 start_0y; 428 uint32 start_1y; 429 uint32 start_0u; 430 uint32 start_0v; 431 uint32 start_1u; 432 uint32 start_1v; 433 uint32 _reserved21[6]; 434 #if 0 435 // (0x70) AWINPOS - alpha blend window position 436 uint32 awinpos; 437 // (0x74) AWINSZ - alpha blend window size 438 uint32 awinsz; 439 440 uint32 _reserved21[10]; 441 #endif 442 443 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 444 // the next two registers switch the usual Y/RGB vs. UV order) 445 uint16 horizontal_scale_uv; 446 uint16 horizontal_scale_rgb; 447 // (0xa4) UVSCALEV - vertical downscale 448 uint16 vertical_scale_uv; 449 uint16 vertical_scale_rgb; 450 451 uint32 _reserved22[86]; 452 453 // (0x200) polyphase filter coefficients 454 uint16 vertical_coefficients_rgb[128]; 455 uint16 horizontal_coefficients_rgb[128]; 456 457 uint32 _reserved23[64]; 458 459 // (0x500) 460 uint16 vertical_coefficients_uv[128]; 461 uint16 horizontal_coefficients_uv[128]; 462 }; 463 464 465 struct hardware_status { 466 uint32 interrupt_status_register; 467 uint32 _reserved0[3]; 468 void* primary_ring_head_storage; 469 uint32 _reserved1[3]; 470 void* secondary_ring_0_head_storage; 471 void* secondary_ring_1_head_storage; 472 uint32 _reserved2[2]; 473 void* binning_head_storage; 474 uint32 _reserved3[3]; 475 uint32 store[1008]; 476 }; 477 478 #endif /* RADEON_HD_H */ 479