1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 28 #include <Accelerant.h> 29 #include <Drivers.h> 30 #include <edid.h> 31 #include <PCI.h> 32 33 34 #define VENDOR_ID_ATI 0x1002 35 36 // Card chipset flags 37 #define CHIP_STD (1 << 0) // Standard chipset 38 #define CHIP_X2 (1 << 1) // Dual cpu 39 #define CHIP_IGP (1 << 2) // IGP chipset 40 #define CHIP_MOBILE (1 << 3) // Mobile chipset 41 #define CHIP_DISCREET (1 << 4) // Discreet chipset 42 #define CHIP_APU (1 << 5) // APU chipset 43 44 #define DEVICE_NAME "radeon_hd" 45 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 46 47 #define MAX_NAME_LENGTH 32 48 49 // Used to collect EDID from boot loader 50 #define EDID_BOOT_INFO "vesa_edid/v1" 51 #define MODES_BOOT_INFO "vesa_modes/v1" 52 53 #define RHD_POWER_ON 0 54 #define RHD_POWER_RESET 1 /* off temporarily */ 55 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 56 #define RHD_POWER_UNKNOWN 3 /* initial state */ 57 58 59 // Radeon Chipsets 60 // !! Must match chipset names below 61 enum radeon_chipset { 62 RADEON_R420 = 0, //r400, Radeon X700-X850 63 RADEON_R423, 64 RADEON_RV410, 65 RADEON_RS400, 66 RADEON_RS480, 67 RADEON_RS600, 68 RADEON_RS690, 69 RADEON_RS740, 70 RADEON_RV515, 71 RADEON_R520, //r500, DCE 1.0 72 RADEON_RV530, // DCE 1.0 73 RADEON_RV560, // DCE 1.0 74 RADEON_RV570, // DCE 1.0 75 RADEON_R580, // DCE 1.0 76 RADEON_R600, //r600, DCE 2.0 77 RADEON_RV610, // DCE 2.0 78 RADEON_RV630, // DCE 2.0 79 RADEON_RV670, // DCE 2.0 80 RADEON_RV620, // DCE 3.0 81 RADEON_RV635, // DCE 3.0 82 RADEON_RS780, // DCE 3.0 83 RADEON_RS880, // DCE 3.0 84 RADEON_RV770, //r700, DCE 3.1 85 RADEON_RV730, // DCE 3.2 86 RADEON_RV710, // DCE 3.2 87 RADEON_RV740, // DCE 3.2 88 RADEON_CEDAR, //Evergreen, DCE 4.0 89 RADEON_REDWOOD, // DCE 4.0 90 RADEON_JUNIPER, // DCE 4.0 91 RADEON_CYPRESS, // DCE 4.0 92 RADEON_HEMLOCK, // DCE 4.0? 93 RADEON_PALM, //Fusion APU (NI), DCE 4.1 94 RADEON_SUMO, // DCE 4.1 95 RADEON_SUMO2, // DCE 4.1 96 RADEON_CAICOS, //Nothern Islands, DCE 5.0 97 RADEON_TURKS, // DCE 5.0 98 RADEON_BARTS, // DCE 5.0 99 RADEON_CAYMAN, // DCE 5.0 100 RADEON_ANTILLES, // DCE 5.0? 101 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 102 RADEON_PITCAIRN, // DCE 6.0 103 RADEON_TAHITI, // DCE 6.0 104 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 105 RADEON_OLAND, // DCE 6.4 106 RADEON_HAINAN, // NO DCE, only compute 107 RADEON_KAVERI, //Sea Islands, DCE 8.1 108 RADEON_BONAIRE, // DCE 8.2 109 RADEON_KABINI, // DCE 8.3 110 RADEON_MULLINS, // DCE 8.3 111 RADEON_HAWAII, // DCE 8.5 112 RADEON_TOPAZ, //Volcanic Islands, NO DCE 113 RADEON_TONGA, // DCE 10.0 114 RADEON_CARRIZO, // DCE 11.0 115 RADEON_POLARIS //Artic Islands, DCE 12.0 116 }; 117 118 // !! Must match chipset families above 119 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 120 "R420", 121 "R423", 122 "RV410", 123 "RS400", 124 "RS480", 125 "RS600", 126 "RS690", 127 "RS740", 128 "RV515", 129 "R520", 130 "RV530", 131 "RV560", 132 "RV570", 133 "R580", 134 "R600", 135 "RV610", 136 "RV630", 137 "RV670", 138 "RV620", 139 "RV635", 140 "RS780", 141 "RS880", 142 "RV770", 143 "RV730", 144 "RV710", 145 "RV740", 146 "Cedar", 147 "Redwood", 148 "Juniper", 149 "Cypress", 150 "Hemlock", 151 "Palm", 152 "Sumo", 153 "Sumo2", 154 "Caicos", 155 "Turks", 156 "Barts", 157 "Cayman", 158 "Antilles", 159 "Cape Verde", 160 "Pitcairn", 161 "Tahiti", 162 "Aruba", 163 "Oland", 164 "Hainan", 165 "Kaveri", 166 "Bonaire", 167 "Kabini", 168 "Mullins", 169 "Hawaii", 170 "Topaz", 171 "Tonga", 172 "Carrizo", 173 "Polaris" 174 }; 175 176 177 struct ring_buffer { 178 struct lock lock; 179 uint32 register_base; 180 uint32 offset; 181 uint32 size; 182 uint32 position; 183 uint32 space_left; 184 uint8* base; 185 }; 186 187 188 struct overlay_registers; 189 190 191 struct radeon_shared_info { 192 uint32 deviceIndex; // accelerant index 193 uint32 pciID; // device pci id 194 uint32 pciRev; // device pci revision 195 area_id mode_list_area; // area containing display mode list 196 uint32 mode_count; 197 198 bool has_rom; // was rom mapped? 199 area_id rom_area; // area of mapped rom 200 uint32 rom_phys; // rom base location 201 uint32 rom_size; // rom size 202 uint8* rom; // cloned, memory mapped PCI ROM 203 204 display_mode current_mode; 205 uint32 bytes_per_row; 206 uint32 bits_per_pixel; 207 uint32 dpms_mode; 208 209 area_id registers_area; // area of memory mapped registers 210 uint8* status_page; 211 addr_t physical_status_page; 212 uint32 graphics_memory_size; 213 214 uint8* frame_buffer; // virtual memory mapped FB 215 area_id frame_buffer_area; // area of memory mapped FB 216 addr_t frame_buffer_phys; // card PCI BAR address of FB 217 uint32 frame_buffer_size; // FB size mapped 218 219 bool has_edid; 220 edid1_info edid_info; 221 222 struct lock accelerant_lock; 223 struct lock engine_lock; 224 225 ring_buffer primary_ring_buffer; 226 227 int32 overlay_channel_used; 228 bool overlay_active; 229 uint32 overlay_token; 230 addr_t physical_overlay_registers; 231 uint32 overlay_offset; 232 233 bool hardware_cursor_enabled; 234 sem_id vblank_sem; 235 236 uint8* cursor_memory; 237 addr_t physical_cursor_memory; 238 uint32 cursor_buffer_offset; 239 uint32 cursor_format; 240 bool cursor_visible; 241 uint16 cursor_hot_x; 242 uint16 cursor_hot_y; 243 244 char deviceName[MAX_NAME_LENGTH]; 245 uint16 chipsetID; 246 char chipsetName[MAX_NAME_LENGTH]; 247 uint32 chipsetFlags; 248 uint8 dceMajor; 249 uint8 dceMinor; 250 251 uint16 color_data[3 * 256]; // colour lookup table 252 }; 253 254 //----------------- ioctl() interface ---------------- 255 256 // magic code for ioctls 257 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 258 259 // list ioctls 260 enum { 261 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 262 263 RADEON_GET_DEVICE_NAME, 264 RADEON_ALLOCATE_GRAPHICS_MEMORY, 265 RADEON_FREE_GRAPHICS_MEMORY 266 }; 267 268 // retrieve the area_id of the kernel/accelerant shared info 269 struct radeon_get_private_data { 270 uint32 magic; // magic number 271 area_id shared_info_area; 272 }; 273 274 // allocate graphics memory 275 struct radeon_allocate_graphics_memory { 276 uint32 magic; 277 uint32 size; 278 uint32 alignment; 279 uint32 flags; 280 uint32 buffer_base; 281 }; 282 283 // free graphics memory 284 struct radeon_free_graphics_memory { 285 uint32 magic; 286 uint32 buffer_base; 287 }; 288 289 // registers 290 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 291 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 292 #define CONFIG_MEMSIZE 0x5428 // r600> 293 294 // PCI bridge memory management 295 296 // overlay 297 298 #define RADEON_OVERLAY_UPDATE 0x30000 299 #define RADEON_OVERLAY_TEST 0x30004 300 #define RADEON_OVERLAY_STATUS 0x30008 301 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 302 #define RADEON_OVERLAY_GAMMA_5 0x30010 303 #define RADEON_OVERLAY_GAMMA_4 0x30014 304 #define RADEON_OVERLAY_GAMMA_3 0x30018 305 #define RADEON_OVERLAY_GAMMA_2 0x3001c 306 #define RADEON_OVERLAY_GAMMA_1 0x30020 307 #define RADEON_OVERLAY_GAMMA_0 0x30024 308 309 struct overlay_scale { 310 uint32 _reserved0 : 3; 311 uint32 horizontal_scale_fraction : 12; 312 uint32 _reserved1 : 1; 313 uint32 horizontal_downscale_factor : 3; 314 uint32 _reserved2 : 1; 315 uint32 vertical_scale_fraction : 12; 316 }; 317 318 #define OVERLAY_FORMAT_RGB15 0x2 319 #define OVERLAY_FORMAT_RGB16 0x3 320 #define OVERLAY_FORMAT_RGB32 0x1 321 #define OVERLAY_FORMAT_YCbCr422 0x8 322 #define OVERLAY_FORMAT_YCbCr411 0x9 323 #define OVERLAY_FORMAT_YCbCr420 0xc 324 325 #define OVERLAY_MIRROR_NORMAL 0x0 326 #define OVERLAY_MIRROR_HORIZONTAL 0x1 327 #define OVERLAY_MIRROR_VERTICAL 0x2 328 329 // The real overlay registers are written to using an update buffer 330 331 struct overlay_registers { 332 uint32 buffer_rgb0; 333 uint32 buffer_rgb1; 334 uint32 buffer_u0; 335 uint32 buffer_v0; 336 uint32 buffer_u1; 337 uint32 buffer_v1; 338 // (0x18) OSTRIDE - overlay stride 339 uint16 stride_rgb; 340 uint16 stride_uv; 341 // (0x1c) YRGB_VPH - Y/RGB vertical phase 342 uint16 vertical_phase0_rgb; 343 uint16 vertical_phase1_rgb; 344 // (0x20) UV_VPH - UV vertical phase 345 uint16 vertical_phase0_uv; 346 uint16 vertical_phase1_uv; 347 // (0x24) HORZ_PH - horizontal phase 348 uint16 horizontal_phase_rgb; 349 uint16 horizontal_phase_uv; 350 // (0x28) INIT_PHS - initial phase shift 351 uint32 initial_vertical_phase0_shift_rgb0 : 4; 352 uint32 initial_vertical_phase1_shift_rgb0 : 4; 353 uint32 initial_horizontal_phase_shift_rgb0 : 4; 354 uint32 initial_vertical_phase0_shift_uv : 4; 355 uint32 initial_vertical_phase1_shift_uv : 4; 356 uint32 initial_horizontal_phase_shift_uv : 4; 357 uint32 _reserved0 : 8; 358 // (0x2c) DWINPOS - destination window position 359 uint16 window_left; 360 uint16 window_top; 361 // (0x30) DWINSZ - destination window size 362 uint16 window_width; 363 uint16 window_height; 364 // (0x34) SWIDTH - source width 365 uint16 source_width_rgb; 366 uint16 source_width_uv; 367 // (0x38) SWITDHSW - source width in 8 byte steps 368 uint16 source_bytes_per_row_rgb; 369 uint16 source_bytes_per_row_uv; 370 uint16 source_height_rgb; 371 uint16 source_height_uv; 372 overlay_scale scale_rgb; 373 overlay_scale scale_uv; 374 // (0x48) OCLRC0 - overlay color correction 0 375 uint32 brightness_correction : 8; // signed, -128 to 127 376 uint32 _reserved1 : 10; 377 uint32 contrast_correction : 9; // fixed point: 3.6 bits 378 uint32 _reserved2 : 5; 379 // (0x4c) OCLRC1 - overlay color correction 1 380 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 381 uint32 _reserved3 : 6; 382 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 383 uint32 _reserved4 : 5; 384 // (0x50) DCLRKV - destination color key value 385 uint32 color_key_blue : 8; 386 uint32 color_key_green : 8; 387 uint32 color_key_red : 8; 388 uint32 _reserved5 : 8; 389 // (0x54) DCLRKM - destination color key mask 390 uint32 color_key_mask_blue : 8; 391 uint32 color_key_mask_green : 8; 392 uint32 color_key_mask_red : 8; 393 uint32 _reserved6 : 7; 394 uint32 color_key_enabled : 1; 395 // (0x58) SCHRKVH - source chroma key high value 396 uint32 source_chroma_key_high_red : 8; 397 uint32 source_chroma_key_high_blue : 8; 398 uint32 source_chroma_key_high_green : 8; 399 uint32 _reserved7 : 8; 400 // (0x5c) SCHRKVL - source chroma key low value 401 uint32 source_chroma_key_low_red : 8; 402 uint32 source_chroma_key_low_blue : 8; 403 uint32 source_chroma_key_low_green : 8; 404 uint32 _reserved8 : 8; 405 // (0x60) SCHRKEN - source chroma key enable 406 uint32 _reserved9 : 24; 407 uint32 source_chroma_key_red_enabled : 1; 408 uint32 source_chroma_key_blue_enabled : 1; 409 uint32 source_chroma_key_green_enabled : 1; 410 uint32 _reserved10 : 5; 411 // (0x64) OCONFIG - overlay configuration 412 uint32 _reserved11 : 3; 413 uint32 color_control_output_mode : 1; 414 uint32 yuv_to_rgb_bypass : 1; 415 uint32 _reserved12 : 11; 416 uint32 gamma2_enabled : 1; 417 uint32 _reserved13 : 1; 418 uint32 select_pipe : 1; 419 uint32 slot_time : 8; 420 uint32 _reserved14 : 5; 421 // (0x68) OCOMD - overlay command 422 uint32 overlay_enabled : 1; 423 uint32 active_field : 1; 424 uint32 active_buffer : 2; 425 uint32 test_mode : 1; 426 uint32 buffer_field_mode : 1; 427 uint32 _reserved15 : 1; 428 uint32 tv_flip_field_enabled : 1; 429 uint32 _reserved16 : 1; 430 uint32 tv_flip_field_parity : 1; 431 uint32 source_format : 4; 432 uint32 ycbcr422_order : 2; 433 uint32 _reserved18 : 1; 434 uint32 mirroring_mode : 2; 435 uint32 _reserved19 : 13; 436 437 uint32 _reserved20; 438 439 uint32 start_0y; 440 uint32 start_1y; 441 uint32 start_0u; 442 uint32 start_0v; 443 uint32 start_1u; 444 uint32 start_1v; 445 uint32 _reserved21[6]; 446 #if 0 447 // (0x70) AWINPOS - alpha blend window position 448 uint32 awinpos; 449 // (0x74) AWINSZ - alpha blend window size 450 uint32 awinsz; 451 452 uint32 _reserved21[10]; 453 #endif 454 455 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 456 // the next two registers switch the usual Y/RGB vs. UV order) 457 uint16 horizontal_scale_uv; 458 uint16 horizontal_scale_rgb; 459 // (0xa4) UVSCALEV - vertical downscale 460 uint16 vertical_scale_uv; 461 uint16 vertical_scale_rgb; 462 463 uint32 _reserved22[86]; 464 465 // (0x200) polyphase filter coefficients 466 uint16 vertical_coefficients_rgb[128]; 467 uint16 horizontal_coefficients_rgb[128]; 468 469 uint32 _reserved23[64]; 470 471 // (0x500) 472 uint16 vertical_coefficients_uv[128]; 473 uint16 horizontal_coefficients_uv[128]; 474 }; 475 476 477 struct hardware_status { 478 uint32 interrupt_status_register; 479 uint32 _reserved0[3]; 480 void* primary_ring_head_storage; 481 uint32 _reserved1[3]; 482 void* secondary_ring_0_head_storage; 483 void* secondary_ring_1_head_storage; 484 uint32 _reserved2[2]; 485 void* binning_head_storage; 486 uint32 _reserved3[3]; 487 uint32 store[1008]; 488 }; 489 490 #endif /* RADEON_HD_H */ 491