1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 28 #include <Accelerant.h> 29 #include <Drivers.h> 30 #include <edid.h> 31 #include <PCI.h> 32 33 34 #define VENDOR_ID_ATI 0x1002 35 36 // Card chipset flags 37 #define CHIP_STD (1 << 0) // Standard chipset 38 #define CHIP_X2 (1 << 1) // Dual cpu 39 #define CHIP_IGP (1 << 2) // IGP chipset 40 #define CHIP_MOBILE (1 << 3) // Mobile chipset 41 #define CHIP_DISCREET (1 << 4) // Discreet chipset 42 #define CHIP_APU (1 << 5) // APU chipset 43 44 #define DEVICE_NAME "radeon_hd" 45 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 46 47 #define MAX_NAME_LENGTH 32 48 49 // Used to collect EDID from boot loader 50 #define EDID_BOOT_INFO "vesa_edid/v1" 51 #define MODES_BOOT_INFO "vesa_modes/v1" 52 53 #define RHD_POWER_ON 0 54 #define RHD_POWER_RESET 1 /* off temporarily */ 55 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 56 #define RHD_POWER_UNKNOWN 3 /* initial state */ 57 58 59 // Radeon Chipsets 60 // !! Must match chipset names below 61 enum radeon_chipset { 62 RADEON_R420 = 0, //r400, Radeon X700-X850 63 RADEON_R423, 64 RADEON_RV410, 65 RADEON_RS400, 66 RADEON_RS480, 67 RADEON_RS600, 68 RADEON_RS690, 69 RADEON_RS740, 70 RADEON_RV515, 71 RADEON_R520, //r500, DCE 1.0 72 RADEON_RV530, // DCE 1.0 73 RADEON_RV560, // DCE 1.0 74 RADEON_RV570, // DCE 1.0 75 RADEON_R580, // DCE 1.0 76 RADEON_R600, //r600, DCE 2.0 77 RADEON_RV610, // DCE 2.0 78 RADEON_RV630, // DCE 2.0 79 RADEON_RV670, // DCE 2.0 80 RADEON_RV620, // DCE 3.0 81 RADEON_RV635, // DCE 3.0 82 RADEON_RS780, // DCE 3.0 83 RADEON_RS880, // DCE 3.0 84 RADEON_RV770, //r700, DCE 3.1 85 RADEON_RV730, // DCE 3.2 86 RADEON_RV710, // DCE 3.2 87 RADEON_RV740, // DCE 3.2 88 RADEON_CEDAR, //Evergreen, DCE 4.0 89 RADEON_REDWOOD, // DCE 4.0 90 RADEON_JUNIPER, // DCE 4.0 91 RADEON_CYPRESS, // DCE 4.0 92 RADEON_HEMLOCK, // DCE 4.0? 93 RADEON_PALM, //Fusion APU (NI), DCE 4.1 94 RADEON_SUMO, // DCE 4.1 95 RADEON_SUMO2, // DCE 4.1 96 RADEON_CAICOS, //Nothern Islands, DCE 5.0 97 RADEON_TURKS, // DCE 5.0 98 RADEON_BARTS, // DCE 5.0 99 RADEON_CAYMAN, // DCE 5.0 100 RADEON_ANTILLES, // DCE 5.0? 101 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 102 RADEON_PITCAIRN, // DCE 6.0 103 RADEON_TAHITI, // DCE 6.0 104 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 105 RADEON_OLAND, // DCE 6.4 106 RADEON_HAINAN, // NO DCE, only compute 107 RADEON_KAVERI, //Sea Islands, DCE 8.1 108 RADEON_BONAIRE, // DCE 8.2 109 RADEON_KABINI, // DCE 8.3 110 RADEON_MULLINS, // DCE 8.3 111 RADEON_HAWAII, // DCE 8.5 112 RADEON_TOPAZ, //Volcanic Islands, NO DCE 113 RADEON_TONGA, // DCE 10.0 114 RADEON_FIJI, // DCE 10.1? 115 RADEON_CARRIZO, // DCE 11.0 116 RADEON_STONEY, // DCE 11.1? 117 RADEON_POLARIS11, //Artic Islands, DCE 12.1? 118 RADEON_POLARIS10, // DCE 12.0? 119 RADEON_POLARIS12, // DCE 12.2? 120 RADEON_VEGAM, // DCE 13.0? 121 RADEON_VEGA10, // DCE 13.0? 122 RADEON_VEGA12, // DCE 13.0? 123 RADEON_VEGA20, // DCE 13.0? 124 RADEON_RAVEN, // DCE 13? 125 RADEON_NAVI, // DCE 13.0? 126 }; 127 128 // !! Must match chipset families above 129 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 130 "R420", 131 "R423", 132 "RV410", 133 "RS400", 134 "RS480", 135 "RS600", 136 "RS690", 137 "RS740", 138 "RV515", 139 "R520", 140 "RV530", 141 "RV560", 142 "RV570", 143 "R580", 144 "R600", 145 "RV610", 146 "RV630", 147 "RV670", 148 "RV620", 149 "RV635", 150 "RS780", 151 "RS880", 152 "RV770", 153 "RV730", 154 "RV710", 155 "RV740", 156 "Cedar", 157 "Redwood", 158 "Juniper", 159 "Cypress", 160 "Hemlock", 161 "Palm", 162 "Sumo", 163 "Sumo2", 164 "Caicos", 165 "Turks", 166 "Barts", 167 "Cayman", 168 "Antilles", 169 "Cape Verde", 170 "Pitcairn", 171 "Tahiti", 172 "Aruba", 173 "Oland", 174 "Hainan", 175 "Kaveri", 176 "Bonaire", 177 "Kabini", 178 "Mullins", 179 "Hawaii", 180 "Topaz", 181 "Tonga", 182 "Fiji", 183 "Carrizo", 184 "Stoney Ridge", 185 "Polaris 11", 186 "Polaris 10", 187 "Polaris 12", 188 "Vega Mobile", 189 "Vega 10", 190 "Vega 12", 191 "Vega 20", 192 "Raven", 193 "Navi", 194 }; 195 196 197 struct ring_buffer { 198 struct lock lock; 199 uint32 register_base; 200 uint32 offset; 201 uint32 size; 202 uint32 position; 203 uint32 space_left; 204 uint8* base; 205 }; 206 207 208 struct overlay_registers; 209 210 211 struct radeon_shared_info { 212 uint32 deviceIndex; // accelerant index 213 uint32 pciID; // device pci id 214 uint32 pciRev; // device pci revision 215 area_id mode_list_area; // area containing display mode list 216 uint32 mode_count; 217 218 bool has_rom; // was rom mapped? 219 area_id rom_area; // area of mapped rom 220 uint32 rom_phys; // rom base location 221 uint32 rom_size; // rom size 222 uint8* rom; // cloned, memory mapped PCI ROM 223 224 display_mode current_mode; 225 uint32 bytes_per_row; 226 uint32 bits_per_pixel; 227 uint32 dpms_mode; 228 229 area_id registers_area; // area of memory mapped registers 230 uint8* status_page; 231 addr_t physical_status_page; 232 uint32 graphics_memory_size; 233 234 uint8* frame_buffer; // virtual memory mapped FB 235 area_id frame_buffer_area; // area of memory mapped FB 236 addr_t frame_buffer_phys; // card PCI BAR address of FB 237 uint32 frame_buffer_size; // FB size mapped 238 239 bool has_edid; 240 edid1_info edid_info; 241 242 struct lock accelerant_lock; 243 struct lock engine_lock; 244 245 ring_buffer primary_ring_buffer; 246 247 int32 overlay_channel_used; 248 bool overlay_active; 249 uint32 overlay_token; 250 addr_t physical_overlay_registers; 251 uint32 overlay_offset; 252 253 bool hardware_cursor_enabled; 254 sem_id vblank_sem; 255 256 uint8* cursor_memory; 257 addr_t physical_cursor_memory; 258 uint32 cursor_buffer_offset; 259 uint32 cursor_format; 260 bool cursor_visible; 261 uint16 cursor_hot_x; 262 uint16 cursor_hot_y; 263 264 char deviceName[MAX_NAME_LENGTH]; 265 uint16 chipsetID; 266 char chipsetName[MAX_NAME_LENGTH]; 267 uint32 chipsetFlags; 268 uint8 dceMajor; 269 uint8 dceMinor; 270 271 uint16 color_data[3 * 256]; // colour lookup table 272 }; 273 274 //----------------- ioctl() interface ---------------- 275 276 // magic code for ioctls 277 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 278 279 // list ioctls 280 enum { 281 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 282 283 RADEON_GET_DEVICE_NAME, 284 RADEON_ALLOCATE_GRAPHICS_MEMORY, 285 RADEON_FREE_GRAPHICS_MEMORY 286 }; 287 288 // retrieve the area_id of the kernel/accelerant shared info 289 struct radeon_get_private_data { 290 uint32 magic; // magic number 291 area_id shared_info_area; 292 }; 293 294 // allocate graphics memory 295 struct radeon_allocate_graphics_memory { 296 uint32 magic; 297 uint32 size; 298 uint32 alignment; 299 uint32 flags; 300 uint32 buffer_base; 301 }; 302 303 // free graphics memory 304 struct radeon_free_graphics_memory { 305 uint32 magic; 306 uint32 buffer_base; 307 }; 308 309 // registers 310 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 311 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 312 #define CONFIG_MEMSIZE 0x5428 // r600> 313 314 // PCI bridge memory management 315 316 // overlay 317 318 #define RADEON_OVERLAY_UPDATE 0x30000 319 #define RADEON_OVERLAY_TEST 0x30004 320 #define RADEON_OVERLAY_STATUS 0x30008 321 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 322 #define RADEON_OVERLAY_GAMMA_5 0x30010 323 #define RADEON_OVERLAY_GAMMA_4 0x30014 324 #define RADEON_OVERLAY_GAMMA_3 0x30018 325 #define RADEON_OVERLAY_GAMMA_2 0x3001c 326 #define RADEON_OVERLAY_GAMMA_1 0x30020 327 #define RADEON_OVERLAY_GAMMA_0 0x30024 328 329 struct overlay_scale { 330 uint32 _reserved0 : 3; 331 uint32 horizontal_scale_fraction : 12; 332 uint32 _reserved1 : 1; 333 uint32 horizontal_downscale_factor : 3; 334 uint32 _reserved2 : 1; 335 uint32 vertical_scale_fraction : 12; 336 }; 337 338 #define OVERLAY_FORMAT_RGB15 0x2 339 #define OVERLAY_FORMAT_RGB16 0x3 340 #define OVERLAY_FORMAT_RGB32 0x1 341 #define OVERLAY_FORMAT_YCbCr422 0x8 342 #define OVERLAY_FORMAT_YCbCr411 0x9 343 #define OVERLAY_FORMAT_YCbCr420 0xc 344 345 #define OVERLAY_MIRROR_NORMAL 0x0 346 #define OVERLAY_MIRROR_HORIZONTAL 0x1 347 #define OVERLAY_MIRROR_VERTICAL 0x2 348 349 // The real overlay registers are written to using an update buffer 350 351 struct overlay_registers { 352 uint32 buffer_rgb0; 353 uint32 buffer_rgb1; 354 uint32 buffer_u0; 355 uint32 buffer_v0; 356 uint32 buffer_u1; 357 uint32 buffer_v1; 358 // (0x18) OSTRIDE - overlay stride 359 uint16 stride_rgb; 360 uint16 stride_uv; 361 // (0x1c) YRGB_VPH - Y/RGB vertical phase 362 uint16 vertical_phase0_rgb; 363 uint16 vertical_phase1_rgb; 364 // (0x20) UV_VPH - UV vertical phase 365 uint16 vertical_phase0_uv; 366 uint16 vertical_phase1_uv; 367 // (0x24) HORZ_PH - horizontal phase 368 uint16 horizontal_phase_rgb; 369 uint16 horizontal_phase_uv; 370 // (0x28) INIT_PHS - initial phase shift 371 uint32 initial_vertical_phase0_shift_rgb0 : 4; 372 uint32 initial_vertical_phase1_shift_rgb0 : 4; 373 uint32 initial_horizontal_phase_shift_rgb0 : 4; 374 uint32 initial_vertical_phase0_shift_uv : 4; 375 uint32 initial_vertical_phase1_shift_uv : 4; 376 uint32 initial_horizontal_phase_shift_uv : 4; 377 uint32 _reserved0 : 8; 378 // (0x2c) DWINPOS - destination window position 379 uint16 window_left; 380 uint16 window_top; 381 // (0x30) DWINSZ - destination window size 382 uint16 window_width; 383 uint16 window_height; 384 // (0x34) SWIDTH - source width 385 uint16 source_width_rgb; 386 uint16 source_width_uv; 387 // (0x38) SWITDHSW - source width in 8 byte steps 388 uint16 source_bytes_per_row_rgb; 389 uint16 source_bytes_per_row_uv; 390 uint16 source_height_rgb; 391 uint16 source_height_uv; 392 overlay_scale scale_rgb; 393 overlay_scale scale_uv; 394 // (0x48) OCLRC0 - overlay color correction 0 395 uint32 brightness_correction : 8; // signed, -128 to 127 396 uint32 _reserved1 : 10; 397 uint32 contrast_correction : 9; // fixed point: 3.6 bits 398 uint32 _reserved2 : 5; 399 // (0x4c) OCLRC1 - overlay color correction 1 400 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 401 uint32 _reserved3 : 6; 402 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 403 uint32 _reserved4 : 5; 404 // (0x50) DCLRKV - destination color key value 405 uint32 color_key_blue : 8; 406 uint32 color_key_green : 8; 407 uint32 color_key_red : 8; 408 uint32 _reserved5 : 8; 409 // (0x54) DCLRKM - destination color key mask 410 uint32 color_key_mask_blue : 8; 411 uint32 color_key_mask_green : 8; 412 uint32 color_key_mask_red : 8; 413 uint32 _reserved6 : 7; 414 uint32 color_key_enabled : 1; 415 // (0x58) SCHRKVH - source chroma key high value 416 uint32 source_chroma_key_high_red : 8; 417 uint32 source_chroma_key_high_blue : 8; 418 uint32 source_chroma_key_high_green : 8; 419 uint32 _reserved7 : 8; 420 // (0x5c) SCHRKVL - source chroma key low value 421 uint32 source_chroma_key_low_red : 8; 422 uint32 source_chroma_key_low_blue : 8; 423 uint32 source_chroma_key_low_green : 8; 424 uint32 _reserved8 : 8; 425 // (0x60) SCHRKEN - source chroma key enable 426 uint32 _reserved9 : 24; 427 uint32 source_chroma_key_red_enabled : 1; 428 uint32 source_chroma_key_blue_enabled : 1; 429 uint32 source_chroma_key_green_enabled : 1; 430 uint32 _reserved10 : 5; 431 // (0x64) OCONFIG - overlay configuration 432 uint32 _reserved11 : 3; 433 uint32 color_control_output_mode : 1; 434 uint32 yuv_to_rgb_bypass : 1; 435 uint32 _reserved12 : 11; 436 uint32 gamma2_enabled : 1; 437 uint32 _reserved13 : 1; 438 uint32 select_pipe : 1; 439 uint32 slot_time : 8; 440 uint32 _reserved14 : 5; 441 // (0x68) OCOMD - overlay command 442 uint32 overlay_enabled : 1; 443 uint32 active_field : 1; 444 uint32 active_buffer : 2; 445 uint32 test_mode : 1; 446 uint32 buffer_field_mode : 1; 447 uint32 _reserved15 : 1; 448 uint32 tv_flip_field_enabled : 1; 449 uint32 _reserved16 : 1; 450 uint32 tv_flip_field_parity : 1; 451 uint32 source_format : 4; 452 uint32 ycbcr422_order : 2; 453 uint32 _reserved18 : 1; 454 uint32 mirroring_mode : 2; 455 uint32 _reserved19 : 13; 456 457 uint32 _reserved20; 458 459 uint32 start_0y; 460 uint32 start_1y; 461 uint32 start_0u; 462 uint32 start_0v; 463 uint32 start_1u; 464 uint32 start_1v; 465 uint32 _reserved21[6]; 466 #if 0 467 // (0x70) AWINPOS - alpha blend window position 468 uint32 awinpos; 469 // (0x74) AWINSZ - alpha blend window size 470 uint32 awinsz; 471 472 uint32 _reserved21[10]; 473 #endif 474 475 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 476 // the next two registers switch the usual Y/RGB vs. UV order) 477 uint16 horizontal_scale_uv; 478 uint16 horizontal_scale_rgb; 479 // (0xa4) UVSCALEV - vertical downscale 480 uint16 vertical_scale_uv; 481 uint16 vertical_scale_rgb; 482 483 uint32 _reserved22[86]; 484 485 // (0x200) polyphase filter coefficients 486 uint16 vertical_coefficients_rgb[128]; 487 uint16 horizontal_coefficients_rgb[128]; 488 489 uint32 _reserved23[64]; 490 491 // (0x500) 492 uint16 vertical_coefficients_uv[128]; 493 uint16 horizontal_coefficients_uv[128]; 494 }; 495 496 497 struct hardware_status { 498 uint32 interrupt_status_register; 499 uint32 _reserved0[3]; 500 void* primary_ring_head_storage; 501 uint32 _reserved1[3]; 502 void* secondary_ring_0_head_storage; 503 void* secondary_ring_1_head_storage; 504 uint32 _reserved2[2]; 505 void* binning_head_storage; 506 uint32 _reserved3[3]; 507 uint32 store[1008]; 508 }; 509 510 #endif /* RADEON_HD_H */ 511