1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm. DCE 0 18 #include "avivo_reg.h" // DCE 1 19 #include "r600_reg.h" // DCE 2 20 #include "r700_reg.h" // DCE 3 21 #include "evergreen_reg.h" // DCE 4 22 #include "ni_reg.h" // DCE 5 23 #include "si_reg.h" // DCE 6 24 #include "sea_reg.h" // DCE 8 25 #include "vol_reg.h" // DCE 10 26 #include "car_reg.h" // DCE 11 27 28 #include <Accelerant.h> 29 #include <Drivers.h> 30 #include <edid.h> 31 #include <PCI.h> 32 33 34 #define VENDOR_ID_ATI 0x1002 35 36 // Card chipset flags 37 #define CHIP_STD (1 << 0) // Standard chipset 38 #define CHIP_X2 (1 << 1) // Dual cpu 39 #define CHIP_IGP (1 << 2) // IGP chipset 40 #define CHIP_MOBILE (1 << 3) // Mobile chipset 41 #define CHIP_DISCREET (1 << 4) // Discreet chipset 42 #define CHIP_APU (1 << 5) // APU chipset 43 44 #define DEVICE_NAME "radeon_hd" 45 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 46 47 #define MAX_NAME_LENGTH 32 48 49 // Used to collect EDID from boot loader 50 #define EDID_BOOT_INFO "vesa_edid/v1" 51 #define MODES_BOOT_INFO "vesa_modes/v1" 52 53 #define RHD_POWER_ON 0 54 #define RHD_POWER_RESET 1 /* off temporarily */ 55 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 56 #define RHD_POWER_UNKNOWN 3 /* initial state */ 57 58 59 // Radeon Chipsets 60 // !! Must match chipset names below 61 enum radeon_chipset { 62 RADEON_R420 = 0, //r400, Radeon X700-X850 63 RADEON_R423, 64 RADEON_RV410, 65 RADEON_RS400, 66 RADEON_RS480, 67 RADEON_RS600, 68 RADEON_RS690, 69 RADEON_RS740, 70 RADEON_RV515, 71 RADEON_R520, //r500, DCE 1.0 72 RADEON_RV530, // DCE 1.0 73 RADEON_RV560, // DCE 1.0 74 RADEON_RV570, // DCE 1.0 75 RADEON_R580, // DCE 1.0 76 RADEON_R600, //r600, DCE 2.0 77 RADEON_RV610, // DCE 2.0 78 RADEON_RV630, // DCE 2.0 79 RADEON_RV670, // DCE 2.0 80 RADEON_RV620, // DCE 3.0 81 RADEON_RV635, // DCE 3.0 82 RADEON_RS780, // DCE 3.0 83 RADEON_RS880, // DCE 3.0 84 RADEON_RV770, //r700, DCE 3.1 85 RADEON_RV730, // DCE 3.2 86 RADEON_RV710, // DCE 3.2 87 RADEON_RV740, // DCE 3.2 88 RADEON_CEDAR, //Evergreen, DCE 4.0 89 RADEON_REDWOOD, // DCE 4.0 90 RADEON_JUNIPER, // DCE 4.0 91 RADEON_CYPRESS, // DCE 4.0 92 RADEON_HEMLOCK, // DCE 4.0? 93 RADEON_PALM, //Fusion APU (NI), DCE 4.1 94 RADEON_SUMO, // DCE 4.1 95 RADEON_SUMO2, // DCE 4.1 96 RADEON_CAICOS, //Nothern Islands, DCE 5.0 97 RADEON_TURKS, // DCE 5.0 98 RADEON_BARTS, // DCE 5.0 99 RADEON_CAYMAN, // DCE 5.0 100 RADEON_ANTILLES, // DCE 5.0? 101 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 102 RADEON_PITCAIRN, // DCE 6.0 103 RADEON_TAHITI, // DCE 6.0 104 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 105 RADEON_OLAND, // DCE 6.4 106 RADEON_HAINAN, // NO DCE, only compute 107 RADEON_KAVERI, //Sea Islands, DCE 8.1 108 RADEON_BONAIRE, // DCE 8.2 109 RADEON_KABINI, // DCE 8.3 110 RADEON_MULLINS, // DCE 8.3 111 RADEON_HAWAII, // DCE 8.5 112 RADEON_TOPAZ, //Volcanic Islands, NO DCE 113 RADEON_TONGA, // DCE 10.0 114 RADEON_FIJI, // DCE 10.1? 115 RADEON_CARRIZO, // DCE 11.0 116 RADEON_STONEY, // DCE 11.1? 117 RADEON_POLARIS11, //Artic Islands, DCE 12.1? 118 RADEON_POLARIS10, // DCE 12.0? 119 RADEON_POLARIS12, // DCE 12.2? 120 RADEON_VEGAM, // DCE 13.0? 121 RADEON_VEGA10, // DCE 13.0? 122 RADEON_VEGA12, // DCE 13.0? 123 RADEON_VEGA20, // DCE 13.0? 124 RADEON_RAVEN, // DCE 13? 125 }; 126 127 // !! Must match chipset families above 128 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 129 "R420", 130 "R423", 131 "RV410", 132 "RS400", 133 "RS480", 134 "RS600", 135 "RS690", 136 "RS740", 137 "RV515", 138 "R520", 139 "RV530", 140 "RV560", 141 "RV570", 142 "R580", 143 "R600", 144 "RV610", 145 "RV630", 146 "RV670", 147 "RV620", 148 "RV635", 149 "RS780", 150 "RS880", 151 "RV770", 152 "RV730", 153 "RV710", 154 "RV740", 155 "Cedar", 156 "Redwood", 157 "Juniper", 158 "Cypress", 159 "Hemlock", 160 "Palm", 161 "Sumo", 162 "Sumo2", 163 "Caicos", 164 "Turks", 165 "Barts", 166 "Cayman", 167 "Antilles", 168 "Cape Verde", 169 "Pitcairn", 170 "Tahiti", 171 "Aruba", 172 "Oland", 173 "Hainan", 174 "Kaveri", 175 "Bonaire", 176 "Kabini", 177 "Mullins", 178 "Hawaii", 179 "Topaz", 180 "Tonga", 181 "Fiji", 182 "Carrizo", 183 "Stoney Ridge", 184 "Polaris 11", 185 "Polaris 10", 186 "Polaris 12", 187 "Vega Mobile", 188 "Vega 10", 189 "Vega 12", 190 "Vega 20", 191 "Raven", 192 }; 193 194 195 struct ring_buffer { 196 struct lock lock; 197 uint32 register_base; 198 uint32 offset; 199 uint32 size; 200 uint32 position; 201 uint32 space_left; 202 uint8* base; 203 }; 204 205 206 struct overlay_registers; 207 208 209 struct radeon_shared_info { 210 uint32 deviceIndex; // accelerant index 211 uint32 pciID; // device pci id 212 uint32 pciRev; // device pci revision 213 area_id mode_list_area; // area containing display mode list 214 uint32 mode_count; 215 216 bool has_rom; // was rom mapped? 217 area_id rom_area; // area of mapped rom 218 uint32 rom_phys; // rom base location 219 uint32 rom_size; // rom size 220 uint8* rom; // cloned, memory mapped PCI ROM 221 222 display_mode current_mode; 223 uint32 bytes_per_row; 224 uint32 bits_per_pixel; 225 uint32 dpms_mode; 226 227 area_id registers_area; // area of memory mapped registers 228 uint8* status_page; 229 addr_t physical_status_page; 230 uint32 graphics_memory_size; 231 232 uint8* frame_buffer; // virtual memory mapped FB 233 area_id frame_buffer_area; // area of memory mapped FB 234 addr_t frame_buffer_phys; // card PCI BAR address of FB 235 uint32 frame_buffer_size; // FB size mapped 236 237 bool has_edid; 238 edid1_info edid_info; 239 240 struct lock accelerant_lock; 241 struct lock engine_lock; 242 243 ring_buffer primary_ring_buffer; 244 245 int32 overlay_channel_used; 246 bool overlay_active; 247 uint32 overlay_token; 248 addr_t physical_overlay_registers; 249 uint32 overlay_offset; 250 251 bool hardware_cursor_enabled; 252 sem_id vblank_sem; 253 254 uint8* cursor_memory; 255 addr_t physical_cursor_memory; 256 uint32 cursor_buffer_offset; 257 uint32 cursor_format; 258 bool cursor_visible; 259 uint16 cursor_hot_x; 260 uint16 cursor_hot_y; 261 262 char deviceName[MAX_NAME_LENGTH]; 263 uint16 chipsetID; 264 char chipsetName[MAX_NAME_LENGTH]; 265 uint32 chipsetFlags; 266 uint8 dceMajor; 267 uint8 dceMinor; 268 269 uint16 color_data[3 * 256]; // colour lookup table 270 }; 271 272 //----------------- ioctl() interface ---------------- 273 274 // magic code for ioctls 275 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 276 277 // list ioctls 278 enum { 279 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 280 281 RADEON_GET_DEVICE_NAME, 282 RADEON_ALLOCATE_GRAPHICS_MEMORY, 283 RADEON_FREE_GRAPHICS_MEMORY 284 }; 285 286 // retrieve the area_id of the kernel/accelerant shared info 287 struct radeon_get_private_data { 288 uint32 magic; // magic number 289 area_id shared_info_area; 290 }; 291 292 // allocate graphics memory 293 struct radeon_allocate_graphics_memory { 294 uint32 magic; 295 uint32 size; 296 uint32 alignment; 297 uint32 flags; 298 uint32 buffer_base; 299 }; 300 301 // free graphics memory 302 struct radeon_free_graphics_memory { 303 uint32 magic; 304 uint32 buffer_base; 305 }; 306 307 // registers 308 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 309 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 310 #define CONFIG_MEMSIZE 0x5428 // r600> 311 312 // PCI bridge memory management 313 314 // overlay 315 316 #define RADEON_OVERLAY_UPDATE 0x30000 317 #define RADEON_OVERLAY_TEST 0x30004 318 #define RADEON_OVERLAY_STATUS 0x30008 319 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 320 #define RADEON_OVERLAY_GAMMA_5 0x30010 321 #define RADEON_OVERLAY_GAMMA_4 0x30014 322 #define RADEON_OVERLAY_GAMMA_3 0x30018 323 #define RADEON_OVERLAY_GAMMA_2 0x3001c 324 #define RADEON_OVERLAY_GAMMA_1 0x30020 325 #define RADEON_OVERLAY_GAMMA_0 0x30024 326 327 struct overlay_scale { 328 uint32 _reserved0 : 3; 329 uint32 horizontal_scale_fraction : 12; 330 uint32 _reserved1 : 1; 331 uint32 horizontal_downscale_factor : 3; 332 uint32 _reserved2 : 1; 333 uint32 vertical_scale_fraction : 12; 334 }; 335 336 #define OVERLAY_FORMAT_RGB15 0x2 337 #define OVERLAY_FORMAT_RGB16 0x3 338 #define OVERLAY_FORMAT_RGB32 0x1 339 #define OVERLAY_FORMAT_YCbCr422 0x8 340 #define OVERLAY_FORMAT_YCbCr411 0x9 341 #define OVERLAY_FORMAT_YCbCr420 0xc 342 343 #define OVERLAY_MIRROR_NORMAL 0x0 344 #define OVERLAY_MIRROR_HORIZONTAL 0x1 345 #define OVERLAY_MIRROR_VERTICAL 0x2 346 347 // The real overlay registers are written to using an update buffer 348 349 struct overlay_registers { 350 uint32 buffer_rgb0; 351 uint32 buffer_rgb1; 352 uint32 buffer_u0; 353 uint32 buffer_v0; 354 uint32 buffer_u1; 355 uint32 buffer_v1; 356 // (0x18) OSTRIDE - overlay stride 357 uint16 stride_rgb; 358 uint16 stride_uv; 359 // (0x1c) YRGB_VPH - Y/RGB vertical phase 360 uint16 vertical_phase0_rgb; 361 uint16 vertical_phase1_rgb; 362 // (0x20) UV_VPH - UV vertical phase 363 uint16 vertical_phase0_uv; 364 uint16 vertical_phase1_uv; 365 // (0x24) HORZ_PH - horizontal phase 366 uint16 horizontal_phase_rgb; 367 uint16 horizontal_phase_uv; 368 // (0x28) INIT_PHS - initial phase shift 369 uint32 initial_vertical_phase0_shift_rgb0 : 4; 370 uint32 initial_vertical_phase1_shift_rgb0 : 4; 371 uint32 initial_horizontal_phase_shift_rgb0 : 4; 372 uint32 initial_vertical_phase0_shift_uv : 4; 373 uint32 initial_vertical_phase1_shift_uv : 4; 374 uint32 initial_horizontal_phase_shift_uv : 4; 375 uint32 _reserved0 : 8; 376 // (0x2c) DWINPOS - destination window position 377 uint16 window_left; 378 uint16 window_top; 379 // (0x30) DWINSZ - destination window size 380 uint16 window_width; 381 uint16 window_height; 382 // (0x34) SWIDTH - source width 383 uint16 source_width_rgb; 384 uint16 source_width_uv; 385 // (0x38) SWITDHSW - source width in 8 byte steps 386 uint16 source_bytes_per_row_rgb; 387 uint16 source_bytes_per_row_uv; 388 uint16 source_height_rgb; 389 uint16 source_height_uv; 390 overlay_scale scale_rgb; 391 overlay_scale scale_uv; 392 // (0x48) OCLRC0 - overlay color correction 0 393 uint32 brightness_correction : 8; // signed, -128 to 127 394 uint32 _reserved1 : 10; 395 uint32 contrast_correction : 9; // fixed point: 3.6 bits 396 uint32 _reserved2 : 5; 397 // (0x4c) OCLRC1 - overlay color correction 1 398 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 399 uint32 _reserved3 : 6; 400 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 401 uint32 _reserved4 : 5; 402 // (0x50) DCLRKV - destination color key value 403 uint32 color_key_blue : 8; 404 uint32 color_key_green : 8; 405 uint32 color_key_red : 8; 406 uint32 _reserved5 : 8; 407 // (0x54) DCLRKM - destination color key mask 408 uint32 color_key_mask_blue : 8; 409 uint32 color_key_mask_green : 8; 410 uint32 color_key_mask_red : 8; 411 uint32 _reserved6 : 7; 412 uint32 color_key_enabled : 1; 413 // (0x58) SCHRKVH - source chroma key high value 414 uint32 source_chroma_key_high_red : 8; 415 uint32 source_chroma_key_high_blue : 8; 416 uint32 source_chroma_key_high_green : 8; 417 uint32 _reserved7 : 8; 418 // (0x5c) SCHRKVL - source chroma key low value 419 uint32 source_chroma_key_low_red : 8; 420 uint32 source_chroma_key_low_blue : 8; 421 uint32 source_chroma_key_low_green : 8; 422 uint32 _reserved8 : 8; 423 // (0x60) SCHRKEN - source chroma key enable 424 uint32 _reserved9 : 24; 425 uint32 source_chroma_key_red_enabled : 1; 426 uint32 source_chroma_key_blue_enabled : 1; 427 uint32 source_chroma_key_green_enabled : 1; 428 uint32 _reserved10 : 5; 429 // (0x64) OCONFIG - overlay configuration 430 uint32 _reserved11 : 3; 431 uint32 color_control_output_mode : 1; 432 uint32 yuv_to_rgb_bypass : 1; 433 uint32 _reserved12 : 11; 434 uint32 gamma2_enabled : 1; 435 uint32 _reserved13 : 1; 436 uint32 select_pipe : 1; 437 uint32 slot_time : 8; 438 uint32 _reserved14 : 5; 439 // (0x68) OCOMD - overlay command 440 uint32 overlay_enabled : 1; 441 uint32 active_field : 1; 442 uint32 active_buffer : 2; 443 uint32 test_mode : 1; 444 uint32 buffer_field_mode : 1; 445 uint32 _reserved15 : 1; 446 uint32 tv_flip_field_enabled : 1; 447 uint32 _reserved16 : 1; 448 uint32 tv_flip_field_parity : 1; 449 uint32 source_format : 4; 450 uint32 ycbcr422_order : 2; 451 uint32 _reserved18 : 1; 452 uint32 mirroring_mode : 2; 453 uint32 _reserved19 : 13; 454 455 uint32 _reserved20; 456 457 uint32 start_0y; 458 uint32 start_1y; 459 uint32 start_0u; 460 uint32 start_0v; 461 uint32 start_1u; 462 uint32 start_1v; 463 uint32 _reserved21[6]; 464 #if 0 465 // (0x70) AWINPOS - alpha blend window position 466 uint32 awinpos; 467 // (0x74) AWINSZ - alpha blend window size 468 uint32 awinsz; 469 470 uint32 _reserved21[10]; 471 #endif 472 473 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 474 // the next two registers switch the usual Y/RGB vs. UV order) 475 uint16 horizontal_scale_uv; 476 uint16 horizontal_scale_rgb; 477 // (0xa4) UVSCALEV - vertical downscale 478 uint16 vertical_scale_uv; 479 uint16 vertical_scale_rgb; 480 481 uint32 _reserved22[86]; 482 483 // (0x200) polyphase filter coefficients 484 uint16 vertical_coefficients_rgb[128]; 485 uint16 horizontal_coefficients_rgb[128]; 486 487 uint32 _reserved23[64]; 488 489 // (0x500) 490 uint16 vertical_coefficients_uv[128]; 491 uint16 horizontal_coefficients_uv[128]; 492 }; 493 494 495 struct hardware_status { 496 uint32 interrupt_status_register; 497 uint32 _reserved0[3]; 498 void* primary_ring_head_storage; 499 uint32 _reserved1[3]; 500 void* secondary_ring_0_head_storage; 501 void* secondary_ring_1_head_storage; 502 uint32 _reserved2[2]; 503 void* binning_head_storage; 504 uint32 _reserved3[3]; 505 uint32 store[1008]; 506 }; 507 508 #endif /* RADEON_HD_H */ 509