1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 #include "avivo.h" 18 #include "r500_reg.h" 19 #include "r600_reg.h" 20 #include "r700_reg.h" 21 #include "evergreen_reg.h" 22 #include "evergreend.h" 23 24 #include <Accelerant.h> 25 #include <Drivers.h> 26 #include <edid.h> 27 #include <PCI.h> 28 29 30 #define VENDOR_ID_ATI 0x1002 31 32 // Card chipset flags 33 #define CHIP_STD (1 << 0) // Standard chipset 34 #define CHIP_IGP (1 << 1) // IGP chipset 35 #define CHIP_MOBILE (1 << 2) // Mobile chipset 36 #define CHIP_DISCREET (1 << 3) // Discreet chipset 37 #define CHIP_APU (1 << 4) // APU chipset 38 39 #define DEVICE_NAME "radeon_hd" 40 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 41 42 // Used to collect EDID from boot loader 43 #define EDID_BOOT_INFO "vesa_edid/v1" 44 #define MODES_BOOT_INFO "vesa_modes/v1" 45 46 #define RHD_POWER_ON 0 47 #define RHD_POWER_RESET 1 /* off temporarily */ 48 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 49 #define RHD_POWER_UNKNOWN 3 /* initial state */ 50 51 52 // Radeon Chipsets 53 enum radeon_chipset { 54 RADEON_R420 = 0, //r400, Radeon X700-X850 55 RADEON_RV515, 56 RADEON_R520, //r500, Radeon X1300-X1950 57 RADEON_RV530, 58 RADEON_RV560, 59 RADEON_RV570, 60 RADEON_R580, 61 RADEON_R600, //r600, Radeon HD 2000, 3000 62 RADEON_RV610, 63 RADEON_RV630, 64 RADEON_RV670, 65 RADEON_RV620, 66 RADEON_RV635, 67 RADEON_RS780, 68 RADEON_RS880, 69 RADEON_RV770, //r700, Radeon HD 4000 70 RADEON_RV730, 71 RADEON_RV710, 72 RADEON_RV740, 73 RADEON_CEDAR, //Evergreen, Radeon HD 5000 74 RADEON_REDWOOD, 75 RADEON_JUNIPER, 76 RADEON_CYPRESS, 77 RADEON_HEMLOCK, 78 RADEON_PALM, //Fusion APU (NI), Radeon HD 6000 79 RADEON_SUMO, 80 RADEON_SUMO2, 81 RADEON_CAICOS, //Nothern Islands, Radeon HD 6000 82 RADEON_TURKS, 83 RADEON_BARTS, 84 RADEON_CAYMAN, 85 RADEON_ANTILLES, 86 RADEON_LOMBOK, //Southern Islands, Radeon HD 7000 87 RADEON_THAMES, 88 RADEON_TAHITI, 89 RADEON_NEWZEALAND 90 }; 91 92 93 struct ring_buffer { 94 struct lock lock; 95 uint32 register_base; 96 uint32 offset; 97 uint32 size; 98 uint32 position; 99 uint32 space_left; 100 uint8* base; 101 }; 102 103 104 struct overlay_registers; 105 106 107 struct radeon_shared_info { 108 uint32 deviceIndex; // accelerant index 109 uint32 pciID; // device pciid 110 area_id mode_list_area; // area containing display mode list 111 uint32 mode_count; 112 113 bool has_rom; // was rom mapped? 114 area_id rom_area; // area of mapped rom 115 uint32 rom_phys; // rom base location 116 uint32 rom_size; // rom size 117 uint8* rom; // cloned, memory mapped PCI ROM 118 119 display_mode current_mode; 120 uint32 bytes_per_row; 121 uint32 bits_per_pixel; 122 uint32 dpms_mode; 123 124 area_id registers_area; // area of memory mapped registers 125 uint8* status_page; 126 addr_t physical_status_page; 127 uint32 graphics_memory_size; 128 129 uint8* frame_buffer; // virtual memory mapped FB 130 area_id frame_buffer_area; // area of memory mapped FB 131 addr_t frame_buffer_phys; // card PCI BAR address of FB 132 uint32 frame_buffer_size; // FB size mapped 133 134 bool has_edid; 135 edid1_info edid_info; 136 137 struct lock accelerant_lock; 138 struct lock engine_lock; 139 140 ring_buffer primary_ring_buffer; 141 142 int32 overlay_channel_used; 143 bool overlay_active; 144 uint32 overlay_token; 145 addr_t physical_overlay_registers; 146 uint32 overlay_offset; 147 148 bool hardware_cursor_enabled; 149 sem_id vblank_sem; 150 151 uint8* cursor_memory; 152 addr_t physical_cursor_memory; 153 uint32 cursor_buffer_offset; 154 uint32 cursor_format; 155 bool cursor_visible; 156 uint16 cursor_hot_x; 157 uint16 cursor_hot_y; 158 159 char deviceName[32]; 160 uint16 chipsetID; 161 char chipsetName[16]; 162 uint32 chipsetFlags; 163 uint8 dceMajor; 164 uint8 dceMinor; 165 }; 166 167 //----------------- ioctl() interface ---------------- 168 169 // magic code for ioctls 170 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 171 172 // list ioctls 173 enum { 174 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 175 176 RADEON_GET_DEVICE_NAME, 177 RADEON_ALLOCATE_GRAPHICS_MEMORY, 178 RADEON_FREE_GRAPHICS_MEMORY 179 }; 180 181 // retrieve the area_id of the kernel/accelerant shared info 182 struct radeon_get_private_data { 183 uint32 magic; // magic number 184 area_id shared_info_area; 185 }; 186 187 // allocate graphics memory 188 struct radeon_allocate_graphics_memory { 189 uint32 magic; 190 uint32 size; 191 uint32 alignment; 192 uint32 flags; 193 uint32 buffer_base; 194 }; 195 196 // free graphics memory 197 struct radeon_free_graphics_memory { 198 uint32 magic; 199 uint32 buffer_base; 200 }; 201 202 // registers 203 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 204 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 205 #define CONFIG_MEMSIZE 0x5428 // r600> 206 207 // PCI bridge memory management 208 209 // overlay 210 211 #define RADEON_OVERLAY_UPDATE 0x30000 212 #define RADEON_OVERLAY_TEST 0x30004 213 #define RADEON_OVERLAY_STATUS 0x30008 214 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 215 #define RADEON_OVERLAY_GAMMA_5 0x30010 216 #define RADEON_OVERLAY_GAMMA_4 0x30014 217 #define RADEON_OVERLAY_GAMMA_3 0x30018 218 #define RADEON_OVERLAY_GAMMA_2 0x3001c 219 #define RADEON_OVERLAY_GAMMA_1 0x30020 220 #define RADEON_OVERLAY_GAMMA_0 0x30024 221 222 struct overlay_scale { 223 uint32 _reserved0 : 3; 224 uint32 horizontal_scale_fraction : 12; 225 uint32 _reserved1 : 1; 226 uint32 horizontal_downscale_factor : 3; 227 uint32 _reserved2 : 1; 228 uint32 vertical_scale_fraction : 12; 229 }; 230 231 #define OVERLAY_FORMAT_RGB15 0x2 232 #define OVERLAY_FORMAT_RGB16 0x3 233 #define OVERLAY_FORMAT_RGB32 0x1 234 #define OVERLAY_FORMAT_YCbCr422 0x8 235 #define OVERLAY_FORMAT_YCbCr411 0x9 236 #define OVERLAY_FORMAT_YCbCr420 0xc 237 238 #define OVERLAY_MIRROR_NORMAL 0x0 239 #define OVERLAY_MIRROR_HORIZONTAL 0x1 240 #define OVERLAY_MIRROR_VERTICAL 0x2 241 242 // The real overlay registers are written to using an update buffer 243 244 struct overlay_registers { 245 uint32 buffer_rgb0; 246 uint32 buffer_rgb1; 247 uint32 buffer_u0; 248 uint32 buffer_v0; 249 uint32 buffer_u1; 250 uint32 buffer_v1; 251 // (0x18) OSTRIDE - overlay stride 252 uint16 stride_rgb; 253 uint16 stride_uv; 254 // (0x1c) YRGB_VPH - Y/RGB vertical phase 255 uint16 vertical_phase0_rgb; 256 uint16 vertical_phase1_rgb; 257 // (0x20) UV_VPH - UV vertical phase 258 uint16 vertical_phase0_uv; 259 uint16 vertical_phase1_uv; 260 // (0x24) HORZ_PH - horizontal phase 261 uint16 horizontal_phase_rgb; 262 uint16 horizontal_phase_uv; 263 // (0x28) INIT_PHS - initial phase shift 264 uint32 initial_vertical_phase0_shift_rgb0 : 4; 265 uint32 initial_vertical_phase1_shift_rgb0 : 4; 266 uint32 initial_horizontal_phase_shift_rgb0 : 4; 267 uint32 initial_vertical_phase0_shift_uv : 4; 268 uint32 initial_vertical_phase1_shift_uv : 4; 269 uint32 initial_horizontal_phase_shift_uv : 4; 270 uint32 _reserved0 : 8; 271 // (0x2c) DWINPOS - destination window position 272 uint16 window_left; 273 uint16 window_top; 274 // (0x30) DWINSZ - destination window size 275 uint16 window_width; 276 uint16 window_height; 277 // (0x34) SWIDTH - source width 278 uint16 source_width_rgb; 279 uint16 source_width_uv; 280 // (0x38) SWITDHSW - source width in 8 byte steps 281 uint16 source_bytes_per_row_rgb; 282 uint16 source_bytes_per_row_uv; 283 uint16 source_height_rgb; 284 uint16 source_height_uv; 285 overlay_scale scale_rgb; 286 overlay_scale scale_uv; 287 // (0x48) OCLRC0 - overlay color correction 0 288 uint32 brightness_correction : 8; // signed, -128 to 127 289 uint32 _reserved1 : 10; 290 uint32 contrast_correction : 9; // fixed point: 3.6 bits 291 uint32 _reserved2 : 5; 292 // (0x4c) OCLRC1 - overlay color correction 1 293 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 294 uint32 _reserved3 : 6; 295 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 296 uint32 _reserved4 : 5; 297 // (0x50) DCLRKV - destination color key value 298 uint32 color_key_blue : 8; 299 uint32 color_key_green : 8; 300 uint32 color_key_red : 8; 301 uint32 _reserved5 : 8; 302 // (0x54) DCLRKM - destination color key mask 303 uint32 color_key_mask_blue : 8; 304 uint32 color_key_mask_green : 8; 305 uint32 color_key_mask_red : 8; 306 uint32 _reserved6 : 7; 307 uint32 color_key_enabled : 1; 308 // (0x58) SCHRKVH - source chroma key high value 309 uint32 source_chroma_key_high_red : 8; 310 uint32 source_chroma_key_high_blue : 8; 311 uint32 source_chroma_key_high_green : 8; 312 uint32 _reserved7 : 8; 313 // (0x5c) SCHRKVL - source chroma key low value 314 uint32 source_chroma_key_low_red : 8; 315 uint32 source_chroma_key_low_blue : 8; 316 uint32 source_chroma_key_low_green : 8; 317 uint32 _reserved8 : 8; 318 // (0x60) SCHRKEN - source chroma key enable 319 uint32 _reserved9 : 24; 320 uint32 source_chroma_key_red_enabled : 1; 321 uint32 source_chroma_key_blue_enabled : 1; 322 uint32 source_chroma_key_green_enabled : 1; 323 uint32 _reserved10 : 5; 324 // (0x64) OCONFIG - overlay configuration 325 uint32 _reserved11 : 3; 326 uint32 color_control_output_mode : 1; 327 uint32 yuv_to_rgb_bypass : 1; 328 uint32 _reserved12 : 11; 329 uint32 gamma2_enabled : 1; 330 uint32 _reserved13 : 1; 331 uint32 select_pipe : 1; 332 uint32 slot_time : 8; 333 uint32 _reserved14 : 5; 334 // (0x68) OCOMD - overlay command 335 uint32 overlay_enabled : 1; 336 uint32 active_field : 1; 337 uint32 active_buffer : 2; 338 uint32 test_mode : 1; 339 uint32 buffer_field_mode : 1; 340 uint32 _reserved15 : 1; 341 uint32 tv_flip_field_enabled : 1; 342 uint32 _reserved16 : 1; 343 uint32 tv_flip_field_parity : 1; 344 uint32 source_format : 4; 345 uint32 ycbcr422_order : 2; 346 uint32 _reserved18 : 1; 347 uint32 mirroring_mode : 2; 348 uint32 _reserved19 : 13; 349 350 uint32 _reserved20; 351 352 uint32 start_0y; 353 uint32 start_1y; 354 uint32 start_0u; 355 uint32 start_0v; 356 uint32 start_1u; 357 uint32 start_1v; 358 uint32 _reserved21[6]; 359 #if 0 360 // (0x70) AWINPOS - alpha blend window position 361 uint32 awinpos; 362 // (0x74) AWINSZ - alpha blend window size 363 uint32 awinsz; 364 365 uint32 _reserved21[10]; 366 #endif 367 368 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 369 // the next two registers switch the usual Y/RGB vs. UV order) 370 uint16 horizontal_scale_uv; 371 uint16 horizontal_scale_rgb; 372 // (0xa4) UVSCALEV - vertical downscale 373 uint16 vertical_scale_uv; 374 uint16 vertical_scale_rgb; 375 376 uint32 _reserved22[86]; 377 378 // (0x200) polyphase filter coefficients 379 uint16 vertical_coefficients_rgb[128]; 380 uint16 horizontal_coefficients_rgb[128]; 381 382 uint32 _reserved23[64]; 383 384 // (0x500) 385 uint16 vertical_coefficients_uv[128]; 386 uint16 horizontal_coefficients_uv[128]; 387 }; 388 389 390 struct hardware_status { 391 uint32 interrupt_status_register; 392 uint32 _reserved0[3]; 393 void* primary_ring_head_storage; 394 uint32 _reserved1[3]; 395 void* secondary_ring_0_head_storage; 396 void* secondary_ring_1_head_storage; 397 uint32 _reserved2[2]; 398 void* binning_head_storage; 399 uint32 _reserved3[3]; 400 uint32 store[1008]; 401 }; 402 403 #endif /* RADEON_HD_H */ 404