1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck IV, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_H 10 #define RADEON_HD_H 11 12 13 #include "lock.h" 14 15 #include "radeon_reg.h" 16 17 //#include "r500_reg.h" // Not used atm 18 #include "avivo_reg.h" 19 #include "r600_reg.h" 20 #include "r700_reg.h" 21 #include "evergreen_reg.h" 22 #include "si_reg.h" 23 #include "ni_reg.h" 24 25 #include <Accelerant.h> 26 #include <Drivers.h> 27 #include <edid.h> 28 #include <PCI.h> 29 30 31 #define VENDOR_ID_ATI 0x1002 32 33 // Card chipset flags 34 #define CHIP_STD (1 << 0) // Standard chipset 35 #define CHIP_X2 (1 << 1) // Dual cpu 36 #define CHIP_IGP (1 << 2) // IGP chipset 37 #define CHIP_MOBILE (1 << 3) // Mobile chipset 38 #define CHIP_DISCREET (1 << 4) // Discreet chipset 39 #define CHIP_APU (1 << 5) // APU chipset 40 41 #define DEVICE_NAME "radeon_hd" 42 #define RADEON_ACCELERANT_NAME "radeon_hd.accelerant" 43 44 #define MAX_NAME_LENGTH 32 45 46 // Used to collect EDID from boot loader 47 #define EDID_BOOT_INFO "vesa_edid/v1" 48 #define MODES_BOOT_INFO "vesa_modes/v1" 49 50 #define RHD_POWER_ON 0 51 #define RHD_POWER_RESET 1 /* off temporarily */ 52 #define RHD_POWER_SHUTDOWN 2 /* long term shutdown */ 53 #define RHD_POWER_UNKNOWN 3 /* initial state */ 54 55 56 // Radeon Chipsets 57 // !! Must match chipset names below 58 enum radeon_chipset { 59 RADEON_R420 = 0, //r400, Radeon X700-X850 60 RADEON_R423, 61 RADEON_RV410, 62 RADEON_RS400, 63 RADEON_RS480, 64 RADEON_RS600, 65 RADEON_RS690, 66 RADEON_RS740, 67 RADEON_RV515, 68 RADEON_R520, //r500, DCE 1.0 69 RADEON_RV530, // DCE 1.0 70 RADEON_RV560, // DCE 1.0 71 RADEON_RV570, // DCE 1.0 72 RADEON_R580, // DCE 1.0 73 RADEON_R600, //r600, DCE 2.0 74 RADEON_RV610, // DCE 2.0 75 RADEON_RV630, // DCE 2.0 76 RADEON_RV670, // DCE 2.0 77 RADEON_RV620, // DCE 3.0 78 RADEON_RV635, // DCE 3.0 79 RADEON_RS780, // DCE 3.0 80 RADEON_RS880, // DCE 3.0 81 RADEON_RV770, //r700, DCE 3.1 82 RADEON_RV730, // DCE 3.2 83 RADEON_RV710, // DCE 3.2 84 RADEON_RV740, // DCE 3.2 85 RADEON_CEDAR, //Evergreen, DCE 4.0 86 RADEON_REDWOOD, // DCE 4.0 87 RADEON_JUNIPER, // DCE 4.0 88 RADEON_CYPRESS, // DCE 4.0 89 RADEON_HEMLOCK, // DCE 4.0? 90 RADEON_PALM, //Fusion APU (NI), DCE 4.1 91 RADEON_SUMO, // DCE 4.1 92 RADEON_SUMO2, // DCE 4.1 93 RADEON_CAICOS, //Nothern Islands, DCE 5.0 94 RADEON_TURKS, // DCE 5.0 95 RADEON_BARTS, // DCE 5.0 96 RADEON_CAYMAN, // DCE 5.0 97 RADEON_ANTILLES, // DCE 5.0? 98 RADEON_CAPEVERDE, //Southern Islands, DCE 6.0 99 RADEON_PITCAIRN, // DCE 6.0 100 RADEON_TAHITI, // DCE 6.0 101 RADEON_ARUBA, // DCE 6.1 Trinity/Richland 102 RADEON_OLAND, // DCE 6.4 103 RADEON_HAINAN, // NO DCE, only compute 104 RADEON_KAVERI, //Sea Islands, DCE 8.1 105 RADEON_BONAIRE, // DCE 8.2 106 RADEON_KABINI, // DCE 8.3 107 }; 108 109 // !! Must match chipset families above 110 static const char radeon_chip_name[][MAX_NAME_LENGTH] = { 111 "R420", 112 "R423", 113 "RV410", 114 "RS400", 115 "RS480", 116 "RS600", 117 "RS690", 118 "RS740", 119 "RV515", 120 "R520", 121 "RV530", 122 "RV560", 123 "RV570", 124 "R580", 125 "R600", 126 "RV610", 127 "RV630", 128 "RV670", 129 "RV620", 130 "RV635", 131 "RS780", 132 "RS880", 133 "RV770", 134 "RV730", 135 "RV710", 136 "RV740", 137 "Cedar", 138 "Redwood", 139 "Juniper", 140 "Cypress", 141 "Hemlock", 142 "Palm", 143 "Sumo", 144 "Sumo2", 145 "Caicos", 146 "Turks", 147 "Barts", 148 "Cayman", 149 "Antilles", 150 "Cape Verde", 151 "Pitcairn", 152 "Tahiti", 153 "Aruba", 154 "Oland", 155 "Hainan", 156 "Kaveri", 157 "Bonaire", 158 "Kabini" 159 }; 160 161 162 struct ring_buffer { 163 struct lock lock; 164 uint32 register_base; 165 uint32 offset; 166 uint32 size; 167 uint32 position; 168 uint32 space_left; 169 uint8* base; 170 }; 171 172 173 struct overlay_registers; 174 175 176 struct radeon_shared_info { 177 uint32 deviceIndex; // accelerant index 178 uint32 pciID; // device pciid 179 area_id mode_list_area; // area containing display mode list 180 uint32 mode_count; 181 182 bool has_rom; // was rom mapped? 183 area_id rom_area; // area of mapped rom 184 uint32 rom_phys; // rom base location 185 uint32 rom_size; // rom size 186 uint8* rom; // cloned, memory mapped PCI ROM 187 188 display_mode current_mode; 189 uint32 bytes_per_row; 190 uint32 bits_per_pixel; 191 uint32 dpms_mode; 192 193 area_id registers_area; // area of memory mapped registers 194 uint8* status_page; 195 addr_t physical_status_page; 196 uint32 graphics_memory_size; 197 198 uint8* frame_buffer; // virtual memory mapped FB 199 area_id frame_buffer_area; // area of memory mapped FB 200 addr_t frame_buffer_phys; // card PCI BAR address of FB 201 uint32 frame_buffer_size; // FB size mapped 202 203 bool has_edid; 204 edid1_info edid_info; 205 206 struct lock accelerant_lock; 207 struct lock engine_lock; 208 209 ring_buffer primary_ring_buffer; 210 211 int32 overlay_channel_used; 212 bool overlay_active; 213 uint32 overlay_token; 214 addr_t physical_overlay_registers; 215 uint32 overlay_offset; 216 217 bool hardware_cursor_enabled; 218 sem_id vblank_sem; 219 220 uint8* cursor_memory; 221 addr_t physical_cursor_memory; 222 uint32 cursor_buffer_offset; 223 uint32 cursor_format; 224 bool cursor_visible; 225 uint16 cursor_hot_x; 226 uint16 cursor_hot_y; 227 228 char deviceName[MAX_NAME_LENGTH]; 229 uint16 chipsetID; 230 char chipsetName[MAX_NAME_LENGTH]; 231 uint32 chipsetFlags; 232 uint8 dceMajor; 233 uint8 dceMinor; 234 235 uint16 color_data[3 * 256]; // colour lookup table 236 }; 237 238 //----------------- ioctl() interface ---------------- 239 240 // magic code for ioctls 241 #define RADEON_PRIVATE_DATA_MAGIC 'rdhd' 242 243 // list ioctls 244 enum { 245 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 246 247 RADEON_GET_DEVICE_NAME, 248 RADEON_ALLOCATE_GRAPHICS_MEMORY, 249 RADEON_FREE_GRAPHICS_MEMORY 250 }; 251 252 // retrieve the area_id of the kernel/accelerant shared info 253 struct radeon_get_private_data { 254 uint32 magic; // magic number 255 area_id shared_info_area; 256 }; 257 258 // allocate graphics memory 259 struct radeon_allocate_graphics_memory { 260 uint32 magic; 261 uint32 size; 262 uint32 alignment; 263 uint32 flags; 264 uint32 buffer_base; 265 }; 266 267 // free graphics memory 268 struct radeon_free_graphics_memory { 269 uint32 magic; 270 uint32 buffer_base; 271 }; 272 273 // registers 274 #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> 275 #define OLD_CONFIG_APER_SIZE 0x0108 // <r600 276 #define CONFIG_MEMSIZE 0x5428 // r600> 277 278 // PCI bridge memory management 279 280 // overlay 281 282 #define RADEON_OVERLAY_UPDATE 0x30000 283 #define RADEON_OVERLAY_TEST 0x30004 284 #define RADEON_OVERLAY_STATUS 0x30008 285 #define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c 286 #define RADEON_OVERLAY_GAMMA_5 0x30010 287 #define RADEON_OVERLAY_GAMMA_4 0x30014 288 #define RADEON_OVERLAY_GAMMA_3 0x30018 289 #define RADEON_OVERLAY_GAMMA_2 0x3001c 290 #define RADEON_OVERLAY_GAMMA_1 0x30020 291 #define RADEON_OVERLAY_GAMMA_0 0x30024 292 293 struct overlay_scale { 294 uint32 _reserved0 : 3; 295 uint32 horizontal_scale_fraction : 12; 296 uint32 _reserved1 : 1; 297 uint32 horizontal_downscale_factor : 3; 298 uint32 _reserved2 : 1; 299 uint32 vertical_scale_fraction : 12; 300 }; 301 302 #define OVERLAY_FORMAT_RGB15 0x2 303 #define OVERLAY_FORMAT_RGB16 0x3 304 #define OVERLAY_FORMAT_RGB32 0x1 305 #define OVERLAY_FORMAT_YCbCr422 0x8 306 #define OVERLAY_FORMAT_YCbCr411 0x9 307 #define OVERLAY_FORMAT_YCbCr420 0xc 308 309 #define OVERLAY_MIRROR_NORMAL 0x0 310 #define OVERLAY_MIRROR_HORIZONTAL 0x1 311 #define OVERLAY_MIRROR_VERTICAL 0x2 312 313 // The real overlay registers are written to using an update buffer 314 315 struct overlay_registers { 316 uint32 buffer_rgb0; 317 uint32 buffer_rgb1; 318 uint32 buffer_u0; 319 uint32 buffer_v0; 320 uint32 buffer_u1; 321 uint32 buffer_v1; 322 // (0x18) OSTRIDE - overlay stride 323 uint16 stride_rgb; 324 uint16 stride_uv; 325 // (0x1c) YRGB_VPH - Y/RGB vertical phase 326 uint16 vertical_phase0_rgb; 327 uint16 vertical_phase1_rgb; 328 // (0x20) UV_VPH - UV vertical phase 329 uint16 vertical_phase0_uv; 330 uint16 vertical_phase1_uv; 331 // (0x24) HORZ_PH - horizontal phase 332 uint16 horizontal_phase_rgb; 333 uint16 horizontal_phase_uv; 334 // (0x28) INIT_PHS - initial phase shift 335 uint32 initial_vertical_phase0_shift_rgb0 : 4; 336 uint32 initial_vertical_phase1_shift_rgb0 : 4; 337 uint32 initial_horizontal_phase_shift_rgb0 : 4; 338 uint32 initial_vertical_phase0_shift_uv : 4; 339 uint32 initial_vertical_phase1_shift_uv : 4; 340 uint32 initial_horizontal_phase_shift_uv : 4; 341 uint32 _reserved0 : 8; 342 // (0x2c) DWINPOS - destination window position 343 uint16 window_left; 344 uint16 window_top; 345 // (0x30) DWINSZ - destination window size 346 uint16 window_width; 347 uint16 window_height; 348 // (0x34) SWIDTH - source width 349 uint16 source_width_rgb; 350 uint16 source_width_uv; 351 // (0x38) SWITDHSW - source width in 8 byte steps 352 uint16 source_bytes_per_row_rgb; 353 uint16 source_bytes_per_row_uv; 354 uint16 source_height_rgb; 355 uint16 source_height_uv; 356 overlay_scale scale_rgb; 357 overlay_scale scale_uv; 358 // (0x48) OCLRC0 - overlay color correction 0 359 uint32 brightness_correction : 8; // signed, -128 to 127 360 uint32 _reserved1 : 10; 361 uint32 contrast_correction : 9; // fixed point: 3.6 bits 362 uint32 _reserved2 : 5; 363 // (0x4c) OCLRC1 - overlay color correction 1 364 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 365 uint32 _reserved3 : 6; 366 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 367 uint32 _reserved4 : 5; 368 // (0x50) DCLRKV - destination color key value 369 uint32 color_key_blue : 8; 370 uint32 color_key_green : 8; 371 uint32 color_key_red : 8; 372 uint32 _reserved5 : 8; 373 // (0x54) DCLRKM - destination color key mask 374 uint32 color_key_mask_blue : 8; 375 uint32 color_key_mask_green : 8; 376 uint32 color_key_mask_red : 8; 377 uint32 _reserved6 : 7; 378 uint32 color_key_enabled : 1; 379 // (0x58) SCHRKVH - source chroma key high value 380 uint32 source_chroma_key_high_red : 8; 381 uint32 source_chroma_key_high_blue : 8; 382 uint32 source_chroma_key_high_green : 8; 383 uint32 _reserved7 : 8; 384 // (0x5c) SCHRKVL - source chroma key low value 385 uint32 source_chroma_key_low_red : 8; 386 uint32 source_chroma_key_low_blue : 8; 387 uint32 source_chroma_key_low_green : 8; 388 uint32 _reserved8 : 8; 389 // (0x60) SCHRKEN - source chroma key enable 390 uint32 _reserved9 : 24; 391 uint32 source_chroma_key_red_enabled : 1; 392 uint32 source_chroma_key_blue_enabled : 1; 393 uint32 source_chroma_key_green_enabled : 1; 394 uint32 _reserved10 : 5; 395 // (0x64) OCONFIG - overlay configuration 396 uint32 _reserved11 : 3; 397 uint32 color_control_output_mode : 1; 398 uint32 yuv_to_rgb_bypass : 1; 399 uint32 _reserved12 : 11; 400 uint32 gamma2_enabled : 1; 401 uint32 _reserved13 : 1; 402 uint32 select_pipe : 1; 403 uint32 slot_time : 8; 404 uint32 _reserved14 : 5; 405 // (0x68) OCOMD - overlay command 406 uint32 overlay_enabled : 1; 407 uint32 active_field : 1; 408 uint32 active_buffer : 2; 409 uint32 test_mode : 1; 410 uint32 buffer_field_mode : 1; 411 uint32 _reserved15 : 1; 412 uint32 tv_flip_field_enabled : 1; 413 uint32 _reserved16 : 1; 414 uint32 tv_flip_field_parity : 1; 415 uint32 source_format : 4; 416 uint32 ycbcr422_order : 2; 417 uint32 _reserved18 : 1; 418 uint32 mirroring_mode : 2; 419 uint32 _reserved19 : 13; 420 421 uint32 _reserved20; 422 423 uint32 start_0y; 424 uint32 start_1y; 425 uint32 start_0u; 426 uint32 start_0v; 427 uint32 start_1u; 428 uint32 start_1v; 429 uint32 _reserved21[6]; 430 #if 0 431 // (0x70) AWINPOS - alpha blend window position 432 uint32 awinpos; 433 // (0x74) AWINSZ - alpha blend window size 434 uint32 awinsz; 435 436 uint32 _reserved21[10]; 437 #endif 438 439 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 440 // the next two registers switch the usual Y/RGB vs. UV order) 441 uint16 horizontal_scale_uv; 442 uint16 horizontal_scale_rgb; 443 // (0xa4) UVSCALEV - vertical downscale 444 uint16 vertical_scale_uv; 445 uint16 vertical_scale_rgb; 446 447 uint32 _reserved22[86]; 448 449 // (0x200) polyphase filter coefficients 450 uint16 vertical_coefficients_rgb[128]; 451 uint16 horizontal_coefficients_rgb[128]; 452 453 uint32 _reserved23[64]; 454 455 // (0x500) 456 uint16 vertical_coefficients_uv[128]; 457 uint16 horizontal_coefficients_uv[128]; 458 }; 459 460 461 struct hardware_status { 462 uint32 interrupt_status_register; 463 uint32 _reserved0[3]; 464 void* primary_ring_head_storage; 465 uint32 _reserved1[3]; 466 void* secondary_ring_0_head_storage; 467 void* secondary_ring_1_head_storage; 468 uint32 _reserved2[2]; 469 void* binning_head_storage; 470 uint32 _reserved3[3]; 471 uint32 store[1008]; 472 }; 473 474 #endif /* RADEON_HD_H */ 475