1 /* 2 * RadeonHD R6xx, R7xx Register documentation 3 * 4 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. 5 * Copyright (C) 2008-2009 Matthias Hopf 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _R600_REG_H_ 26 #define _R600_REG_H_ 27 28 /* 29 * Register definitions 30 */ 31 32 #include "r600_reg_auto_r6xx.h" 33 #include "r600_reg_r6xx.h" 34 #include "r600_reg_r7xx.h" 35 36 37 /* SET_*_REG offsets + ends */ 38 enum { 39 SET_CONFIG_REG_offset = 0x00008000, 40 SET_CONFIG_REG_end = 0x0000ac00, 41 SET_CONTEXT_REG_offset = 0x00028000, 42 SET_CONTEXT_REG_end = 0x00029000, 43 SET_ALU_CONST_offset = 0x00030000, 44 SET_ALU_CONST_end = 0x00032000, 45 SET_RESOURCE_offset = 0x00038000, 46 SET_RESOURCE_end = 0x0003c000, 47 SET_SAMPLER_offset = 0x0003c000, 48 SET_SAMPLER_end = 0x0003cff0, 49 SET_CTL_CONST_offset = 0x0003cff0, 50 SET_CTL_CONST_end = 0x0003e200, 51 SET_LOOP_CONST_offset = 0x0003e200, 52 SET_LOOP_CONST_end = 0x0003e380, 53 SET_BOOL_CONST_offset = 0x0003e380, 54 SET_BOOL_CONST_end = 0x0003e38c 55 }; 56 57 /* packet3 IT_SURFACE_BASE_UPDATE bits */ 58 enum { 59 DEPTH_BASE = (1 << 0), 60 COLOR0_BASE = (1 << 1), 61 COLOR1_BASE = (1 << 2), 62 COLOR2_BASE = (1 << 3), 63 COLOR3_BASE = (1 << 4), 64 COLOR4_BASE = (1 << 5), 65 COLOR5_BASE = (1 << 6), 66 COLOR6_BASE = (1 << 7), 67 COLOR7_BASE = (1 << 8), 68 STRMOUT_BASE0 = (1 << 9), 69 STRMOUT_BASE1 = (1 << 10), 70 STRMOUT_BASE2 = (1 << 11), 71 STRMOUT_BASE3 = (1 << 12), 72 COHER_BASE0 = (1 << 13), 73 COHER_BASE1 = (1 << 14) 74 }; 75 76 /* packet3 IT_WAIT_REG_MEM operation encoding */ 77 enum { 78 WAIT_ALWAYS = (0<<0), 79 WAIT_LT = (1<<0), 80 WAIT_LE = (2<<0), 81 WAIT_EQ = (3<<0), 82 WAIT_NE = (4<<0), 83 WAIT_GE = (5<<0), 84 WAIT_GT = (6<<0), 85 86 WAIT_REG = (0<<4), 87 WAIT_MEM = (1<<4) 88 }; 89 90 /* Packet3 commands */ 91 enum { 92 IT_NOP = 0x10, 93 IT_INDIRECT_BUFFER_END = 0x17, 94 IT_SET_PREDICATION = 0x20, 95 IT_REG_RMW = 0x21, 96 IT_COND_EXEC = 0x22, 97 IT_PRED_EXEC = 0x23, 98 IT_START_3D_CMDBUF = 0x24, 99 IT_DRAW_INDEX_2 = 0x27, 100 IT_CONTEXT_CONTROL = 0x28, 101 IT_DRAW_INDEX_IMMD_BE = 0x29, 102 IT_INDEX_TYPE = 0x2A, 103 IT_DRAW_INDEX = 0x2B, 104 IT_DRAW_INDEX_AUTO = 0x2D, 105 IT_DRAW_INDEX_IMMD = 0x2E, 106 IT_NUM_INSTANCES = 0x2F, 107 IT_STRMOUT_BUFFER_UPDATE = 0x34, 108 IT_INDIRECT_BUFFER_MP = 0x38, 109 IT_MEM_SEMAPHORE = 0x39, 110 IT_MPEG_INDEX = 0x3A, 111 IT_WAIT_REG_MEM = 0x3C, 112 IT_MEM_WRITE = 0x3D, 113 IT_INDIRECT_BUFFER = 0x32, 114 IT_CP_INTERRUPT = 0x40, 115 IT_SURFACE_SYNC = 0x43, 116 IT_ME_INITIALIZE = 0x44, 117 IT_COND_WRITE = 0x45, 118 IT_EVENT_WRITE = 0x46, 119 IT_EVENT_WRITE_EOP = 0x47, 120 IT_ONE_REG_WRITE = 0x57, 121 IT_SET_CONFIG_REG = 0x68, 122 IT_SET_CONTEXT_REG = 0x69, 123 IT_SET_ALU_CONST = 0x6A, 124 IT_SET_BOOL_CONST = 0x6B, 125 IT_SET_LOOP_CONST = 0x6C, 126 IT_SET_RESOURCE = 0x6D, 127 IT_SET_SAMPLER = 0x6E, 128 IT_SET_CTL_CONST = 0x6F, 129 IT_SURFACE_BASE_UPDATE = 0x73 130 }; 131 132 #endif 133