12613175eSAlexander von Gluck IV /* 22613175eSAlexander von Gluck IV * RadeonHD R6xx, R7xx Register documentation 32613175eSAlexander von Gluck IV * 42613175eSAlexander von Gluck IV * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. 52613175eSAlexander von Gluck IV * Copyright (C) 2008-2009 Matthias Hopf 62613175eSAlexander von Gluck IV * 72613175eSAlexander von Gluck IV * Permission is hereby granted, free of charge, to any person obtaining a 82613175eSAlexander von Gluck IV * copy of this software and associated documentation files (the "Software"), 92613175eSAlexander von Gluck IV * to deal in the Software without restriction, including without limitation 102613175eSAlexander von Gluck IV * the rights to use, copy, modify, merge, publish, distribute, sublicense, 112613175eSAlexander von Gluck IV * and/or sell copies of the Software, and to permit persons to whom the 122613175eSAlexander von Gluck IV * Software is furnished to do so, subject to the following conditions: 132613175eSAlexander von Gluck IV * 142613175eSAlexander von Gluck IV * The above copyright notice and this permission notice shall be included 152613175eSAlexander von Gluck IV * in all copies or substantial portions of the Software. 162613175eSAlexander von Gluck IV * 172613175eSAlexander von Gluck IV * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 182613175eSAlexander von Gluck IV * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 192613175eSAlexander von Gluck IV * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 202613175eSAlexander von Gluck IV * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 212613175eSAlexander von Gluck IV * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 222613175eSAlexander von Gluck IV * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 232613175eSAlexander von Gluck IV */ 242613175eSAlexander von Gluck IV 252613175eSAlexander von Gluck IV #ifndef _R600_REG_H_ 262613175eSAlexander von Gluck IV #define _R600_REG_H_ 272613175eSAlexander von Gluck IV 282613175eSAlexander von Gluck IV /* 292613175eSAlexander von Gluck IV * Register definitions 302613175eSAlexander von Gluck IV */ 312613175eSAlexander von Gluck IV 322613175eSAlexander von Gluck IV #include "r600_reg_auto_r6xx.h" 332613175eSAlexander von Gluck IV #include "r600_reg_r6xx.h" 342613175eSAlexander von Gluck IV #include "r600_reg_r7xx.h" 352613175eSAlexander von Gluck IV 362613175eSAlexander von Gluck IV 37*1d5cfc64SAlexander von Gluck IV /* From Linux DRM Radeon driver for AtomBIOS */ 38*1d5cfc64SAlexander von Gluck IV #define RADEON_SEPROM_CNTL1 0x01c0 39*1d5cfc64SAlexander von Gluck IV #define RADEON_SCK_PRESCALE_SHIFT 24 40*1d5cfc64SAlexander von Gluck IV #define RADEON_SCK_PRESCALE_MASK (0xff << 24) 41*1d5cfc64SAlexander von Gluck IV 42*1d5cfc64SAlexander von Gluck IV #define RADEON_VIPH_CONTROL 0x0c40 43*1d5cfc64SAlexander von Gluck IV #define RADEON_VIPH_EN (1 << 21) 44*1d5cfc64SAlexander von Gluck IV 45*1d5cfc64SAlexander von Gluck IV #define RADEON_GPIOPAD_MASK 0x0198 46*1d5cfc64SAlexander von Gluck IV #define RADEON_GPIOPAD_A 0x019c 47*1d5cfc64SAlexander von Gluck IV #define RADEON_GPIOPAD_EN 0x01a0 48*1d5cfc64SAlexander von Gluck IV #define RADEON_GPIOPAD_Y 0x01a4 49*1d5cfc64SAlexander von Gluck IV #define RADEON_MDGPIO_MASK 0x01a8 50*1d5cfc64SAlexander von Gluck IV #define RADEON_MDGPIO_A 0x01ac 51*1d5cfc64SAlexander von Gluck IV #define RADEON_MDGPIO_EN 0x01b0 52*1d5cfc64SAlexander von Gluck IV #define RADEON_MDGPIO_Y 0x01b4 53*1d5cfc64SAlexander von Gluck IV 54*1d5cfc64SAlexander von Gluck IV #define RV370_BUS_CNTL 0x004c 55*1d5cfc64SAlexander von Gluck IV 56*1d5cfc64SAlexander von Gluck IV #define R600_CG_SPLL_FUNC_CNTL 0x600 57*1d5cfc64SAlexander von Gluck IV #define R600_CG_SPLL_STATUS 0x60c 5852aeea24SAlexander von Gluck IV #define R600_ROM_CNTL 0x1600 5952aeea24SAlexander von Gluck IV #define R600_BUS_CNTL 0x5420 60*1d5cfc64SAlexander von Gluck IV 6152aeea24SAlexander von Gluck IV #define R600_BIOS_ROM_DIS (1 << 1) 6252aeea24SAlexander von Gluck IV #define R600_SCK_OVERWRITE (1 << 1) 63*1d5cfc64SAlexander von Gluck IV #define R600_SPLL_CHG_STATUS (1 << 1) 64*1d5cfc64SAlexander von Gluck IV #define R600_SPLL_BYPASS_EN (1 << 3) 6552aeea24SAlexander von Gluck IV #define DVGA_CONTROL_MODE_ENABLE (1 << 0) 6652aeea24SAlexander von Gluck IV #define DVGA_CONTROL_TIMING_SELECT (1 << 8) 6752aeea24SAlexander von Gluck IV #define VGA_VSTATUS_CNTL_MASK (3 << 16) 6852aeea24SAlexander von Gluck IV 69*1d5cfc64SAlexander von Gluck IV 702613175eSAlexander von Gluck IV /* SET_*_REG offsets + ends */ 712613175eSAlexander von Gluck IV enum { 722613175eSAlexander von Gluck IV SET_CONFIG_REG_offset = 0x00008000, 732613175eSAlexander von Gluck IV SET_CONFIG_REG_end = 0x0000ac00, 742613175eSAlexander von Gluck IV SET_CONTEXT_REG_offset = 0x00028000, 752613175eSAlexander von Gluck IV SET_CONTEXT_REG_end = 0x00029000, 762613175eSAlexander von Gluck IV SET_ALU_CONST_offset = 0x00030000, 772613175eSAlexander von Gluck IV SET_ALU_CONST_end = 0x00032000, 782613175eSAlexander von Gluck IV SET_RESOURCE_offset = 0x00038000, 792613175eSAlexander von Gluck IV SET_RESOURCE_end = 0x0003c000, 802613175eSAlexander von Gluck IV SET_SAMPLER_offset = 0x0003c000, 812613175eSAlexander von Gluck IV SET_SAMPLER_end = 0x0003cff0, 822613175eSAlexander von Gluck IV SET_CTL_CONST_offset = 0x0003cff0, 832613175eSAlexander von Gluck IV SET_CTL_CONST_end = 0x0003e200, 842613175eSAlexander von Gluck IV SET_LOOP_CONST_offset = 0x0003e200, 852613175eSAlexander von Gluck IV SET_LOOP_CONST_end = 0x0003e380, 862613175eSAlexander von Gluck IV SET_BOOL_CONST_offset = 0x0003e380, 872613175eSAlexander von Gluck IV SET_BOOL_CONST_end = 0x0003e38c 882613175eSAlexander von Gluck IV }; 892613175eSAlexander von Gluck IV 902613175eSAlexander von Gluck IV /* packet3 IT_SURFACE_BASE_UPDATE bits */ 912613175eSAlexander von Gluck IV enum { 922613175eSAlexander von Gluck IV DEPTH_BASE = (1 << 0), 932613175eSAlexander von Gluck IV COLOR0_BASE = (1 << 1), 942613175eSAlexander von Gluck IV COLOR1_BASE = (1 << 2), 952613175eSAlexander von Gluck IV COLOR2_BASE = (1 << 3), 962613175eSAlexander von Gluck IV COLOR3_BASE = (1 << 4), 972613175eSAlexander von Gluck IV COLOR4_BASE = (1 << 5), 982613175eSAlexander von Gluck IV COLOR5_BASE = (1 << 6), 992613175eSAlexander von Gluck IV COLOR6_BASE = (1 << 7), 1002613175eSAlexander von Gluck IV COLOR7_BASE = (1 << 8), 1012613175eSAlexander von Gluck IV STRMOUT_BASE0 = (1 << 9), 1022613175eSAlexander von Gluck IV STRMOUT_BASE1 = (1 << 10), 1032613175eSAlexander von Gluck IV STRMOUT_BASE2 = (1 << 11), 1042613175eSAlexander von Gluck IV STRMOUT_BASE3 = (1 << 12), 1052613175eSAlexander von Gluck IV COHER_BASE0 = (1 << 13), 1062613175eSAlexander von Gluck IV COHER_BASE1 = (1 << 14) 1072613175eSAlexander von Gluck IV }; 1082613175eSAlexander von Gluck IV 1092613175eSAlexander von Gluck IV /* packet3 IT_WAIT_REG_MEM operation encoding */ 1102613175eSAlexander von Gluck IV enum { 1112613175eSAlexander von Gluck IV WAIT_ALWAYS = (0<<0), 1122613175eSAlexander von Gluck IV WAIT_LT = (1<<0), 1132613175eSAlexander von Gluck IV WAIT_LE = (2<<0), 1142613175eSAlexander von Gluck IV WAIT_EQ = (3<<0), 1152613175eSAlexander von Gluck IV WAIT_NE = (4<<0), 1162613175eSAlexander von Gluck IV WAIT_GE = (5<<0), 1172613175eSAlexander von Gluck IV WAIT_GT = (6<<0), 1182613175eSAlexander von Gluck IV 1192613175eSAlexander von Gluck IV WAIT_REG = (0<<4), 1202613175eSAlexander von Gluck IV WAIT_MEM = (1<<4) 1212613175eSAlexander von Gluck IV }; 1222613175eSAlexander von Gluck IV 1232613175eSAlexander von Gluck IV /* Packet3 commands */ 1242613175eSAlexander von Gluck IV enum { 1252613175eSAlexander von Gluck IV IT_NOP = 0x10, 1262613175eSAlexander von Gluck IV IT_INDIRECT_BUFFER_END = 0x17, 1272613175eSAlexander von Gluck IV IT_SET_PREDICATION = 0x20, 1282613175eSAlexander von Gluck IV IT_REG_RMW = 0x21, 1292613175eSAlexander von Gluck IV IT_COND_EXEC = 0x22, 1302613175eSAlexander von Gluck IV IT_PRED_EXEC = 0x23, 1312613175eSAlexander von Gluck IV IT_START_3D_CMDBUF = 0x24, 1322613175eSAlexander von Gluck IV IT_DRAW_INDEX_2 = 0x27, 1332613175eSAlexander von Gluck IV IT_CONTEXT_CONTROL = 0x28, 1342613175eSAlexander von Gluck IV IT_DRAW_INDEX_IMMD_BE = 0x29, 1352613175eSAlexander von Gluck IV IT_INDEX_TYPE = 0x2A, 1362613175eSAlexander von Gluck IV IT_DRAW_INDEX = 0x2B, 1372613175eSAlexander von Gluck IV IT_DRAW_INDEX_AUTO = 0x2D, 1382613175eSAlexander von Gluck IV IT_DRAW_INDEX_IMMD = 0x2E, 1392613175eSAlexander von Gluck IV IT_NUM_INSTANCES = 0x2F, 1402613175eSAlexander von Gluck IV IT_STRMOUT_BUFFER_UPDATE = 0x34, 1412613175eSAlexander von Gluck IV IT_INDIRECT_BUFFER_MP = 0x38, 1422613175eSAlexander von Gluck IV IT_MEM_SEMAPHORE = 0x39, 1432613175eSAlexander von Gluck IV IT_MPEG_INDEX = 0x3A, 1442613175eSAlexander von Gluck IV IT_WAIT_REG_MEM = 0x3C, 1452613175eSAlexander von Gluck IV IT_MEM_WRITE = 0x3D, 1462613175eSAlexander von Gluck IV IT_INDIRECT_BUFFER = 0x32, 1472613175eSAlexander von Gluck IV IT_CP_INTERRUPT = 0x40, 1482613175eSAlexander von Gluck IV IT_SURFACE_SYNC = 0x43, 1492613175eSAlexander von Gluck IV IT_ME_INITIALIZE = 0x44, 1502613175eSAlexander von Gluck IV IT_COND_WRITE = 0x45, 1512613175eSAlexander von Gluck IV IT_EVENT_WRITE = 0x46, 1522613175eSAlexander von Gluck IV IT_EVENT_WRITE_EOP = 0x47, 1532613175eSAlexander von Gluck IV IT_ONE_REG_WRITE = 0x57, 1542613175eSAlexander von Gluck IV IT_SET_CONFIG_REG = 0x68, 1552613175eSAlexander von Gluck IV IT_SET_CONTEXT_REG = 0x69, 1562613175eSAlexander von Gluck IV IT_SET_ALU_CONST = 0x6A, 1572613175eSAlexander von Gluck IV IT_SET_BOOL_CONST = 0x6B, 1582613175eSAlexander von Gluck IV IT_SET_LOOP_CONST = 0x6C, 1592613175eSAlexander von Gluck IV IT_SET_RESOURCE = 0x6D, 1602613175eSAlexander von Gluck IV IT_SET_SAMPLER = 0x6E, 1612613175eSAlexander von Gluck IV IT_SET_CTL_CONST = 0x6F, 1622613175eSAlexander von Gluck IV IT_SURFACE_BASE_UPDATE = 0x73 1632613175eSAlexander von Gluck IV }; 1642613175eSAlexander von Gluck IV 1652613175eSAlexander von Gluck IV #endif 166